RU1824636C - Device for interruption of redundant computer system - Google Patents

Abstract

The invention relates to computing, in particular to interrupt service control devices, and can be used in real-time multi-channel redundant microprocessor systems. The aim of the invention is to expand the functionality of the device due to the priority service of applicants for interruption. The device contains identical channels, each of which contains a brand register, register. The invention relates to computer technology and can be used in multi-channel redundant microprocessor systems of real time. The purpose of the invention is to expand the functionality of the device by providing priority services to those who receive wok for interruption. Figure 1 shows the functional diagram of the device; figure 2 is a functional diagram of the block priority request. queries, current state register, interrupt inhibit trigger, interrupt inhibit trigger group, first and second interrupt triggers, request priority block, comparison circuit, majority element, AND element block, first, third and second AND elements, AND element group, first and second elements OR. a block of trunk elements, a pulse shaper, a group of control and information inputs of the device, a group of synchronizing inputs of the device, a group of outputs of the device interrupt vector, outputs of the interrupt enable, outputs of the channel interrupt, channel interrupt confirmation outputs, device interrupt outputs, channel interrupt input and confirmation outputs channel interruption; input 35 processor status words. The device is characterized by a wider range of priority service disciplines while maintaining speed and reliability. 2 ill. The device contains identical channels 1i-1n, each of which contains a mask register 2, a request register 3, a current state register 4, an interrupt inhibit trigger 5, a group of interrupt inhibit triggers 6i-6n, the first 7 and second 8 interrupt triggers, priority block 9 request, comparison circuit 10, majority element 11, block of AND elements, first 13, third 14 and second 15 elements AND, group of elements AND 16i-16n-i, first 17 and second 18 OR elements, block 19 trunk (Л С 00 N5 4 ABOUT ON

Description

elements, pulse shaper 20, group control 21 and information 22 device inputs, group clock input 23 of the device, group outputs 24 of the device interrupt vector, outputs 25 enable interrupt devices, outputs 26 interrupt channels, outputs 27 confirm interrupt channels, outputs 28 interrupt device , inputs of the first 29.1, second 29.2 and third 29.3 groups of bits of the group information input 22 of the device, inputs of the first and ninth 30.1-30.9 bits of the group control input 21 of the device, inputs of the first of 31.1 and 31.2 of the second group of bits synchronizing input device 23, input group 32i-32n-i interrupt channels, input group 331 ZZp-1 interrupt acknowledge channel input audio processor 35 status word.

The request priority block circuit contains request inputs 1-5, group of elements AND 6. group of elements AND 7, node 8 of request analysis, polling input, group of outputs of device 10, block of OR elements 11, priority blocks 12, blocks of elements BAN

13, decoder 14, priority register 15, sync.

The elements of the block are connected as follows. Inputs 1-5 are connected to the corresponding inputs of blocks 13 of the elements of the PROHIBIT. The outputs of the first block of elements FORBID are connected to the first inputs of block 11 of the elements OR, and the outputs of the second and third blocks (numbering from top to bottom) of elements FORBID are connected to the corresponding inputs of blocks 12 of priority, the first of which is used to implement priority with a cyclic, and the second - priority with dynamic service discipline. The inputs of priority register 15 are connected to the control outputs of the computer, and its outputs are connected to the inputs of the decoder

14, the outputs of which are connected to the inhibitory inputs of the blocks 13 of the element is FORBIDDEN. The outputs of the block 11 elements OR are connected: the first to the input of the first element AND group 7, the rest to the inputs of the corresponding elements AND group 6. The synchro input is connected to the synchro input of the second block 12 of priority, the remaining elements are connected, as shown in the description of autosw. USSR No. 1070553.

Linear discipline of priority service is implemented in that part of the device, which is known from Autosv. USSR No. 1070553, cyclic and dynamic disciplines are implemented on programmable logic matrices of type K 556 RT 1.

The operation of this priority block scheme is quite simple, sleep from the prototype and does not require additional understanding.

The elements of the device are connected as follows: the inputs of the first and second bits 30.1 and 30.2 of the group control input 21 of the device are connected to the first and second inputs of the first element And, the output of which is connected to the F-input of the block

19 trunk elements, the output of which is the group output 24 of the device interrupt vector, and the inputs of the third and fourth bits 30.3 and 30.4 of the group control input 1 of the device are connected to the R and C inputs of mask register 2, the output of which is connected to the second inputs of the block 12 AND elements, the first inputs of which are connected to the inputs of the first group of bits 29.1 of the group information input of the device 22, and the outputs are with the D-inputs of the 3 request register, the V-input of which is connected to the direct output of the trigger 5 of interrupt inhibit, and the outputs ; 3.1 - to the third inputs of the first, second and third elements AND 13, 15, 14; 3.2 - to the input of the priority block 9 of the request, the outputs of which are connected to the D-inputs of the block 19 of the main elements and the A-output of the comparison circuit 10, the B-input of which is connected to the output of the current state register 4, the D-inputs of which are connected to the third group of bits 29.3 of the group information input 22 of the device, and V- and C-inputs with inputs 5 and 6 of bits 30.5 and 30.6 of the group control input 21 of the device, respectively, input 7 of the bit 30.7 of the group control input 21 of the device is connected to the fourth input of the second element AND 15, the second input which connected to the output of the first OR gate 17 and an output - with a D-input of the first flip-flop 7 interrupts, direct output to which a key input of the pulse 20, whose output is connected to the S-input

interrupt inhibit trigger 5, the first input of the second OR element 18, is the channel interrupt input 32 and the channel interrupt output 26, the second input of the third 14 and the first input of the second 15 elements

and connected to the second bit 30.2 of the corpse of the new control input 21 of the device, the output of the third AND element 14 is the output 25 of the device interrupt enable, and the third input of the And 15 element is connected

to the direct output of the interrupt inhibit trigger 5, the inverse output of the current state register 4 is connected to the second input of the first element OR 17 and to the first input of the third element AND 14, eighth digit

30.8 group control-input; 21 devices are connected to the C-input of the first interrupt trigger 7, and the ninth bit 30.9 of the group control input 21 is connected to the R-input of the second interrupt trigger 8, the inputs of the first 31.1 bit of the group clock input 23 are connected to the sync inputs of the group of interrupt inhibit triggers, which are set according to the channel interrupt signals at the inputs 32i-32n-i, and the second bit 31.2 of the group clock input 23 is connected to the C1 input of the second interrupt trigger 8, the single output of which is connected to the first input of the majority element 11 and the corresponding input of the channel interruption confirmation group, the output of the majority element 11 is the device interrupt output 28, and the inputs of the majority element 11 from the second to the nth are respectively the inputs of the channel interruption confirmation group ЗЗг-ЗЗп-1 and connected to the outputs of the corresponding 8 channel triggers, inverse outputs of interrupt inhibit group 6 are connected to the first inputs of the AND elements of group 16, the second inputs of which are connected to the group of 32 channel interrupt inputs, and the outputs to the corresponding the input inputs of the second element OR 18, the output of which is connected to the input D1 of the second trigger 8 of the interrupt, the input of the second group 29.2 bits of the group information input of the device is connected to the O-input of the register 2 of the mask, the clock input of the trigger 5 of the interrupt inhibit is connected to the clock input of the register 4 of the current status, and the D-input of the interrupt inhibit trigger 5 is connected to the housing.

In the initial state, all memory elements are set to the zero state (inputs of the initial installation are not represented).

To bring the device into working condition, single signals are supplied to the inputs 30.2 and 30.5 of the group control inputs of the device 21. In addition, with the input 29.3 of the group information inputs of the device into the request registers 4 of all channels 1i (, n), the code of the current state of the program (at the beginning is the zero code), executed by the system, is written according to the clock pulse from input 30.6. By the same clock, the interrupt inhibit trigger 5 is set to the zero state. In this case, the zero signal from the output of trigger 5 allows the recording of interrupt requests in register 3.

The mask register 2 is set to zero by the signal from input 30.3. The same signal is used to reset the microprocessor

(class INTEL 8080 or K580VM80, K580VM80) multi-channel majority-redundant system.

After performing the indicated operations, the device is ready for operation.

The group inputs of the device 22 receive information signals promoted through all n channels of the redundant system. The code for the mask of interruptions is recorded in register 2 from input 29.2 by the signal from input 30.4, which corresponds to the output of a microprocessor system based on K580BM80. The mask code from the outputs of register 2 is sent to the inputs of the AND block 12, through which the interrupt request signals from the request inputs 29.1 are filtered. Moreover, any unmasked request signal is delivered to the D-inputs of the register 3 requests.

If there are no request signals in register 3, then the request priority block 9 closes the block 19 of the trunk elements, prohibits the generation of an interrupt confirmation signal through the OR element 17 and allows the generation of an interrupt enable signal at the output of the AND element 14.

Upon receipt of interrupt request signals from the outputs of the block of 12 elements

0 And they are stored in register 3. However, the request after that is not canceled from outputs 29.1, since register 3 is executed on latch triggers, and the information in register 3 will be stored only 5 after setting trigger 5 to one.

Information from the output 3.1 of register 3 is fed to the inputs of the request priority block 9, which, in accordance with the discipline of servicing set at the processor input 35 (in the order of receipt, is cyclical, dynamic) / 2 / selects the interrupt signal of the highest priority. The signal from the output 3.2 of register 3, generated when there is at least one request in the register, opens the And 13 element, the output signal of which opens the block 19 of the main elements and allows the system interrupt code to be transmitted to the 24 output channel. Also allowed

0, the operation of the And element 15 is triggered and the issuance of a permission signal from the output of the And element 14 to the output 25 of the device is prohibited.

When the block 9 priority of the request in a cyclic discipline or in order

5 receipts, its output code is also output to inputs A of circuit 1C, where it is compared with the code of the current program recorded in register 4. If the code from input A is larger than the code from input B of comparison circuit 10, then its output is issued

cash, which through the element OR 1 / and the open element AND 15 enters the D-input of trigger 7. Otherwise (dynamic discipline), the processor itself selects the request of the desired priority level and rewrites it according to the signal the microprocessor is ready, coming from input 35, through an open block of trunk amplifiers 19. In all other cases (discipline in the order of receipt, reverse), there is no signal at the output of circuit 10. Then the interruption confirmation signal can only occur if zero is written to the fourth bit of register 4 at input 30.5, since the inverse output of this bit is through an OR element 17 of the function. 10.

If there is a signal at the output of circuit 10 with the receipt of the enable signal from input 30.7 and a clock from input 30.8, the unit is written to trigger 7. The signal from the single output of trigger 7 through element 20 is fed to the input of trigger 5, which is set to unity. When com, it allows reception of new request signals to register 3 and trigger i 7 is prepared for reset to zero. Therefore, with the arrival of the next pulse from input 30.8, the trigger 7 is set to zero. Thus, the duration of the signal at the output of trigger 7 is determined by the period the impulses follow from input 30.8.

Shaper 20 generates a single pulse at output 26 after setting i jivirrpps 7 in a single state,

In order to exclude the possibility of double interruption on the same request, as well as interruption on requests of lower priorities with respect to the processed one, it is necessary after processing the interrupt signal generated from the outputs of 28 channels to write the code of the request processing program to the state register 4 as described.

If this is not necessary, then a zero code is written to register 4 by the signal from input 30.6. As a result, trigger 5 is reset to zero and the device is prepared to receive the next interrupt request.

After the generation of interrupt signals at the outputs of 26 channels, they arrive at the corresponding inputs 32i-32n-i of each of the remaining channels,

In each channel, interrupt signals from the remaining channels are fed to the D-inputs of the corresponding triggers and to the first inputs of the corresponding elements And 16-16n 1. In the absence of channel failures

signal., 1 from the inputs 32i 32n-i are supplied to the clock but intended to detect false output of the interrupt signal from the input 31.1. Therefore, 6i-6n 1

signals from the zero outputs open the And 16i 16n-i- elements. Thus, the channel output signal from the output of the body 20 or the remaining channels from the outputs of the And 16 | -) 6l 1 elements through the OR element

18 arrive at the D-input of trigger 8 I lo the interrupt polling clock signal from input 31.2 sets trigger 8 to the single state, the signal from the single output of trigger 8 through the J7 channel output

arrives at the corresponding inputs of the group of inputs ЗЗт-ЗЗп 1 from the main channels and then to the inputs of the majority element 11. The majority element I is triggered when there are interrupt signals in most channels and outputs an interrupt signal to the output of the device 28 to the corresponding system cable.

In the event of a failure due to freezing of channels, the signal

In addition, the moment of applying a clock pulse from input 31.1, through which the corresponding trigger from the group of triggers Pi-6lt i is set to one, and blocks the passage of

m signal through the corresponding element And groups hlsmenton And 16i 1Gn 1

For N: for and from i i n i i Simplify “tg ;,) to stop tearing apart computing systems containing n, beginning (where n is n ;, ropes), each of which includes d (. “soft register, query register, register held, interrupt prohibition trigger

two triggers regeere-gir, schema srlnneni, bpak 0 / JOMCHTOB AND, three elements AND,, is an OR element. block block international helmengop pulse shaper, interrupt inhibit trigger group, majority

an element, a group of AND elements, and in each channel, the first groups of control and information inputs of the device are connected with groups of the same input channel inputs, the first is an enable input, the first

reduction inputs, operating state, reset path, the second allowing in the “one and the second input of the installation of О О the group of control inputs of the channel are connected to the group of inverse inputs of the first AND element, the first direct input of the first AND element, the mask register reset input, the back input - hroshchizchii mask register, the input razsheni register current status, the synchronization inputs of the status register and trigger Zoppetz prreny enii

the first input of the second .nw-in- AND. chho house sync first hr pg-rg. HRC-- Ryvanip, respectively Pepp., W Prague and third subgroups of the category information inputs group k) NELN OODMN TP is responsible for the first group of inputs of the block of elements AND, the information group1; inputs of the current state registers, the output group of which is connected to the lerchol by the group of inputs of the comparison circuit, the group of outputs of the mask register is connected to the second group of inputs of the element block -.A. output; which is connected to the group of information inputs of the request register, the output of the first AND element is connected to the permission input of the trunk elements, the inverse output of the current state register is connected to the measured inputs of the first OR element and the third And element, the trigger information input the interrupt inhibit is connected to the bus of the zero potential of the device, the single output of the interrupt inhibit trigger is connected to the request enable register input and the inverse input of the second element AND, the output of the comparison circuit is connected with the second input of the first element OR, ПУУ-Д which is connected to the SECOND INPUT D), :: ln; : 0 (T9

And, the first input of the reduction is a pafio - .. the state of the control group the channel input is connected to the second direct input of the current element And and the third direct input of the second element And, the output of the query register is connected to the second direct input of the first element I. the inverse input of the third AND element and the fourth direct input of the second AND element, the output of which is connected to the information input of the first one: interrupt trigger, a straight line, the output of which is connected via the pulse former to the inverse single input of the interrupt inhibit trigger, inverse the outputs of the interrupt prohibition triggers of the group are connected to the first inputs of the corresponding AND elements of the group, the channel interrupt input group is connected to the information inputs of the interrupt prohibition triggers of the group and the second inputs

. l / i. .. P;.: MV vi. -jinrre-; / oP. .p.npv. ;; pr1-p-- --I (and; .i Cf: e; -ni i U i

i. G. “OG: M (:;. ЧО РРГ р-Д; 5 .pynnij C .IH.spOtly-. (. 1. V. Tro-stza chho / if ionni4; bit h rpYi ;;; i- r .y /. device is connected to cci-.: 0. 0. by the second trigger breakthrough. ФО Ma11ИО М-МЫЙ МУЛСОЙ УГЛЗНОПОЧ –ni whose moves are mostly given by the output of the second element v-3x0, 40 m confirmation of interruptions of the group UFN1; the fans of the channel A, the element L of the group are connected to the second element: and the second element I.PI, the output of the fifth interrupt fig. Is connected to the first input of the main line, the remaining ports of which are connected to the corresponding group inputs in odov interrupt acknowledgment channel output PFN Port Inon with soot0 ve gstvuyuschim gztorogo input group of OR block mchgisgrllnyh elements and outputs the output of third AND n- pyugs sootvetstpenno group pmhodov vector preryp &. nm and output resolution

5 device booting, the output of the main element B: -:, the channel is the output of the interrupt yciPOISTRZ, the output of the pulse retransmission is output by the right or left, the output of the second

0 triperp: ergs; and .y is the output under 1g er hdenir for channel termination, output: interruptions and confirmations of each channel are connected to the cooinet inputs of the same input groups of each of

5 other channels, characterized in that, d, in order to enhance the functionality of the device due to priority servicing of incoming transmissions, the device contains 0 ;; it contains an iTpv pnreTa request block, the first and second groups of information inputs of which are connected to the group of outputs of the register request and group of inputs of the status of the word device, group of outputs of the block

Request priority 5 is connected to the second group of inputs of the comparison circuit and the group of information inputs of the block of trunk elements

FIG. ABOUT..