SU1246769A1 - Discrete quantity flow generator - Google Patents

Description

1246769 control input of the register of registers.

connected nerator.

The probes are connected to the corresponding bit of the register control field.

The invention relates to computing and can be used as a simulator of a stream of discrete quantities during adjustment, simulation of the operation and operation of technical and software tools used to measure the flow of electric pulses in systems

automation experimental der

research and tests performed, in particular, on accelerators of nuclear particles and atomic reactors.

The purpose of the invention is to expand the functionality of the generator by providing the generation of a predetermined stream of discrete quantities with predetermined parameters, including non-stationary.

The generator contains the first memory block 1, the second memory block 2, the third memory block 3, the buffer register 4, the time register 5, the amplitude register 6, counters 7 and 8, element 9 ,. a digital-to-analog converter 10, an analog key 11, a generator of 12 clock pulses, a controlled frequency divider 13, a timer 14, and a control register 15.

Figure 1 presents the structural diagram of the generator; figure 2 - timer circuit; on fig.Z - scheme of the buffer register.

Output 16 of register 4 is the signal output of the generator time interval code, output 17 of register 6 is the signal output of the generator amplitude code, output 18 of register 5 is the signal output of the generator output pulse. The inputs-outputs 20-25 of the control register 15 are inputs-outputs of the generator, connecting it with sources of control actions.

The memory unit 1 is used to store codes representing the sequence of time intervals between the generated values characteristic of the desired stream.

whose installation input to the input of the mode setting is

n 5

j

Q

e

five

The memory unit 2 is used for storing codes indicative of the generated pulse amplitude distribution.

The memory unit 3 is used to store the frequency division factors of the clock pulse generator necessary for reproducing a non-stationary stream with a predetermined law of changing time intervals.

The buffer register 4 serves to store codes received from memory block 1 and transfer them to register 5 and to output 16 of the generator. In autonomous operation, it is used in counting mode as a source of codes, independent of block 1.

Register 5 of the time interval; serves to convert the code received from register 4 to the corresponding time interval.

Amplitude register 6 is used similarly to register 4, but to generate pulse amplitude codes.

Counters 7 and 8 are used to sequentially select the addresses of the memory cells of blocks 1 and 2. Element 9 serves to offset the address of the cell 1 of the memory relative to the cell address of the block 2 of the memory by one for each full pass of the second address.

Ayalo-digital converter 10 and an analog key 11 provide at the output of the pulse generator with an amplitude corresponding to the code received from register 6.

The generator 12 clock pulses sets the flow of periodic pulses of such a frequency that, after dividing, a stream of discrete values is provided at the output of the output switch of the discrete magnitude, the required intensity or frequency.

The controlled frequency divider 13 divides the frequency of the periodic pulses of the g-generator 12 in accordance with the division factor assigned to it.

Timer 14 through intervals set by the internal generator, codes, the high bits of which directly determine the high bits of the division factor of the divider 13, and the low bits serve as the address of the memory cell of the block 3, where the coefficient is stored; nta division for this divider.

The control register 15 permits communication of the elements of the flow generator with the sources of control actions.

The generator works as follows.

Before starting work, preparatory operations are performed. First of all, blocks 1, 2 and 3 of the memory are filled with data in accordance with the type of stream to be generated. For the systems of automation of nuclear physics research in the fields of medium and low energies, isotopic and activation analyzes, the possibility of simulating a flow of Poisson-type pulses with an amplitude distribution corresponding to a certain isotope (or mixture), as well as the intensity of or varying according to the half-life of the simulated isotope. It is of interest to be able to operate with both analog and digital values of the generated values.

In this case, the generator works as follows.,

To obtain a Poisson flow of output pulses, memory block 1 in random order records logarithms of natural numbers from 1 to N, where N is the memory capacity, and the codes are normalized so that the memory grid is optimally used. In block 2, codes characterizing the distribution of amplitudes are also recorded in a random (different) order. Finally, in block 3, a sequence of codes is recorded, which determines an exponential decrease in the flow rate by a factor of 2 when polling all the cells in which this sequence is written.

For generating a non-stationary flow, timer 13 (see FIG. 2), a sequentially connected pulse generator, is a binary

five

ABOUT

five

0 5 0 5

Q / j e

the counter (defining the lower bits of the timer) and the shift register (defining the higher bits of the timer) are set to a state in which the counter is reset to 0, whereby the address of the first cell of the memory block 3 is selected, and the timer register is written the code defining the base of the division factor for the controlled divider 13. The counter is reset by a signal coming in circuit 23, the register is set in circuit 23, and the generator timer is started in circuit 23 from the corresponding bit outputs of the control register 15, in which the necessary data is recorded through the inputs / outputs 20 from the source to the control actions. When generating a stationary stream, signal 23 is not used; When a non-stationary flow is generated by the signal from the overflow trigger of the shift register of the timer, one of the triggers of the control register 15 is activated, used as a flag for the end of operation of the entire device. The corresponding signal can be transmitted on the inputs-outputs

20c control device.

Also, at the beginning of operation (although this can be done at any time), element 9 is set to 24 by a signal from the corresponding bit of the output of register 15 so that the overflow signal of counter 8 blocks the pulse of the end of the interval, resulting in the ability to generate all amplitude values for each time interval value. With the opposite signal value in circuit 24, the effect of the overflow signal is canceled and a certain time interval will always correspond to each amplitude value.

The modes of generation of the output stream are set by a set of signals supplied from the corresponding, digital outputs of the control register 15 to registers 4 and 6 along chains

21 and 25. There are three possible variants for the generation of time intervals and amplitudes: the values determined by codes read from memory blocks,

1 and 2, constant values given by the source of control actions by means of register 15, and linearly

increasing values when registers 4 and 6 are running in the counting mode. The control circuit for register 4 (they are analogous for register 6) is shown in FIG. 3. The first variant is carried out in case parallel circuit is specified in circuit 21, circuit 21 is allowed to pass information from block 1. The second variant, if the signal in circuit 21j allows the passage of information from register 15 through circuit 21 ,. The third option is if the signal in the circuit 21 sets the pulse counting mode for the end of the time intervals received from register 5. Data is recorded in all cases by these pulses.

The flow generation starts from the source of control actions by a command coming through the inputs-outputs 20 to the register 15, as a result of which the signal on the circuit 22 starts the generator 12 and, if the generation of the non-stationary flow is set, the signal on the circuit of the internal timer generator 14. Clock pulses from the generator 12 is fed to the divider 13, and from the output with a frequency determined by

five

0

five

the division factor specified by this divisor is passed to the counting input of the register 5 of the time interval (a counter with a preset), which performs their recalculation until the moment of overflow. Since, in the initial state, 1 bits 1 are written to all bits of this register, the first impulse passes on its output. And since counters 7 and 8 are reset to O, this pulse reads the data from the first cells, memory blocks 1 and 2, into registers 4 and 6, respectively. The generated signals are transferred to inputs 16-19 of the generator, counters 7 and 8 set the address of the following cells of memory 1 and 2, the next time interval register 5 is preset. In the mode of generating linearly increasing values, the code change in registers 4 and / or 6 is executed by a pulse at the end of the interval when it enters the counting input. When generating constant time intervals and amplitudes, this pulse removes data passing to registers 4 and 6 along chains 21, (25).

fig.1

Compiled by S.Kurosh Editor T.Ivanova Tehred L.Oleinik

Order 294/1 Circulation 673 Subscription VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

KZ

2

Fi & W

Proofreader L. Pilipenko

Claims (1)

A DISCRETE VALUE FLOW GENERATOR containing an AND element, a memory block, a time interval register, an amplitude register, a controlled frequency divider, a buffer register, two counters, the amplitude register output being connected to the generator amplitude code output, and the buffer register output being connected to the information input of the time interval register , characterized in that, in order to expand the functional capabilities of the generator by ensuring the generation of a given stream of discrete quantities with specified parameters, including n stationary, a clock pulse generator, two memory blocks, a timer, a control register are introduced into it, and the output of the first counter is connected to the address input of the first memory block, the output of which is connected to the information input of the buffer register, the control input of which is connected to the discharge output of the register control field control, the output of the buffer register is connected to the output of the generator time interval code, the synchronization input of the time interval register is connected to the output of the controlled frequency divider the first input of which is connected to the output of the clock pulse generator, the input of setting the upper bits of the division factor of the controlled frequency divider is connected to the output of the higher bits of the timer, the output of the lower bits of which is connected to the address input of the second memory block, the output of which is connected to the input of the setting of the lower bits of g the division factor of the controlled frequency divider, the start inputs of the clock generator and the timer are connected to the corresponding outputs of the bits of the control register control field, to the input setting the discharge bit of which the overflow output of the temporary clock input of the timer is connected, the output of the interval register is connected to the AND element, the counting input counter, and the inputs of the synchronized output. amplitude and generator, th counter, the element is connected to the control field of the control register, the output of the element And is connected to the counting input of the first counter, the output of the second counter It is connected to the address input of the third memory block, the output of which is connected to the information input of the amplitude register, the control input of the amplitude register is connected to the corresponding bit of the control register control field, the installation input of which is connected to the input of the generator mode job.