SU1243148A1 - Device for cycle phasing of digital information receiver - Google Patents

Abstract

The invention relates to telecommunications. Cyclic time is shortened. phasing. The device contains the distributor 1, the element AND 2, the address switch (KA) 3, the trigger 4, the error detection block 5, the storage block (ST) 6, the decisive block 7 and the write-write signal generator (FSS) 8. During the duration of each clock cycle, the FSS 8 generates a write-write-to-switch signal, and the detected error block 5 calculates the error of the combination received at its B5sod. For each clock cycle in ST 6, the address determined by the position of the distributor 1 and the AC 3 is logically 1 if the combination syndrome calculated in block 5, which is located in error detection block 5, is equal to zero, and logical O, if this syndrome is not to zero. In the read operation mode of ST 6, a sequence of logical 1 appears at its output at its output, which through decisive block 7, trigger 4 and element I.2 arrive at the output of the device. The goal is achieved by the introduction of KA 3, ZB 6 and FSS 8. 2 Il: SL to 4 oo 00 Fig.1

Description

The invention relates to telecommunications and can be used in the transmission of data for cyclic phasing of discrete information transmission equipment using group corrective code. The purpose of the invention is to shorten the duration of cyclic phasing.

: FIG. Figure 1 shows the structural functional diagram of the cyclic phasing device of the discrete information receiver; in fig. 2- - timing diagrams for the operation of the device.

The cyclic phasing receiver of the discrete information contains the distributor 1, the AND element. Switch 3 of the addresses of the storage unit, trigger, 4, error detection unit 5, the storage unit 6, the decisive unit 7 and the write-read signal generator 8.

The device cyclic phasing receiver discrete information works as follows.

Information blocks (Fig. 2b) arrive at the error detection unit 5, and the clock pulses (Fig. 2 o) arrive at the clock inputs of the error detection unit 5, the distributor 1 and the signal generator 8 and the first input of the address switch 3. By

For each clock pulse, the dispenser 1 at the phased position relative to the received blocks (Fig. 2fe) generates signals (Fig. 25), and at the phased position - signals (Fig. 2 l). On

The duration of each cycle the driver of the write-match signals 8 generates a signal (Fig. 2), the error detection unit 5 calculates the syndrome of the combination received at its input. For each clock cycle in the storage unit 6, the address is determined by the position of the distributor 1 and the switch 3 addresses, logically 1, if the syndrome calculated in this cycle, which is in block 5 for detecting the failing combination, is O, and logical O, if this syndrome is not O. In the Filing mode (Fig. 2j), the memory block works. 6, the address switch 3 sequentially sets the address of the current information block (FIG. 2 d), the previous information block (FIG. 2 (j), etc.).

ten

is

20

25

thirty

35

40

45

50

35

482

(Fig. 2c, g), total (m-1). addresses of previous blocks of information. The value of i-n is determined by the duration of the analysis interval of the receiver synchronicity and in the example of operation of the device correspond to the interval, which is equal to the duration of four combinations. Thus, in the mode of combining the operation of the storage unit 6, each sequence at its output a sequence of logical 1 appears, corresponding to the zero syndromes of the previous blocks (Fig. 2i). The clock having the largest number of logical 1 reads corresponds to the end of the received information block and the output signal of the decision block 7 (Fig. 2, k) at the unphased position sets valve 1 to the common-mode position

(Fig. 2 l), and in the phased position confirms the common-mode position of the distributor 1 (Fig. 2 S). The output signal of the decision block 7 (Fig. 2k) through the trigger 4 generates a signal the beginning of the block, arrives at the output of the device through the element 2.

Fo) Mula Invention

 The cyclic phasing device of the discrete information receiver, containing an error detection unit, a distributor, a serially connected decision unit, a trigger and an AND element, to the second input of which the output of the distributor synchronization signal is connected, the information and clock inputs of the error detection unit being the corresponding inputs of the device, l and h and e, so that, in order to reduce the cycle phasing time, a storage unit, a write-read signal generator and a switch are introduced addresses remembering its block, while this clock input of the error detection block is combined with the corresponding inputs of the distributor, the switch of addresses of the storage block and the write-read signal generator, the output of which is connected to the input of the record-block of the recording block, the clock output of the distributor is connected to to another input of the address switch;

the mining block, the output of the decision block block is connected to the input; the river is connected to the installation input.

the melting unit, the output of the distributor block, the address outputs of the error blocking are connected to the bare and outputs of the switch of addresses to the information input of the memory block through the memory of the block.

Compiled by V. Evdokimova Editor N. Bobkova. Tehred M. KhodanychKorrektor E. Sirohman

 .m e ,, - .- ™. - --- - - - -

Order 3719/58 Circulation 624 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company; Uzhgorod, st. Project, 4

The main unit is connected to the input of the remote unit, the output of the unit is obfig. g

Claims (1)

Claim A device for cyclic phasing of a discrete information receiver, comprising an error detection unit, a distributor, a decisive unit, a trigger and an And element connected in series to the second input of which the output of the distributor synchronization signal is connected, the information and clock inputs of the error detection unit being the corresponding device inputs, characterized in that, in order to reduce cyclic phasing time, a storage unit, a write-read signal generator, and an address switch for memory unit, while the clock input of the error detection unit is combined with the corresponding inputs of the allocator, address switch of the storage unit and the driver of write-read signals, the output of which is connected to the write-read input of the recording unit, the clock output of the distributor is connected to another input of the address switch blinking unit, the output of the decisive unit is connected to the installation input of the distributor, the address outputs of which and the outputs of the address switch of the storage unit through the memory conductive block connected to the input deciding unit, an output error detection unit connected to the information input unit zapomi5 huge capacity. FIG. 2