SU1242948A1 - Device or controlling interruptions - Google Patents

Abstract

The invention relates to computing and can be applied in multiprogram, multiprocessor systems. The purpose of the invention is to simplify the device. This is achieved by introducing into the device an allocation unit of the lowest priority, a comparison element and a group of elements AND with the corresponding functional connections between them and the known device blocks. The device serves a system from n request sources (processors) in which an arbitrary set of tasks (programs) can be processed simultaneously. 2 hp f-ly, 3 ill. 1C 4ib 1C CO 4a 00

Description

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The invention relates to computing and can be applied, in particular, in multiprogram, multiprocessor systems.

The purpose of the invention is to simplify the device.

FIG. 1 is a schematic of an interrupt control device; in fig. 2 is a block diagram of the lowest priority block; in fig. 3 is a block diagram of priority selection of requests.

The interrupt control unit contains (Fig. 1) block 1 of the priority selection of requests, register 2 filled queues, block 3 determining the division of the senior unit, block 4 allocating the lowest priority, circuit 5 comparison and group 6 elements I. The inputs of block 1 are connected to inputs 7 query word device. The first group of drives

I connected to the installation inputs to o, and the second group of outputs to the installation inputs to 1 of the corresponding bits of the register 2 filled queues. The device also has an output of 8. The output of the register 2 is connected

with the input of the definition unit 3 is older than the unit, the output of which is connected to the output of the most priority non-empty device queue and to the first input of the comparison circuit 5. The second input of the comparison circuit 5 is connected to the first output of the lowest priority priority block 4, and the output is connected to the first inputs of elements AND of group 6. The second inputs of elements AND of group 6 are connected to the corresponding outputs of block 4, and the outputs are connected to the corresponding outputs of device 9 . The inputs of block 4 are connected to the corresponding inputs 10 of the priority of the device.

Block 1 priority selection requests (Fig. 2) contains a group

II of n triggers, where n is the number of requests, switch

12, the element AND-NO 13, the element 14 delay, the decoder 15 and the group of 16 elements AND-NOT. The first inputs of the elements of AND-NOT group 6 are connected to the higher-level input of the corresponding inputs 17 of the block, the second input to the input of delay element 14, the output of the OR-NOT 13 element and the gate input of the decoder 15, the inputs of the OR-NOT 13 element are connected to

2A2d482

mmpm outputs of the corresponding triggers 1 1 and to the corresponding control inputs of the switch 12, the information inputs of which are connected to

5 inputs of the lower bits of the corresponding inputs of the 17th block. The output of the delay element 14 is connected to the inputs of the installation in On the triggers I. The input of the installation in 1 trigger llj,

0 where j- l, 2, ..., p, is connected to the output of the AND-NOT 16j element and to the (+2) -th inputs of the remaining (nj) elements of the IS-NOT group 16. Switch output i 2 is connected to the information input S do decoder 15. Even and odd outputs of the decoder 15 are connected respectively to the first and second groups of outputs .18 block.

Selection block 4, the smallest at 20. priority (Fig. C) contains n counters 19, the switch 20, the delay element 21, the element OR 22, the generator 23 clock pulses. Counter input 1 9j

25 (j-l, 2, ..., n) is connected to the i-th output of the generator 23 clock pulses, and the information input is connected to the input 24j of the block and to the j-th information input of the switch

30 20. Loan output 1ka 19J is connected to the j-th control input of the switch 20, to the J-th input of the IPI 22 element and to the output 25j of the unit. The output of the element OR 22 is connected to the input

25 start generator 23 and the input element. 21 delays, the output of which is connected to the write inputs of the counters 19. B. The OUT of the switch 20 is connected to the output 26 of the extraction unit 4

40 lower priority.

The device works as follows.

The device serves a system from n request sources (processors) in which an arbitrary set of tasks (programs) can be processed simultaneously. Over time, the number of tasks in the system changes: if necessary, from outside

 - through each processor, a new task can arrive in the system (the set increases), after solving

the task is eliminated from the system set) v. Each task that newly entered the system is assigned a certain priority (it is possible to assign the same priority to several tasks). As tasks arrive for each of the possible priority values in the system, a queue for processing is generated. In this case, part of the queues may be empty if there are currently no tasks with these priorities in the system.

Each of the processors can handle any of the tasks. In this case, the processor is assigned the priority of the problem to be solved (current priority). In addition, each of the processors has its own, independent of the tasks to be solved, a constant priority (for example, for the first processor, the highest, for the n-th one).

The distribution of programs on processors using the proposed device is carried out as follows. When assigning tasks to the queue, the device, one of the inputs 7, receives the query word at the input of the block 1 priority selection of requests. When the incoming request is processed, block 1 sets one of the bits of the register 2 filled queues to one. The register width 2 is equal to the maximum number of possible current priorities in the system. If, when a task is removed from the queue, the queue appears empty, then the query word arrives at input 7, during processing of which unit 1 zeroes the register 2 corresponding to this queue. Thus, the presence of non-empty task queues in the system is reflected in a single state of bits. register 2.

If several requests are simultaneously received at the input 7 of the device, then in block 1, the request of the processor having a higher constant priority is processed first.

From the output of register 2, the code is fed to the input of block 3 of the definition of the highest unit, where it is converted into a code of the priority number of the non-empty queue with the highest priority. This code is fed to the input of the comparison circuit 5 and to the output 8 of the device. The second input of the comparison circuit 5 receives the code of the smallest current priority, produced by block 4. The input of block 4 from input 10 of the device receives the codes of the current priority of the processors. Block 4 passes only code to the input of circuit 5, com242948

corresponding to the lowest current priority, and a strobe signal operates on one of the outputs. If the smallest code is the current priority

5 is fed to the input lOj, then the strobe signal is fed to the input element And 6j. If the smallest current priority code is on multiple inputs 10, then the strobe

10, the signal is fed to the input of that element AND 6, the output of which is connected to the input of the processor with the lowest constant and current priorities. In the case when the code at the output of block 5 ka 2 turns out to be greater than the code at the output of circuit 5, a logical 1 signal appears, which is fed to the inputs of the AND 6 elements and allows the passing of the gating signal from one

20 of the outputs of block 4 to the output 9 of the interrupt device. On this signal, the processor with the lowest current priority stops processing the current task and starts processing

25 new tasks with higher priority. The queue code where the new task is located comes from the output 8 of the device. In this case, the processor produces the old problem

30 queue and removes from the queue a new task with issuing the corresponding requests at the input 7 of the device.

The block 1 priority choice for the promises works as follows.

One of the inputs 17J block receives the request code. The highest bit of the code arrives at the input of the element AND-NOT of group 16, and the lower bits - at the j-th information input of the switch 12. The output signal of the element AND-NO 16j sets the corresponding trigger 11j to one state. The signal from the direct output of the trigger llj enters the jth control input of the switch 12 and permits the passage of the lower bits of the request code through the switch 12 to the information input of the decoder 15.

50 The same signal is fed to the input of the element OR-NOT 13, the output of which is used for strobing. the decoder's messages 15, to prohibit a new request for AND-NOT elements 16,

55 and is also delayed by the delay element 14 by the time required to process the request, and resets the triggers II to the zero state.

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When a gated sieve appears, a signal appears at one of the outputs of the decoder 15. The signal on the Even outputs of the decoder is used to set certain bits of the register 2 filled queues to a single state, on odd outputs to the zero state.

At the simultaneous appearance of a request on several inputs 17 of the block, the input of the trigger 11 receives a signal only from the output of the AND-NOT element 16j with a smaller J, i.e. a request with a higher priority is being processed.

The unit of allocation of the lowest priority works as follows.

The current priority codes, among which the smallest is necessary, are received from inputs 24 of the block to the inputs of the corresponding subtractive counters 9 and informational inputs of the switch 20. The output codes of the delay element 21 put counters 19 into the input codes of current priorities. Loan signals at the outputs of counters 19 are missing. At the output of the element OR 22, a logical O signal is set, which permits the generation of time-shifted pulses at the generator outputs 23. The signal at the output of the delay element 21 disappears and the counter 19j, in which the code of the lowest priority is located, first reaches the zero state. Then, a loan signal is generated at its output, which goes to the corresponding control input of the switch 20 and permits the passage through the switch 20 to the output 26 of the code block of the lowest priority, followed by its output pulse 25j. The same signal through the element OR 22 is fed to the inputs of the delay element 21 and the generator 23. Generator 23 stops the formation of output pulses. After some time, a signal appears again at the output of the delay element 21, and the block starts working first.

Claims (3)

Invention Formula I. Interrupt control unit containing the priority selection block of requests, the register is filled with queues, the output of which 0 five , | (about ; five Ci connected to the input of the senior unit, whose output is connected to the output of the device’s highest priority non-empty queue, jth input of the query selection priority block (.,. n, where n is the number of requests) is connected to the jth input of the device query word, about t- - lich auschee e with. in order to simplify the device, it contains the lowest priority allocation unit, a comparison circuit and a group of I elements, whose outputs are connected to the interrupt outputs of the device, respectively, the first inputs of the And elements of the group are connected to the output of a comparison circuit, the first input of which is connected with the output of the senior unit, and the second input is with the first output of the lowest priority selection block, the i-th output of which (... n + l) is connected to the second input of the j-TO element AND group, the j-th input of the allocation block of the smallest prioritize and is connected to the j-th entry of the current priority ustroystvaj first and second outputs block selection priority group requests are respectively connected to the inputs of the installation in G 1 and k-ro razr5eda, rn, wherein m -.. the number of gradations filled priority queue register. 2. The device according to claim Ij, characterized in that the allocation unit of the lowest priority contains n counters, a switch, a delay element, an OR element, a clock generator, the j-th output of the clock generator connected, to the subtracting input of the jth counter, the information input of which is connected to the 1st input of the lowest priority block and to the jth information input of the switch, the jth control input of which is connected to the output of the loan of the jth counter, to the jth input element OR and is connected to the j-th output of the last block: its priority, the first output of which is connected to the switch output, the output of the OR element is connected to the start input of the clock generator, and through the delay element to the write inputs n of the counters. 3. The device according to claim 1, characterized in that the block is the routine selection of requests contains a group of n triggers, a switch, an OR-HP element, a delay element, a decoder and a group of N-N elements, the first input of the J-ro element of the N-group group is connected to the input of the higher bit-j-ro input The second input is with the input of the delay element and with the output of the OR-NOT element, the jth input of which is connected to the direct output of the j-ro trigger of the group and the JM control input of the switch, the jth information input of which is connected to the inputs of the lower bits Dov j-ro block input, respectively, switch output 429488 connected to the information input of the decoder, the gate input of which is connected to the output of the element OR NOT, the delay element of the delay element is connected to the input of the O trigger of the group, the input of 1 is connected to the output of the J-ro element of the NAND group, the output of the pth (... nl) element of the NAND group 0 is connected to (p + 2) -th inputs of all subsequent elements of the NAND group, even and odd outputs of the decoder are connected to the first and second groups, respectively 5 blocks. figure 1 .L.- - FIG. I -I Compiled by L. Sergeichuk Editor I. Nikolaichuk Sehred O.Gortvay Proofreader A, Zimokosov Order 3706/48 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4 .3