SU1524050A1 - Device for distributing tasks among processors - Google Patents

Abstract

The invention relates to computing and can be used as a hardware program manager, ready for execution, for distribution among processors of a multiprocessor system. The aim of the invention is to increase speed. The device contains six registers, eight counters, eighteen And elements, three multiplexers, seven flip-flops, ten OR elements, two comparison circuits, two decoders, five groups of And elements, two AND-NOT elements, three ILM-NOT elements, two elements AND-OR, switch group, priority node, OR group of elements, delay element. The device has the ability to distribute a specific task to a given processor with parallel viewing of the job queue and locking the distribution on this processor of tasks that can be executed on any processor of the system. 1 il.

Description

The invention relates to computing and can be used as a hardware program manager, ready for execution, for distribution among processors of a multiprocessor system.

The goal is to increase speed.

The drawing shows a block diagram of the device.

The device contains blocks 1 and 2 of memory, registers 3-8, counters 9-16, elements AND 17-34, signal output

35 devices, group of code inputs

36 devices, elements OR 37-46, generator 47 pulses, signal input 48 devices, triggers 49-55, multiplexers 56-58, circuits 59-60

comparisons, decoders 61 and 62, groups of elements I 63-67, group of code inputs 68 devices, elements AND-NOT 69-70, elements ШШ-НЕ 7 and 72, ele-ment ment 73, elements И-ШП 74 and 75 , switch group 76, device readiness input group 77, priority node 78, 1 SH 79 element group, device information output 80 group, device code output 81 group, device start input 82, device stop input 83, delay elements 84-86.

The device works as follows.

In the initial state of the device, registers 3-8 and counters 9-16 have

SL N5

4 About SL

the zero content, the flip-flops 49-55 are reset to zero, the I and 2 memory blocks are cleared (device reset circuit is not shown). At the same time, a single signal is set at the device output 35, allowing the distribution request codes to be sent to the device too much, at the outputs of the 80th group and at the exits of the 81 zero levels of the signals.

Before the device starts operating, inputs 68 enter into counter 16 a code for viewing the queue of tasks on a specific processor of the system.

The operation of the device begins with the arrival of a pulse start signal at the input 82 of the device, through which the trigger 54 is transferred to a single connection and the high level of the signal at its direct output enables the operation of the pulse generator 47.

The operation of the device consists in receiving from the source requests for the task distribution code, entering the request by attribute into one of the queues, and then issuing by the indication to one of the processors of the multiprocessor system. In parallel with the assignment of tasks; There is a process of previewing to a given depth of the job queue for a specific processor system. In the process of viewing

The bits of register bits 3 are received at the inputs of the same name of the SHSh 37 element, K11tpyry analyzes the sign of the request that was made and, together with the NE 73, AND 18-21, OR 38 and 39 elements, produces the conditions for switching the device to the next sync pulse. operations.

If, for example, a request arrives with a task that requires a particular processor to execute, then the unit levels of the signals at the direct output of Tpvirrepa 49 and the output of the OR element 37 are opened for the sync pulse of the AND 19 and AND 21 elements and the creation of the Fot condition to go to a single trigger state 50 corresponding to a job queue operation for a particular processor system. The sync pulse also arrives through the l-inH 38 elements on the sync input trigger 53 and checks for the presence of conditions for combining operations.

On the negative front of the clock pulse, the trigger 50 is translated into a single state and opens the elements AND 24, AND-HE 69, and also allows the feed to the inputs -t. LUX 58 through the multiplexer 56 addresses the upper limit of the job queue on a specific processor system, monitored using the counter i1, Well

Parallel signals are being generated at the address input for determining the selected processors, jobs from the job queue to any processor in the system.

Receiving the request consists in fixing the request code in the receiving register 3 with the subsequent creation of conditions for the operation of placing the request in the queue. The condition for a new request to the device is

Tiplexor 58 permits the passage to hell; the valid input of memory information block 1 from the inputs. The single signal from the direct output of the trigger 50 of the block 40 also goes through the element of the IPN-NE 71 to the access enable input of the memory 1 and creates conditions for modifying the queue. The sync pulse passes through the element AND-NOT 69 and the formation of a high signal level at a vz “t command Record, by which

course 35 of the device, meaning that the receiving register 3 is free and there is a place in the queue of requests. The request source, via device inputs 36, enters the request register 3 into the request code and places a single signal at the device input 48, which is stored on the negative edge of the clock in trigger 49. Switching to the one trigger condition 49 causes a zero signal at output 35 , receiving which, the source of requests removes a single signal from the input 48 of the device. The signals from the field signal at the address input of multiplexer 58 permit the passage to hell; the valid input of memory information block 1 from the inputs. The single signal from the direct output of the trigger 50 also stops through the IIS-NE element 71 to the access enable input of the memory unit 1 and creates conditions for modifying the queue. The sync pulse passes through the element AND-NOT 69 and forms

five

block 1 of the memory stores the contents of register 3, and in counter 9 the filling of the queue is corrected. The next clock pulse passes through the AND 24 element to the counting input of the counter 11 and corrects the upper limit of the queue. This signal, through the OR 40 element, flushes trigger 49 and clears the receiving register 3. According to the following clock pulse, trigger 50 is triggered and new requests are analyzed.

The request is received and entered into the queue of tasks on any processor of the system in a similar way, with the only difference that in the memory block 2 the contents of other bits of the register 3 are stored,

As tasks are accumulated in memory block 1, a pre-emptive queue mechanism is activated. The essence of which lies in the fact that the queue is scanned to a predetermined depth and the distribution blocking signals to the processors required by the selected jobs from the job queue to any processor of the system are generated. To start a viewing operation, the following conditions must be met: the viewing depth is not reached (there is a single signal at the signal output of counter 16}); the current border of the proj-yutr has not reached the upper limit of the queue (zero signal at the output of the comparison circuit 59); the current job is waiting in register 8 for the release of the required processor (zero signal at the output of the element 30).

As a result, a single signal is generated at the output of the AND-75 element, which enters the information input of the trigger 52 and converts it to a single state on the negative edge of the sync pulse (if the previous clock did not receive a job or received a task to any system processor), corresponding to the state of the sample job from the queue. At the output of the element And 22, a single signal is generated, which arrives at the address input of ml, pin 58 and permits the output to the address input of memory block 1 of the address of the queue view address generated in the counter 15. At the output of the element OR 71, a zero signal is generated, which is fed to the access enable input of memory 1 and allows operation with a job queue. The following clock pulse at the output of the AND 26 element produces a single signal, according to which a request from the outputs of memory block 1 is entered into the register 4 According to the following clock pulse, a single signal is generated at the output of the AND-OR 74 element, which enters the counting input of the counter 15 and corrects the current address view the queue, and also enters through the OR element 46 on the control input of the decoder-

torus 61. This signal at the output of the decoder 62, corresponding to the uni TapHo fy code of the processor number required by this task, generates a single signal that goes to the same unit input of register bit 7 and sets it to 1. The signal from the inverse output of this the bit enters the input of the element of the same name of group 65 and thereby blocks the participation of this processor in the distribution of tasks from the queue specified in any process of the system. The signal from the output of the element AND-OR 74 is also fed to the subtracted input of counter I6 and corrects the achieved depth of the queue view. According to the next clock pulse

0 at the output of the element 34 is formed by a single signal, which is fed to the reset input of register 4 and clears it, after which conditions are formed in the device for performing the next onepamiH.

To start the operation of issuing a task from the queue, the following conditions must be met: the queue is not empty (the signal on the second signal output is counter 9 (0)); the register of issue of the task is free (zero signal at the output of the element OR 45 (42)).

In this case, the issuance of a task from the echee of a task to any processor is completed in one cycle, and to issue a task from the queue of tasks to a specific processor, two cycles of operation are required.

0 In the first cycle, the job is sampled in register 4, and in the second clock cycle, the contents of register 4 are overwritten in register 8. If the specified conditions are met, an single signal is generated at the output of the AND-OR element 75 (AND 31), which arrives at the trigger input 52 (53) and on the negative front of the sync pulse translates it

0 in one state (if at the previous clock cycle the device did not receive new requests). Zero signals at the address inputs of multiplexers 58 (57) and 56 permit transmission to the address input of block 1 (2) of the memory of the lower queue boundary address generated in counter 13 (14). At the output of the element OR NOT 71 (72)

a zero signal is generated, which enters the access enable input of the memory block 1 (2) and enables operation with the job queue. According to the following clock pulse, at the output of AND 26 (27), a signal is generated, according to which a request from the outputs of block 1 (2) of the memory is entered into register 4 (5). In addition, for a job queue on any processor of the system, this signal corrects the filling of the queue. According to the following clock pulse, a single signal is generated at the output of AND 28 (29), which corrects the address of the queue boundary in the counter 13 (14). By the following clock pulse, trigger 52 (53) is reset to the initial zero state. For a job queue on any processor, the task queuing operation is completed on this and the job in register 3 is waiting for the free processor to be allocated to it. For the job queue, the specific processor in the next clock cycle performs the second stage of the task issuing operation, the conditions for which are the presence of the job B register 4 (a single signal on the course of the element Ш1И А1); Register 8 in boden (zero signal at the output of the ment OR 45).

As a result, at the output of the element 30, a single signal is generated, which is fed to the information, the trigger input 55 and on the negative front of the clock translates it into a single state (if a new request was not received at the previous clock cycle or a request was sent to any CPU). The following clock pulse at the output of the element And 23 forms a single signal, which is fed to the synchronous input of register 8 and records the CEC information from it) from the output of register 4. This signal also goes to the counting input of the counter 16 and the subtracting input of the counter 9, thereby correcting the depth view the queue and its filling. The entry in the register 8 causes the appearance of a single signal. At the output of the element OR 45, which enters the input of the element AND 34 and unlocks it. The following sync pulse at the output of the element And 34 forms a single signal, which arrives at the input of the reset of the register 4 and clears it after which the device is formed

Catch the length of the next operation.

 running a task distribution operation; The following conditions must be met for the processors: the task is registered in the issue register 8 (5) (a single signal at the output of the element OR 45 (42)); the required processor is free (a single signal at the output of the corresponding element And 63).

As a result, a single signal is generated at the pin of the element OR 49 (50). At the same time, a single signal on the output of the corresponding element AND 63 (67) of the pa3peii aei group is output to the required processor via one} Name switch / 6 groups of the code of the job number from the register 8 (5) output, According to the sync pulse at the output of the corresponding element 64 A group of a single signal is generated. This signal passes through the group IH1 79 of the same name to the signal output of the VO and gates the processor to receive the job number code from the output of group 81. The device allows the issuance of tasks on one clock cycle: from both queues, however, a task and a queue of tasks are sent to a specific processor by a delayed (on delay element 86) synchro loop to eliminate possible signal level fluctuations 5c at the output of the priority node caused by the discharge rate register 7. After issuing a task to the processor, register 8 (5) is cleared by the signal from the output of element 32 (33) which is delayed on element 84 (85), after which the E device is formed to proceed to the next operation.

The operation of the device observes the following priority of operations: the operation of receiving a request and placing it in a queue; the operation of fetching a request from a queue and transmitting it for distribution; the operation of anticipating the queue of tasks on a conventional processor system.

However, queuing allows you to combine within one clock cycle such operations as, for example, placing a request in a job queue on any processor of the system a) I and proactively viewing the queue of tasks on a specific processor of the system or placing the request in a queue of tasks on a specific processor of the system and

issuing the current zalann from this queue, waiting in register 8 release of the required processor.

In the future, the device operates as described.

Claims (1)

Invention Formula A device for distributing tasks to processors, comprising first and second memory blocks, first and second registers, nepBbrfi and second counters, first decoder, first And element, clock generator, 15 output of Fourth element And connected with the second input of the third component KCHI, the output of which is connected to the synchronous rotations of the fourth trigger, the output of the fifth element I is connected to the second 20 inputs of the second element OR, the output of which is connected to the first trigger, the group of outputs of the third counter is connected to the first group of information inputs of the first multiplexer and the first group of inputs of the first comparison circuit, the group of information inputs of the second multiplexer , 30, the pyrodor group of which is connected to the address inputs of the second memory unit, the output group of the fifth counter is connected to the second information group — UiOHfa.ix of the first multiplexer; and to the first input group of the second main circuit; the output group of the sixth counter is connected to the second group of information inputs. the second m multiplexer, the output group is the first multiplexer, the first and second delay elements, the nerves and the second OR elements, and the information outputs of the first memory block are connected to the information inputs of the first the register, the transfer output of the first counter is connected to the first input of the first element AND, characterized in that, in order to improve speed, it contains the third, fourth, fifth and sixth registers, the third, quarter and fifth, sixth, seventh and eighth counters , from the second to the eighteenth elements AND, from the third to the tenth elements OR, the first and second elements AND-NOT, the first: i the second elements l-LTH-HE, the first to the seventh triggers, the priority node, the first and second cxeNuj comparison, per-BbD i and the second elements I-OR, second and third multiplexers, ale nt NOT ggrety delay element from the first to fifth group elements li, or group of elements, the second decoder and a group of switches, the output of the first 40 multiplexer is connected to the perrnos. and the second counter is connected to the second input of the first element, whose input is the signal output of the device, the first group of code inputs of the device is connected to the group of information inputs of the syncro input of the second register, the first an output group of which is connected to the data inputs of the first memory block. the second and third groups of outputs of the first, “first decoder are connected to the one register connected to the inputs of the first OR element and to the data inputs of the second memory block, the outputs of which are connected to the information inputs of the third register, the first clock generator output is connected to the first inputs of the second and the third element And the synchronous input of the fourth register. 55 The main inputs of the bits of the registrar, the outputs of the second decoder are connected to the first inputs of the elements of the first and second groups, the output of the sixth element is connected to the address input of the third fan, the output of the seventh element is connected to the subtracting input of the first counter, with a sum of the left of the eighth Signal input device connected. with the information input of the first trigger, the inverse output of which is connected to the third input of the first and second input of the second And elements, the output of the second And element is connected to the first inputs of the second and third OR elements, the direct output of the first And trigger, the output of which connected to the first inputs of the fourth and fifth And elements and to the synchronous inputs of the second and third triggers. five group of information inputs of the third multiplexer, the group of outputs of which is connected to address rods of the first memory block, the group of input of the seventh connection counter 5a with the second group of information inputs of the third multiplexer and the second group of inputs of the first and second comparison circuits, outputs five The main inputs of the bits of the registrar, the outputs of the second decoder are connected to the first inputs of the elements of the first and second groups, the output of the sixth element is connected to the address input of the third fan, the output of the seventh element is connected to the subtracting input of the first counter, with a sum of the left of the eighth counter and synchronous input of the sixth register, direct output of the second trigger is connected to the address input of the first multiplexer and the first inputs of the eighth element AND, the first element NAND and the first element OR NOT, the output of the eighth element AND is connected to the counting input of the third counter and the first input the fourth element OR, the output of the first element IS is NOT connected to the summing input of the first counter and the write enable input of the first memory block; the output of the first element SH-NO is connected to the access enable input of the first memory block directly The third output of the third trigger is connected to the address input of the second multiplexer and to the first inputs of the ninth AND element, the second AND-NOT element and the second tUTM-HR element, the output of the 9th And element is connected to the counting input of the fourth counter and the second input of the fourth element OR whose output is connected to zero in: {ode of the first trigger and the reset input of the second register, the output of the second element I – CHE is connected to the oyMMipyiouutM input of the second counter and the resolution input, recording the second memory block, the output of the second element IPI is NOT connected to the input BTOpoi access block o memory block, the output of the first element OR is connected to the second element I, the output of the second trigger, and the input of the element NOT, the output of which is connected to the second input of the fourth element And and the information input of the third trigger, the second the output of the clock generator is connected to the first inputs of the seventh, tenth, and eleventh socket. And it is connected to the second inputs of the first and second elements AND, NOT, a third the clock generator output is connected to BTOIJUMH of the eighth and ninth e And, with the first inputs of the twelfth and eleventh element of the AI with the first input of the first: AND-OR element, the first group of outputs of the first register connects to the information inputs of the sixth register, the second group of outputs of the second register is connected to the inputs of the fifth IS and the inputs of the first decoder the outputs of the third register are connected to the inputs of the sixth element OR and the first III groups of information inputs five 0 five 0 five 0 five 0 five group switches, a group of device ready inputs is connected to a group of information inputs of the fourth register, the outputs of which are connected to the second inputs of the corresponding AND elements of the first group and the first inputs of the corresponding AND elements of the third group whose outputs are connected to the inputs of the priority node, the outputs of the priority node are connected to the first inputs the corresponding elements of the fourth and fifth groups, the direct output of the fourth trigger is connected to the first input of the sixth element I, to the second inputs of the tenth ele enta AND, the first element OR NOT, the first element AND-OR and with the second direct input of the twentieth element AND, the direct output of the fifth trigger is connected to the second inputs of the second element OR-NOT, the eleventh and thirteenth elements AND, the output of the dec of the element And is connected to the synchronous input of the first register, the output of the eleventh element And is connected to the synchronous input of the third register and the subtractive input of the second counter, the outputs of the elements And of the first group are connected to the first control inputs of the corresponding switches of the group and the corresponding the inputs of the seventh OR element, the outputs of the AND elements of the second group are connected to the zero inputs of the corresponding bits of the fifth register and the first inputs of the corresponding OR elements, the outputs of the AND elements of the fourth group are connected respectively to the second inputs of the OR elements, the outputs of which are a group of information outputs the devices, the outputs of the elements And the fifth group are connected to the corresponding inputs of the eighth element OR and the second control inputs of the corresponding switches of the group, the outputs which are groups of code outputs of the device, the first group of outputs of the sixth register is connected to the inputs of the second decoder and inputs of the ninth OR element, the second group of outputs of the sixth register is connected to the second groups of information inputs of the group switches, the output of the twelfth element I is connected to the counting input of the fifth counter , with the third input of the first element AND-OR, and with the first input of the tenth element OR element I is connected to the counting input of the sixth counter, the second group of code inputs of the device is connected to the information inputs and the synchronous input of the eighth counter, the output of which equals zero is connected to the first direct input of the second element AND-OR, the output of equality to zero of the first counter is connected to the second right The second input of the second element, AND-OR, the device start input is connected to the single input of the sixth trigger, the device stop input is connected to the zero input of the sixth trigger, the forward output of which is connected to the control input clock generator, the first output of which is connected to the synchronous input of the seventh trigger, the direct output of which is connected to the second direct input of the seventh element AND, the output of the fifth element OR is connected to the direct input of the fourteenth element AND, the output of which is connected to the information input of the seventh trigger and with the first and second inverse inputs of the second element AND-OR, the output of the sixth element OR is connected with the inverse input of the fifteenth element AND, and with the second inputs of the elements AND of the fifth group, the output of equality to zero second The first counter is connected to the direct input of the fifteenth element AND, the output of which is connected to the information input of the fifth trigger, the output of the seventh element OR is connected to the first input of the sixteenth element AND, the output of which is connected to the second inputs of elements AND of the second group, and through the first element beyond - 0 0 50 holders with a reset input of the sixth register, the output of the eighth element OR is connected to the first input of the seventeenth element AND, the output of which is connected to the second inputs of elements AND of the fourth group and through the second delay element to the reset input of the third register, the output of the ninth element OR inputs of the seventh, twelfth and fourth elements And, with the second input of the sixth And element with the first input of the eighteenth And element, with the fourth input of the first and the third input of the second OR-AND element and with the control input The second decoder, the output of the first comparison circuit is connected to the fourth inverse input of the second AND-OR element, the output of which is connected to the information input of the fourth trigger, the output of the second comparison circuit is connected to the fifth input of the first AND-OR element, the output of which is connected to the counting input of the seventh counter , with the subtracting input of the eighth counter and with the second input of the tenth OR element, the output of which is connected to the control input of the first decoder, the fourth output of the clock generator is connected to the blue output the first trigger, with zero inputs of the second, third, fourth, fifth, and seventh triggers, with the second inputs of the seventeenth and eighteenth elements And through the third delay element with the second input of the sixteenth element And, the output of the eighteenth element And connected to the reset input of the first register. five 0 "about S--: 1-01 g  ABOUT . about w3  ; j  ZO