SU907551A1 - Multi-microprocessor system - Google Patents

Description

And: the acquisition relates to computing and can be used in the design of multi-microprocessor systems.  Homogeneous multimicroprocessor systems are known that contain memory blocks and microprocessor blocks, addresses and data connected by buses and connected to a bus switch.  In homogeneous multi-microprocessor systems, the functions of the controller and system primitives are implemented as a set of operating system (OS) programs and can be performed by any microprocessor unit 1 and 2.  The disadvantage of these systems is the time-consuming management and synchronization of the processes.  The closest to the technical essence of the invention is a multi-microprocessor system containing a group. microprocessors and a resource allocation microprocessor connected by buses to memory blocks and an I / O subsystem, the control outputs of the resource allocation microprocessor connected to the control inputs of the group of executive microprocessors whose outputs are connected to the resource processor microprocessor inputs.  The resource allocation microprocessor here performs the functions of the traffic controller 3.  A disadvantage of the known system is that there is a need to implement a switch of type each with each of the microprocessor-based executives in order to organize the quick exit of microprocessors from the binding locks on the resources.  In addition, the implementation of system primitives using the universal instruction set used by the microprocessor processors leads to significant time losses in executing the process control function, which causes a decrease in the performance of the system as a whole.  The purpose of the invention is to increase system performance.  The goal is achieved by the fact that in a multi-microprocessor system containing an execution microprocessor device, a microprocessor resource allocation unit, a microprocessor input-output unit, a memory communication device, a control microprocessor device including a microprocessor synchronization unit, the first. control outputs, address outputs and informational inputs-outputs of which are connected respectively to the control input, via the address bus to the address input and via the data bus to the information input-output of the storage device, switching unit, including the register for npi coB, first groups of elements AND, OR elements, NOT elements, two OR elements, two NOT elements, AND element, the output of which is connected to the first control input of the microprocessor I / O unit, the second and third control inputs and the second, third and fourth equal outputs of which are connected respectively to the second and third control outputs and to the first and second control inputs of the communication device with the memory and to the input of the first digit of the request register, the output of the first bit of the register of the switching unit requests is connected to the first inputs of the element And the first element OR of the switching unit, the output of the first element OR of the switching unit is NOT connected to the synchronization input of the request register via the first element And the elements of the first group are connected to the first control input an executive microprocessor device, the second control input and the second and third control outputs of which are connected respectively to the second control output and the first control input of the microprocessor resource allocation unit and to the inputs of the first group of request register bits, the outputs of the last digit of the first group bits and the last bit of the second group of bits of the register of the switching unit request are connected to the first inputs of the second OR element and the first OR element, respectively ruppy switching unit, the first inputs of the remaining elements OR of the first group are connected to the outputs of the remaining bits of the first group of the query register, the first and second inputs of elements AND of the first group of the switching unit are connected respectively to the outputs of the bits of the first group of the query register and through the elements of the first group NOT the outputs of the elements OR of the first group, the output of each previous element OR of the first group of the switching unit is connected to the second input of the subsequent element OR of the first group, and the output of the last element OR the first group is connected to the second input of the second OR element of the switching unit, the output of which is connected to the second input of the first OR element and through the second element HE with the second input of the AND element of the switching unit, the third control output and the second control input of the microprocessor resource allocation unit are connected respectively to the input and the output of the second bit of the register of requests, the microprocessor unit for creating the process is additionally introduced into the control microprocessor device, the microprocessor unit for destruction No process, microprocessor message transfer unit, microprocessor message receiving unit, two control registers, seven OR elements, and the second group of OR elements, NOT elements and AND elements, the first control inputs and outputs, the second control outputs , address outputs and information inputs / outputs of microprocessor units for creating a process, destroying a process, sending a message, receiving a message are connected respectively to the output of the second group of elements I, to the input of the second group of bit s of the query register with the control input via the address bus with the address input and through the data bus with the information input-output of the storage device, the first and second control inputs and the second and third control outputs of the microprocessor synchronization unit are connected respectively to the output of the second group of elements And , with the output of the first element OR of the controlling microprocessor device, with the input of the second group of bits of the register of queries, with the input of the first register, the third and fourth control outputs, and the second and third The first control inputs of the microprocessor unit for creating the process are connected respectively to the first inputs of the first and second OR elements of the controlling microprocessor device with the output of the third OR element and the first output of the first register, the second, third, fourth and fifth outputs of which are connected respectively; with the third control input of the microprocessor resource allocation unit, with the first inputs of the fourth and. the fifth OR elements, with the second control input of the microprocessor process destruction unit, the third control input, the third fourth, fifth, sixth, seventh control outputs of which are connected respectively to the first output of the second register, with the first control input of the microprocessor resource allocation unit , with the second input of the second element OR of the control microprocessor device, with the first inputs of the third and sixth elements OR, with the second input of the first element OR of the control microprocessor units, the third input of which is connected to the second output of the second register, the input, the third, fourth and fifth outputs of which are connected respectively to the fourth control output of the microprocessor resource allocation unit, the second inputs of the third and sixth elements OR, to the first input of the seventh element OR, the second input of which is connected to the third control output of the microprocessor transmission unit of the message, the second and third control inputs,. The fourth, fifth and sixth control outputs of which are connected respectively to the outputs of the fourth and sixth elements OR, to the third input of the second element OR to the control microprocessor device, to the fourth input of the first element OR to the control microprocessor device, to the second input of the fifth element OR, the output of which is connected to the second control input of the microprocessor receiving unit for communication 16, the third control input, the third, fourth, fifth, sixth and seventh control outputs of which are connected to Responsibly with the output of the seventh element OR, with the third inputs of the third and sixth elements OR, with the second input of the fourth element OR, with the fifth input of the first and with the fourth input of the second elet-ieHtOB OR control microprocessor device, the output of the second element OR of the control microprocessor device connected to the fourth control input of the micro processor resource allocation unit; the output of the last bit of the second group of the query register is connected. with the first input of the AND element of the second group, the outputs of the remaining bits of the second group of the query register are connected to the first inputs of the remaining AND elements of the second group and the first inputs of the OR elements of the second group, the second inputs of the AND elements. The second group is connected to the outputs of the corresponding NOT elements of the second group, the input of the first element is NOT the second group connected to the output of the second bit of the query register, the inputs of the remaining elements of the second group are NOT connected to the outputs of the corresponding elements OR of the second group, the output of each previous element OR the second group is connected to the second input of the subsequent element OR of the second group, the output of the last element OR of the second group is connected to the second input of the first element OR of the first group.  FIG.  1 shows a block diagram of a multi-microprocessor system; in fig.  2 is a block diagram of an executive microprocessor device; in fig.  3 microprocessor unit structure; in fig.   - microprocessor node structure; in fig.  5 structure of the microprocessor interrupt assembly node; in fig.  6 — memory block diagram; in fig.  7 structure of the memory block of the memory device; in fig. 8 structure of the switching unit; in fig. 9, the memory circuit block diagram of FIG. 10 shows the structure of a memory management unit; in fig.  11 is a block structure of memory storage device registers; on.  FIG.  12 is a block diagram of a control microprocessor device.  7 The system includes an executive microprocessor device 1, a memory device 2, a switching unit 3, a microprocessor resource allocation unit, a microprocessor I / O unit 5, a memory communication device 6, a control microprocessor device 7.  Executive microprocessor device 1 is designed for processing user and system processes.  The storage device 2 is intended for storing user programs and operating system programs designed as user and system processes, for storing system tables, lists and synchronization semaphores, as well as for accumulating execution results.  Switching unit 3 is intended for organizing priority access of system units to storage device 2.  The microprocessor unit 4 for resource allocation is intended for assigning processes to the microprocessor-controlled device. The microprocessor unit 5 for input-to-water is intended for controlling information input-output instructions.  The device 6 for communication with the memory is intended for the organization of a direct access mode for the exchange of data arrays between the storage device 2 and external devices (in FIG.  1 not shown).  Control microprocessor device 7 is designed to perform the functions of system primitives.  The first control outputs, information inputs-outputs and address outputs of the executive microprocessor unit 1, the microprocessor block 4 of resource allocation, the microprocessor block 5 I / O, the device 6 communication with the memory and the control microprocessor unit 7 are associated respectively with the control via the data bus 8 with information input-output and bus 9 addresses with the address input of the storage device2.  The third control outputs of the executive microprocessor unit 1 and the microprocessor distribution unit of the resuo 18 sockets, the microprocessor input-output unit 5 and the control microprocessor device 7 are connected to the first to fourth inputs of the switching unit 3, respectively, and their control inputs are shown respectively by lines with the first to fourth outputs of the switching unit 3.  Executive microprocessor device 1 contains Executive microprocessor units 18. 17 18. n and register 19 (fig. 2).  Executive microprocessor units I8,1rl8. n are designed to execute commands for user and system processes being processed.  Register 19 is designed to receive and store interrupt codes of microprocessor execution units 18. 1-18. P.  Executive microprocessor unit 18. K contains a group of microprocessor nodes 20. 1720. 8, the micro-command address register 21, the micro-command memory node 22, the micro-command register 23, the interrupt node 2, the expansion register 25 (phi-g. H).  Microprocessor nodes 20. 1g20 8 are intended to perform arithmetic and logical operations, as well as shift and transfer operations.  The micro-command address register 21 is intended to form the micro-command address next to the one being executed, as well as to gate the interrupt 2 on input 26.  The micro-command memory node 22 is designed for storing and issuing micro-commands and contains a matrix of storage elements.  Node 22 of the microinstructions memory of each executive microprocessor unit 18. 1t-18. A firmware of processing the call to the other operating system, processing the interrupt from the microprocessor block k of resource allocation and interpreting the received instruction set is recorded.  The micro-command register 23 is intended to receive micro-command codes from the micro-command memory node 22 and generate control signals to all the nodes of the execution microprocessor unit 18. TO.  9 Interrupt node 2t is designed to prioritize the selection of interrupt requests and identify the source of the interrupt.  Expansion register 25 is intended for storing, storing, and issuing an address of memory blocks of memory device 2.  Microprocessor node 20, i is a two-bit processor section and contains memory address register 27, accumulating register 28, operation element 29, decoder 30, first switch 31 second switch 32, memory element 33, first output buffer 3, second output buffer 35 (FIG. .  The memory address register 27 is designed to form and store an address when accessing the memory device 2.  The accumulation register 28 is designed to store the results of the operations of the operating element 29 and contains two triggers.  Operational element 29 is designed to perform arithmetic and logical operations and contains a group of logical elements AND, OR, NOT.  The decoder 30 is designed to convert the state of the field of functions of microinstructions into a sequence of control signals of the elements of the microprocessor node 20.  i.  The first and second switches 31 and 32 are designed for switching CI - lines at the inputs of the operating element 29.  The memory element 33 is intended to temporarily store the results of operations performed by the operation element 29, and contains a group of two bit registers.  The first output buffer Z is designed to connect the output of the memory address register 27 to the address bus 9 and contains a group of logic elements.  The second output buffer 35 is designed to connect the output of the accumulating register 28 to the data bus 8 and contains a group of logic elements.  Interrupt node 2t contains the encoder 36, the current priority register 37, the compare item 38, the request register 39 (FIG. five).  1 The encoder 36 is designed to generate an interrupt code and generate an interrupt acknowledgment signal. The current priority register 37 is for storing the priority code of the program being executed.  Comparison element 38 is intended to compare the current priority code and the interrupt request code.  Request register 39 is for storing requests from interrupt sources.  The memory device 2 contains a memory block address decoder kQ and a group of blocks l. lftl. m memory (fig. 6).  The memory address decoder kO is intended to convert the memory block address code into memory block trigger signals.  Al memory blocks. . m are intended for recording, storing and reading information.  The memory unit 41 comprises a decoder 42, a first trigger, an And k element, a second trigger 5, a first, second, third and fourth delay elements, a group of storage elements 50 (FIG. 7).  The k2 decoder is designed to convert the address code into the sample signals of the storage elements.  The first trigger 3 is intended to form a storage signal, the second trigger 45 is intended to form a write / read signal for a group of storage elements 50.  The group of storage elements 50 is designed to store information and is a matrix of semiconductor crystals.  Switching unit 3 contains the first group of elements And 51. . p, the element And 52, the second group of elements And 53. 1-53. 5, the first group of inverters 54. 15+. p, the first inverter 55, the second group of inverters 5b, 1t5b. 5, the second inverter 57, the first group of elements OR 58,175V. p, the first element OR 59, the second group of elements OR 60,1-f60, the second element OR 61, the register 62 requests (FIG. 8) The Request Register 62 is for receiving and storing requests for accessing shared memory.  The first, second, third and fourth inputs of the switching unit 3 are connected respectively to the outputs of the first group of elements I 51. 1r51. n, through the lines l4,1flA. n to the high bit of the register of b2 queries, to the output of the And 52 element, and through lines 17. . 5 to the moves of the second group of elements And 53.  And 53. five.  The first entrances of the pei group of elements I 51. . n, the element And 52 and the second group of elements And 53. 1t53. 5 are connected respectively to the outputs of the first group of inverters 5. 1t5. p, with the output of the first inverter 55 and with the outputs of the second group of inverters 5b. 1g5b. five.  The number of elements and 51. 1t 51.  P; 52.  53. 1 33. 5 number of inverters 5. 1t5. P; 55.5b. Tt5b. 5 and the number of elements OR 58L-58. P; 59.60. 1460. 4, 61 are one less than the number of register bits of the b2 query.  Each bit of the register b2 of queries, except the most significant bit, is associated with the second input of the corresponding element AND 51. 1r51. P; 52.53. If53. 5 and with the first input of the corresponding element OR 58,1t58. P; 59.60. 1-60. .  61.  The highest bit of the source of 62 voltages is connected to the input of the inverter 56. 1 and to the second input of the element OR 60. one.  Element output OR 58. I of the first group is connected to the input of the inverter 5. i of the first group and with the second input of the element OR 58. n The output of the element OR 58, which is connected with the second input of the first element OR 59, whose output is connected to the input of the first inverter 55 and to the BtopOMy input of the second element OR b1.  Item output OR 60. i is connected to the input of the inverter 5b.  i + 1 and with the second input of the element OR 60. i + 1.  Item output OR 60. 4 is connected to the second input of the element OR 58. one.  The output of the second element OR 61 is connected via the second inverter 57 to the control input of the register of 62 queries, the installation inputs of which are connected respectively to the first input through the lines 10.1-g 10. P to the second entrance, to the third entrance and through lmnii 13. 1T13. 5 to the fourth input unit 3 switching.  The synchronizing input of the register 62, after passing through the line 2b, is connected to the output of the clock signal generator (in FIG. 8 not shown).  The structure of the microprocessor, the resource allocation unit k and the microprocessor input-output unit 5 is similar to the structure of the executive microprocessor unit 18. K represented in FIG. H.  In node 22 of the microprocessor memory of microprocessor resource allocation unit C, a microprogram is recorded that performs the system functions of the controller who assigns processes for processing in the microprocessor execution device 1, as well as the interrupt processing firmware from the execution microprocessor 1 and control microprocessor 7.  In node 22 of the microinstructions memory of the microprocessor I / O unit 5, a microprogram is recorded that implements I / O operations as well as an interrupt handling microprogram from the memory communication device 6.  The memory device 6 comprises a write address counter 63, a write length counter 64, an operation mode register 65, a switch 66, a register b7 block, a control block 68, a switch 69, a request register 70, an encoder 71, a buffer node 72 (FIG. 9).  The write address counter 63 is designed to store and modify the addresses of the transmitted data.  The record length counter 64 is designed to store and modify the length codes of the transmitted records.  The operation mode register b5 is for indicating the direction of data transmission.  Switch 66 is designed to transmit data from the data bus 8 in two directions.  The block b7 of registers is intended for storing, writing and reading addresses of records, codes of lengths of records and codes of transmission modes.  The control unit 68 is designed to form a time sequence of signals controlling the nodes of the memory communication device 6.  The switch 63 is designed to switch signals at the input of the register block 67 and contains AND, OR, NOT logic elements.  - Request register 70 is designed to record and store interrupt requests from external devices at input 73.  The encoder 71 is intended to identify sources of interrupt requests.  The output 74 of the communication device 6 is connected to external devices.  The control block 68 contains the first trigger 75, the first element AND 7b, the first element OR 77, the second element AND 7-8, the second trigger 79, the third element AND 80, the decoder 81, the counter 82, the second element OR 83 (FIG. ten).  The first trigger 75 is intended.  To normalize the enable signal of the mode — Transmit.  The second trigger 79 is intended to form the enable signal of the Channel Programming mode.  The decoder 81 is intended to form a Read, Write +1, Reset signal.  Counter 82 is used to form a sequence of control codes.  Block 67 of the registers contains the first, second and third decoders 8 86, the first group of registers 87. 1t 87-8 and the second group of registers 88. 1 88. 8 (FIG. eleven).  Decoders are designed to convert the register address codes into signals Read, Write Reset.  The first group of registers 87. .  intended for storing addresses of records.  The second group of registers 88. 1t88.  designed to store codes for records.  The control microprocessor device 7 contains a microprocessor synchronization unit 89, a microprocessor processing unit 90, a microprocessor processing destruction unit 91, a microprocessor communication transfer unit 92, a message reception microprocessor unit 93, the first register 9, the second register 95, the first to seventh elements OR (FIG. 12).  Microprocessor block 89 synchronization. designed for synchronizing microprocessor units 9093 when accessing system semaphores.  The structure of the microprocessor unit 89 synchronization is similar to the structure of the Executive microprocessor unit 18. K represented in FIG. H.  At node 22 of the micro-command memory of the microprocessor synchronization unit 89, a microprogram view frame is recorded — system indicators are semaphore based on the interrupt signals.  The microprocessor unit 90 created the process, the microprocessor unit 91 of the process destruction, the microprocessor unit 92 for transmitting the message, and the microprocessor unit 93 for receiving the message, respectively, are designed to perform system functions for creating and destroying processes, for transmitting and receiving messages.  Their structures are similar to the structure of the executive microprocessor unit 18. K represented in FIG. H.  Node 22 of the microinstructions memory of each microprocessor unit 90t-93 contains the interrupt handling microprogram and the microprogram of the corresponding system primitive.  The first second 95 registers are designed to receive and store interrupt reason codes.  The system works as follows.  The multi-microprocessor system handles both independent sequential tasks, and tasks whose execution algorithms allow parallelization.  Job processing is performed in batch mode with multiprogramming under the control of the operating system.  In multimicroprocessor systems operating in multiprogramming multiprocessing mode, at a given time period in service there is a package of tasks, each of which is represented by a set of processes.  The concept of a process (as a basic processing unit) is used in computing as a necessary means of representing tasks performed simultaneously and in parallel and competing with each other in accessing shared resources within a computational one.  system.  A process is a part of a task (or task) of a user, forming an independent branch and carried out in parallel with other branches (processes) of this task and other tasks.  The process includes user statements, information storage areas for interruptions, and control information for communicating with other processes.  Control information representing sufficient autonomy to the process is drawn up in the form of a process control table (TUP).  The process is in one of

three possible states: activity (the processor is allocated to the process and its programs are currently running), readiness (the process is ready for execution, but waiting for one of the processors to be released) and blocking (the process is waiting for some event, for example, a message from another process) . Process management in multimicroprocessor systems is carried out by an operating system core (OS), which includes the following components; lower level scheduler (regulator), means for creating / destroying processes in the system, means for communicating processes, means for synchronizing processes. The traffic controller ensures the parallel execution of processes in the system, taking into account the state of all processes in the system, changing the state of processes, selecting ready-made processes and assigning processors to them. Process creation / destruction tools are used to format tasks and independent parts of tasks in the form of processes, as well as to output the executed processes from the service loop. The means of communication processes provide the ability to exchange messages between processes. The means of creating / destroying and communicating processes are system primitives that are included in the OS kernel and implement user interaction with OS control programs. Synchronization tools provide coordination of processes when accessing common system resources (for example, P and V operations on semaphores).

The structure of a multi-microprocessor system is largely determined by the distribution of the functions of the drug core in process control between the modules of the system. In the system, the functions of the system primitives are performed by the microprocessor units of the control microprocessor device 7.

When managing processes in the system, the following system pointers and semaphores are used that are located in memory 2:

THE DECISION OF THE SOST form a list of state indicators of the executive microprocessor blocks I8.1fl8.n and are used to indicate the states of these blocks when the microprocessor block k of resource allocation is accessed. In addition, each status indicator contains the address of the PMU of the process that is currently being executed on this execution microprocessor unit;

NEXT is an indicator of the process to be assigned as the first of the ready-made processes to the vacated microprocessor control unit.

PAM DEPT is a pointer to the address of the first free memory zone in

list of free memory zones; LIST DECIDE is the index of the address of the first TUP in the general list of processes (OBSH);

The CEM OEIIJ LIST is used to synchronize the blocks of the controlling microprocessor device 7 and the microprocessor block k of resource allocation when accessing the GENERAL LIST;

CEM PAM (memory semaphore) is used to control blocked processes waiting to satisfy memory requests;

CEM LIST PAM (semaphore free list of memory) is used to synchronize the blocks of the control microprocessor device 7 when referring to LIST PAM;

CEM LIST A PAM block (the semaphore of the list of processes blocked by CEM PAM) is used to synchronize the blocks of the control microprocessor device 7.

The means of communication for the processes in the system is the PMU, which consists of the following components:

im process (NAME);

index of the next process in OBDD LIST (NEXT GEN);

an index of the next process in the list of a group of processes related to one task (NEXT GROUPS);

process status indicator (A);

an index of the state of readiness of the process for execution (D); process pointers to the microprocessor units of ETEZ for creating a process, destroying the process, sending a message and receiving a message (C ,. Y, PEP, PR);

process pending message waiting indicator (BLOCK MESSAGE);

the process interlock pointer on waiting for free memory when the microprocessor unit 90 runs the primitive CREATE GTHROCESS (UNIT UNIT G.); process lock pointer waiting for free memory when the microprocessor unit 92 executes the TRANSFER COOBLIE.HME primitive. (BLOCK PAI PER); process messages semaphore (CEM CEDR1D); the semaphore of the list of messages addressed to this process (CEM LIST MESS); The address pointer of the next TUP in the list of processes blocked in one semaphore (NEXT CEM); the area of preservation of the word of the state and the contents of the registers of microprocessor units (OBL SAV) The microprocessor control device 7 access parameters (PARAMETERS) parameter area. After the operating system initialization, the task scheduler, designed as a process and being one of the OS components, is assigned to one of the execution microprocessor-based I8.1rl8.n blocks, for example, block 18.1. Next, the executive microprocessor unit 18.1 through the memory communication device 6 and the microprocessor input-output unit 5 enters the I jobs of users from the lamppost disk (not shown) into the lemny area of the RAM. After completing the input of the 1st task, the executive microprocessor unit 18.1 executes the command to access another OS, as a result of which an interrupt occurs, which is processed in the standard way by changing the layer of the process state. By the reason code of the interruption in the TUP of the task scheduler, the pointer C is set and the stored information is rewritten, after which the pointer of block 18.1 in the list of state indicators of the microprocessor-based execution blocks 18..p is set to FREE and the microprocessor block C distributes the address to the microprocessor unit 90 for creating a process that draws the TUP of the first of the entered tasks and informs the microprocessor unit of the resource distribution about the availability of ready-to-run process in the system. After this, the execution of the job scheduler at the executive compressor unit 18.1 is resumed. The Task Scheduler repeats the above described cycle for creating processes for each of the 1 loaded tasks. In parallel with this, the microprocessor-based resource allocation unit performs the assignment of newly created user processes to free execution microprocessor-based 18.1t18 units. After the task scheduler finishes the 1st process creation cycle, it performs a call to another OS and, using the microprocessor block 93, the message is transferred to the list of blocked processes waiting for the message until a message about the processing of one of the tasks entered into the system appears. The created user processes are executed in parallel on the execution microprocessor device 1. In this case, the RAM areas that the execution microprocessor blocks I8.1rl8.n work with are specified by the corresponding PMU parameters. The execution of the program command by the microprocessor-based execution unit 18. As shown in the following order. In the register 27 of the memory address under the control of micro-commands, which are received from the micro-command memory node 22 through the register of 23 micro-commands, the address of the command is set. From the twelfth register output 23 microinstructions to the second control output of the executive microprocessor unit 18. A signal is sent to the Bus request, after which the microprocessor unit 18 K goes to the Standby mode. The appearance at the first control input of the executive microprocessor block 18.K signal Confirmation of a request to the fourth control input of the register 21 of microinstruction addresses causes the microcommand to be read, according to which the first and second control inputs of microprocessor nodes 20.1g20.8 open signals the first and second output buffers Z and 35. As a result, the address output of the executive microprocessor unit 18.K sets the address of the command, and the first control output microprocessor from the eleventh output of the micro-command register 23, a signal is received that determines the operation mode of the storage device 2. After an interval of time determined by the physical properties of the storage elements of the storage device 2, the address code is set to the information input-output of the microprocessor-based processing unit 18 teams. The address part of the command enters microprocessor nodes 20.t20.8, and the operational part of the command enters the address register of 21 microcommands. The operational part of the command is the address of the first microcommand from the microprogram interpreting this command. The microcommand also has an address and operational part. The address part of the microcommand containing the address of the microcommand following it is fed to the third control input of the register 21 of the microcommand address. The operational part of the microcommand contains the microfunction codes for which the control signals are generated, which enter the nodes and elements of the microprocessor control unit 18, K, With the arrival of each sync pulse along line 26 to the synchronizing inputs of the microprocessor nodes 20.1 g20.8, to their third control The micro inputs are received by the microcommands that are decoded by the decoder 30, the first and second switching elements 31 and 32 select the operands, and the operating element 29 performs the desired operation. On the second edge of the clock. The result of the operation is placed either in the accumulating register 28, or in the specified register of the memory element 33, or in the memory address register 27. At the end of the execution of each command, the gating of the interrupt node 2k is performed. The request received in the request register 39 during the period of validity of the strobe is received along with the code from the current priority register 37 n comparison element 38. If the priority of the incoming request is higher than the current priority, then the ST encoder generates a signal arriving at the second output of node 2 of the interrupt. On this signal, the address of the beginning of the interrupt processing firmware is read from register 2 G of the address of the micro commands 21, which reads the interrupt code and 120, after appropriate processing, rewrites this code in the current priority register 37. The exchange of commands and data between the system blocks and the storage device 2 takes place via the data bus 8, and the addresses are issued via the address bus 9. In this case, the memory device 2 operates in two modes: Read and Write. In the Read mode, the code of the sixteen lower bits of the data address is sent to the address inputs of the memory blocks, on the first control inputs of which the code of the read mode is set, the Code of the four higher bits of the data address The input to the decoder 40 determines the number of the memory block. To the second control input of the selected block k7. i memory receives a trigger signal, with the arrival of which a sampling signal appears at the output of decoder 2 allowing data to be read from the group of storage elements 50. After the time determined by the first delay element 6, the first flip-flop kj is set to the receive address state, and read data is output to the information input of the block, 1.1 of the memory, From the first control input of the block k. memory on the element And 4 gives a prohibitory signal, and the second trigger 46 remains in its original state Read, After a time determined by the fourth delay element 49, the first trigger 43 is reset to its original state. In the recording mode on the first control inputs of blocks 4l.1fit1, m of the memory is set to the Record mode code, and the first input of the AND element 44 of the selected memory block 41.1 receives the enabling signal, which allows you to first set the second trigger 45, to the Record state, and then switch to Storage, System n Blocks Access to storage device 2 is obtained through switching unit 3, which processes requests to memory according to their priorities. Requests are received at the input of register b2 requests. The highest priority request generates on one of the outputs of block 3 of the switching a request confirmation signal, which simultaneously blocks lower priority requests. When all requests

21

will be satisfied in the order of sequence, from the output of the second inverter 57 to the control input of the register of 62 requests will receive a signal that with the arrival of the clock pulse on line 26 will allow the reception of a new group of requests.

When the user process passes through the system, it can generate new processes related to the parallelizable task being performed, exchange messages with them and system processes, remove the created processes from the system with the help of microprocessor & coping device 7. The request of the controlling microprocessor device 7 is executed by the executive microprocessor unit 18. K by processing the extra code to access another OS. According to the code, the cause of the interruption in the TUP of the user process is established, the corresponding access indicator C, U. PER or PR is rewritten, the stored information and the state indicator of the execution microprocessor unit 18. K are set to the Free state, and then from the third control output of the execution microprocessor block 18.K, a signal is output to the second control output of the microprocessor unit 1. This signal goes to the first control input of the microprocessor block k for resource definitions, which starts viewing the list of the DECISION SOST, analyzes the PMU of the interrupted process and generates the corresponding interrupt code of the controlling microprocessor device 7 at its fourth control output. the process is ready for execution, and the fourth control input of the microprocessor block k of resource allocation receives a signal ready process in the system. The microprocessor block “C” of resource allocation through the P-operation on the CEM GENERAL LIST is included in the general list of processes, finds the TUP of the finished process, performs the V-operation on the CEM GEN, LIST, Places the address of the found PUP and the label is BUSY in the DECISION

122

of the free executive microprocessor unit 18.i, sets the pointer A in the TUP and generates the code of the microprocessor unit l8.i at its second control output. This code through the second control. Input executive microprocessor device 1 is fed to. register 19 and causes an interruption of the microprocessor-controlled block iB.i, which, at the address of the TUP, in its pointer, finds this TUP, loads the necessary parameters from the TUP into its own registers and proceeds to program execution.

When performing the OS core primitives, the blocks of the controlling microprocessor device 7 operate as follows.

The microprocessor unit 30 for creating a process, when its second control input receives a signal coming from the second control input of the controlling microprocessor device 7 through the second register 95 and the third element OR 98, performs the P-operation on the CEM OSlii, LIST, finds the TUP c pointer C, loads into its own registers the parameters necessary for execution from this TUP and performs a V-operation on the CEM OBSH, LIST Then a P-operation is performed on the CEM LIST of the CAM, a search for a free memory zone is performed, the volume of which is sufficient for registration of the PMU of the process being created, and a V-operation is performed on the CEM CAM LIST. Next, in the allocated memory zone, the TUP of the created process is formed, the P-operation is performed on the CEM OBSH, the LIST, this TUP is included in the ob-. The list of processes in the PMU of the creator process is removed pointer C and. pointer G is set, and from the fourth control output of the microprocessor unit 90 for creating a process, a signal OR is sent to the fourth control output of the control microprocessor unit 7 via the second element OR 97.

Microprocessor unit 31 unich. process, when a signal arrives at its third control input, coming from the second control input of the controlling microprocessor device 7, through the second register 95I, performs a P-operation on the CEM COMM LIST, finds a TUP with the indicator Y, loads the necessary data on its own registers the parameters from this TUP and searches for the TUP of the process being destroyed, after which it is excluded from the general list of processes and the U-Operation is performed on the CEM GENERAL LIST. Then, the process destruction microprocessor unit 91, according to the CEM index, COOB1D, finds the address of the list of messages of the process being destroyed and, through the CEM LIST of the CAM, includes the memory occupied by the messages sent to this process in the CAM LIST, then the same list includes the memory occupied by the TUP of the deleted of the process. After that, a pointer G is set in the TUP of the interrupted process and a signal is sent to the fourth control output from the fourth control output of the microprocessor block 91 of the process destruction the control output of the control microprocessor device 7. If the microprocessor unit 91 of the process destruction removes a process that is in the execution stage of one of the execution microprocessor units 8, IT 18, p from the system, then in the DECT of this executive unit the label Free is set. From the third control output of the microprocessor destruction unit 91, the signal is sent to the third control output of the control microprocessor device 7 Microprocessor transfer unit 92 on the third control input of the signal coming from the second control input of the controlling microprocessor device 7 through the register 95 and the OR element 101, the operation is completed CEM GENERAL LIST, finds the PMU with the indicator PER, loads the parameters necessary for the primitive to execute the primitive From this TUP, searches for the TUP of the process-receiver and performs a U-operation on the CEM GENERAL LIST. Then, a P-operation is performed on the CEM LIST of the CAM, a search of the memory area is made which is sufficient to decorate the transmitted message, and a V-operation is performed on the CEM CAM LIST. After this, a message is created in the allocated memory area, P-operations are performed on the CEM LIST of the process message-receiver MESSAGE, the message is included in the MESSAGE LIST, a V-operation is performed on the CEM LIST of the MESSAGE and V-operation is performed on the CEM COMMUNICATION of the receiver process then a pointer G is set in the process transmitter TUP and a signal is sent from the control output of the microprocessor transmission unit 92 to the message through the OR 97 element to the fourth control output of the control microprocessor device 7. The microprocessor processing unit 93 receiving a message when a signal arrives at its third control course, coming from the second control input of the controlling microprocessor device 7, through the register 95 and the OR element 102, performs a P-operation on the CEM COMM LIST, finds the TUP with the PR indicator, loads the own registers required for the execution of the primitive parameters from this TUP and performs the Y-operation1 on the CEM OBUL LIST, Then the P-operation is performed on the CEM COMMUNICATION in the found TUP, and in the case of the presence of addressed pro- process messages, the P-operation is performed hell CEM LIST MESSAGE, the first message is read from the LIST MESSAGE and the V-operation is performed on the CEM LIST of the MESSAGE, after which the P-operation is performed on the CEM LIST of the CAM, the memory occupied by the read message is included in the CAM LIST and the V-operation is performed over the CEM CAM LIST, After that, a pointer G is set in the TUP and a signal is sent from the seventh control output of the message receiving microprocessor 93 through the element OR 97 to the fourth control output of the control microprocessor device 7, In the absence of the non- process messages TUP mounted pointer BLOCK reported that puts the process in the list of blocked processes. If, when the V-operation is transmitted by the microprocessor unit 92, it is above the SEM SMS, the receiver is in the MESSAGE UNIT, then the MESSAGE UNIT indicator is removed in the receiver process control unit, the PR indicator is set, and a control output is sent from the control output of the microprocessor unit 92 the element OR 102 to the second control input of the microconductor

cessing unit 93 receiving messages.

When operating the microprocessor creation unit 90, which requires a memory to form a PMU of the process to be created, or the microprocessor communication unit 92, which requires a memory to form a message sent by the process, it is possible that there is not enough free memory. In this case, the microprocessor unit 9 or 92 performs the P operation on the CEM PAM, sets the processor of the creator or the transmitter process to the PMU, the corresponding pointer PAM C BLOCK or PAM PER BLOCK, performs the P operation on the CEM LIST CAM block, includes the PMU in the list processes blocked by CEM PAM and performs V-operation on CEM LIST of CAM block.

When the process control microprocessor unit 91 is in operation, the memory occupied by the PMU and messages of the process being destroyed is released, and when the message receiving microprocessor unit 93 is operated, the memory occupied by the read message is released. After arranging the PAM LIST, the microprocessor block 91 or 93 by means of the V operation on the CEM PAM checks for the processes blocked on this semaphore, and in the TUP of the first of the LIST of the PAM process block, an indicator C or PER is set, and then with the control output the destruction process unit 91 or the third control output of the microprocessor message receiving unit 93 sends a signal via the third element OR 98 to the second control input of the microprocessor unit 90 for creating the process, or from the sixth the control output of the process deletion microprocessor unit 91 or the fourth control output of the message receiving microprocessor unit 93 sends a signal through the OR 101 element to the third control input of the message transmission microprocessor unit 92.

When asynchronous viewing of system lists by microprocessor units 1,90,91, 92,93, the occurrence of linking blocking on system semaphores CEM COMM LIST, CEM LIST PAM and CEM LIST PAM BLOCK may occur

The operative exit from the mode of linking blocking is realized with the help of microprocessor synchronization unit 89. When performing one of the microprocessor blocks 4,90,91,92,93 P-operations on the system semaphore and in case of blocking on this semaphore, an index of the corresponding microprocessor block is set in memory that requires access to the system list. When performing one of the microprocessor blocks A, 90 91.92.93 V-operations on the system semaphore and in the case of a blocked microprocessor block, the second control input of the microprocessor block 89 synchronizes the signal through the OR 9b element from the corresponding control output of one of the microprocessor blocks 4,90,91,92,93, performed the head of the Y-operation. On this signal, the microprocessor synchronization unit 89 analyzes the corresponding blocking pointers, removes the pointer and issues a code to the third control output, using which through the register 95 to the third control input of the blocked microprocessor unit 90 and to the inputs of the blocks 91, 92.93 or. The third control input of the microprocessor resource allocation unit 4 receives a signal that outputs the unit from the interlocking lock mode.

Between microprocessor blocks 92 and 93, an interlocking lock may occur on the CEM LIST. When the microprocessor unit 92 transmits messages or the microprocessor unit 93 receives the message P-operation on the CEM LIST of the MESSAGE and in case of blocking on this semaphore, the microprocessor unit switches to the standby mode at its second control input. When one of the microprocessor blocks 92.93 performs V-operations on the CEM LIST of the MESSAGE and if there is a lock on this semaphore, another of the microprocessor blocks 92 and 93 produces an unlock signal or from the sixth control output of the microprocessor block 92 transmitting the message through the OR 100 element to the second control input of the microprocessor unit 93 receiving a message, or from the fifth control output of the microprocessor unit 93 receiving the message OR 99 to the second control input of the microprocessor unit Single 92 transmit a message. The execution of the user process is completed by processing the operating system's extracode. In this case, the microprocessor message transmission unit 92 is interrupted, which generates a message to the task scheduler. The task scheduler is transferred from the list of blocked processes to the number of ready-to-run processes, the microprocessor resource allocation unit assigns it one of the execution microprocessor blocks I8,1rl8.n, after which the task scheduler accesses the microprocessor block 93 for receiving messages, analyzes the read message, outputs it through the microprocessor an input / output unit 5 and a memory device 6 are output data of a user process to a printing device (not shown) and outputs an access code th to the microprocessor unit 91 destruction process. The spent user process is removed from the system, and the microprocessor unit 93 for receiving the message performs a P-operation on the CEM MESSAGE in the TUP of the task scheduler and includes this TUP in the list of processes that are pending on the message. After receiving the completion of the 1st task, the task scheduler is placed in the operational memory of the next portion of several tasks stored on the magnetic disk, and the system operation cycle described above is repeated. The system interacts with external devices through the microprocessor input unit 5 -outputs and a memory communication device 6 The memory communication device 6 operates in two modes: Channel programming and Transmission. In the Channeling mode, the microprocessor I / O unit 5 records in the b7 block the registers of the start address, the record length code and the data transfer mode code, the recording being carried out in two stages. At the first stage, the address of the start of data recording through the switch 66 enters 128 to the second information input of the register block 67, and the register address to which the recording will be made enters the third information input of the block b7 of registers via the switch b9. Simultaneously, from the third control output of the microprocessor I / O unit 5, via the second control input of the memory device 6, a Record signal is sent to the third input of the control unit 68, which sets the second trigger 79 of the control unit 68 to the Channel programming state. 8 of this state, the receipt of the register address through the switch b9 to the third information input of the register block 67 is allowed, and the passing of the clock pulses through the first element 7b and the first element OR 77 to the fourth and seventh outputs of the control block 68 is allowed. The register address goes to register 67 on descramblers and the start address of the data record is stored in the specified register of the first group of registers 87.1r87.8. After that, the microprocessor block 5 I / o removes the signal Record. At the second stage, the microprocessor I / O unit 5 supplies, on the data bus 8, the data recording length code, the transfer mode code and the register address from the second group of registers 88.1g88.8 of the b7 block of registers to which recording should be made. The code length of the data record and the code transfer mode is received through the switch 66 to the first information input of the block 67 of registers. The further order of operation of the memory communication device 6 in the second stage is similar to the operation of the device in the first stage. In the Transfer mode, data transfer requests are received from external devices on pin 73 to the request register 70. The encoder 71 generates at the output the request code, which is also the register address in the register block b7, is fed to the input of the switch 68. From the third output of the encoder 71, a bus request signal is output to the third control output of the memory link 6. This system is transmitted by the microprocessor I / O unit 5 to the switching unit 3. Having received a signal from the switching unit 3 Confirming the request, the microprocessor input-output unit 5 translates it via the second control input of the memory communication device 6 to the buffer node 72 and suspends its operation. From the buffer node 72, via the fk line, a signal is sent to the external device, via which the external device sends the prepared data to the data bus 8. From the buffer node 72, a signal is also sent to the second input of control unit 68, which sets the first trigger 72 to the Transmit state. Thereby, the passage of the register address through the switch b9 to the third information input of the block b7 of registers and the passage of the clock through the third element I 80 to the input of the counter 82, which is set to the Read state, is permitted. Via a decoder 81, the signal Read is transmitted to block b7 of registers and reads the contents of two registers from groups of registers 87.1t87.8 and 88.1-88.8, the address of which is set at the input of the decoders. The contents of the addressed registers goes to the counter 63 of the address of the record, the counter 6 of the length of the record and the register B5 of the operation mode.

With the arrival of the second clock pulse, the counter 82 enters the +1 state. Through the decoder 81, the +1 signal is transmitted to the register unit 67, increases the contents of the write address counter 63, and decreases the contents of the record length counter b by one. The third sync pulse sets the counter 82 to the Master reset state and (if the contents of the record length counter 6 is zero), the signal from the second output of the decoder 81 goes through the second element And 78 to the second and seventh outputs of control unit 68. The contents of the addressable registers of register block 67 will be set to zero. According to the signal at its second control input, the microprocessor input-output unit 5, through the first control input of the memory communication device 6, the buffer node 72 and the second input of the control unit 68 will set the first trigger 75 to the initial state. If the content of the record length counter 6A is not zero, then the state of the memory communication device 6 does not change. The fourth clock pulse sets the Record state in counter 82. In this case, the signal Record from the decoder 81

enters the block b7 of registers, where it records the contents of counter 63 of the write address, counter b of the record length and register b5 of the operating mode in two registers of the first and second groups of registers 87.1787.8 and 88.1t88.8 at the address set on the third information input of the block b7 registers. This same signal will go to the microprocessor unit 5 I / o. With the arrival of the fifth sync pulse, the decoder 81 will generate a Reset signal, which sets the record address counter 63, the record length counter 4, and counter 82 to a zero state. After that, the signal from the microprocessor I / O unit 5 sets the control unit 68 to the initial state, and also removes the request from the input of the switching unit 3. Subsequent sessions, the communication of external devices with the storage device 2 are carried out similarly.

Thus, the performance of the proposed multimicroprocessor system in comparison with the known one is increased by increasing the system capacity in connection with the possibility of combining the execution phase of the system primitives and the assignment phase of the executive microprocessor units for the sequence of processes

parallel operation of functional dedicated microprocessor units and microprocessor-based execution units, as well as by reducing the operating system overhead for executing control and synchronization functions in hardware-firmware structuring of the software core.

In addition, the proposed system allows simplifying management in a multimicroprocessor system by assigning interrupt handling functions of a certain type to certain modules and simplifying, thereby, the structure of an intermodular switch and microprocessor identification mechanism, duplicating the organization of online access to resources and tables through semaphores.

Invention Multimicroprocessor system comprising microprocessor executive device, microprocessor block for resource allocation, microprocessor input / output unit, communication device with memory, microprocessor control device including microprocessor synchronization unit, first control outputs, address outputs and information inputs the outputs of which are connected respectively to the control input, via the address bus — to the address input and via the data bus — to information input-output memory unit, switching unit, including the request register, the first groups of AND elements, OR elements, NOT elements, two OR elements, two NOT elements, And element, the output of which is connected to the first control input of the microprocessor I / O unit, the second and third control The second and third and fourth control outputs of which are connected respectively to the second and third control outputs and to the first and second control inputs of the communication device with the memory and to the input of the first digit of the request register, the first bit of the register of the switching unit request register is connected to the first inputs of the AND element and the first OR element of the switching unit; the output of the first OR element of the switching unit is NOT connected to the synchronization input of the query register; the outputs of the AND elements of the first group are connected to the first control the input of the executive microprocessor device, the second control input and the second and third control outputs of which are connected respectively to the second control output and to the first control input of the micro the processor-based resource allocation unit and with the inputs of the first group of bits of the query register; the outputs after it are the bits of the first group, the last bit of the second group of bits of the register of the switching unit request register are connected to the first inputs of the second OR element and the first OR element, respectively, the first inputs of the remaining elements OR of the first group are connected to the outputs of the remaining bits of the first group of the query register, the first and second inputs of the elements AND of the first group of the switching unit

are connected respectively with the outputs of the bits of the first group of the Register of Requests and through the elements of NOT the first group - k. the outputs of the OR elements of the first group, the output of each previous element OR of the first group of the switching unit is connected to the second input of the subsequent element ILK) of the first group, and the output of the last element OR of the first group is connected to the second input of the second OR element of the switching unit whose output is connected to the second input of the first element OR and through the second element HE with the second input of the element I of the switching unit, the third control output and the second control input of the microprocessor resource allocation unit are connected With the input and output of the second bit of the query register, characterized in that, in order to increase the system's capacity, the microprocessor unit for creating the process, the microprocessor for process destruction, the microprocessor for transmitting the message, the microprocessor unit for receiving the message, were inserted into the control microprocessor; two control registers. seven OR elements, and the second group of OR elements, NOT elements and AND elements are entered into the switching unit, with the first control inputs and outputs, the second control outputs, the address outputs and the information inputs / outputs of the microprocessor units for creating the process, killing the process, sending the message , receiving messages are connected respectively with the output of the second group of elements And,. with the input of the second group of request register bits, with the control input, via the address bus with the address input and through the data bus with the information input-output of the storage device, the first and second control inputs and the second and third control outputs of the microprocessor synchronization unit are connected respectively with the output of the second group of elements AND, with the output of the first element OR of the controlling microprocessor device, with the input of the second group of bits of the register of requests, with the input of the first register, the third and fourth equal outputs and second and third control inputs of the microprocessor unit for creating a process are connected respectively to the first inputs of the first and second OR elements of the controlling microprocessor device, to the output of the third OR element and to the first output of the first register, second, third, fourth and fifth the outputs of which are connected respectively to the third control input of the microprocessor resource allocation unit with the first inputs of the fourth and fifth OR elements, with the second control input of the microprocess The third destruction input unit, the third control input, the third, fourth, fifth, sixth, seventh control outputs of which are connected respectively to the first output of the second register with the first control input of the microprocessor resource allocation unit, and the second input of the second control element OR microprocessor device with the first inputs of the third and sixth elements OR with the second input of the first element OR of the controlling microprocessor device, the third input of which is coaxially connected with the second output of the second register, the input, the third, fourth and fifth outputs of which are connected respectively to the fourth controlling output of the microprocessor resource distribution unit, the second inputs of the third and sixth OR elements, to the first input of the seventh OR element, the second input to which is connected to the third control the output of the microprocessor message transfer unit, the second and third control inputs, the fourth, fifth and sixth control outputs of which are connected respectively to the outputs of the fourth and sixth OR elements, with the third in the second element OR of the controlling microprocessor device, with the fourth input of the first element OR of the controlling microprocessor device, with the second input of the fifth OR element, the output of which is connected to the second control input of the microprocessor message receiving unit, the third control input, the third, fourth , the fifth, sixth and seventh control outputs of which are connected respectively with the output of the seventh element OR, with the third inputs of the third and sixth element OR, with the second input of the fourth element OR, with n the first input and the fourth input of the second OR element of the controlling microprocessor device, the output of the second OR element of the controlling microprocessor device is connected to the fourth control input of the microprocessor resource allocation unit, the output of the last bit of the second group of the query register is connected to the first input of the second group And the second group , the outputs of the remaining bits of the second ..th group of the query register are connected to the first inputs of the remaining AND elements of the second group and to the first inputs of the AND elements Both the second group, the second inputs of the elements AND the second group are connected to the outputs of the corresponding elements NOT the second group, the input of the first element NOT the second group is connected to the output of the second bit of the query register, the inputs of the remaining elements NOT the second group are connected to the outputs of the corresponding elements OR the second group, the output of each previous element OR of the second group is connected to the second input of the subsequent element OR of the second group, the output of the last element OR of the second group is connected to the second input of the first element OR the first the first group. Sources of information taken into account in the examination 1. US patent ff, cl. G About F GZ / 10.15 / 16, 1977. 2. US patent N 4065809, cl. G 06 F 15/16, 1977. 3. Computer design. 197, W 3, p. 86

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Claims (1)

Claim Multi-microprocessor system containing an executive micropro 31 907551 processor, microprocessor-based resource allocation unit, microprocessor-based I / O unit, memory device, microprocessor-based control unit, including a microprocessor-based synchronization unit, the first control outputs, address outputs and information inputs-outputs of which are connected respectively to the control 1 input, through address bus - with address input and via data bus - with information input / output of the storage device, switching unit, including the request register, 1 first groups AND elements, OR elements, NOT elements, two OR elements, two NOT elements, AND element, the output of which is connected to the first control input of the microprocessor I / O unit, the second and third control inputs and the second, third and fourth control outputs of which are connected respectively to the second and third control outputs and with the first and second control inputs of the communication device with memory and with the input of the first category of the request register, the output of the first category of the request register of the switching unit is connected to the first inputs and And of the first element OR switching unit, the output of the first element OR switching unit through the first element is NOT connected to the synchronization input of the request register, the outputs of the elements of the first group are connected to the first control input of the executive microprocessor device, the second control input and the second and third control outputs of which connected respectively to the second control output and to the first control input of the microprocessor resource allocation unit and to the inputs of the first group of bits of the request register , the outputs of the last bit of the first group, the last bit of the second group of bits of the request register of the switching unit are connected to the first inputs of the second OR element and the first element of the first group of the switching unit, respectively, the first inputs of the remaining OR elements of the first group are connected to the outputs of the remaining groups of the request register, the first and second inputs of the elements And of the first group of the switching unit are connected respectively to the outputs of the bits of the first group of the register of Requests and through the elements NOT of the first group ppi - by the outputs of the OR elements of the first group, the output of each previous OR element of the first group of the switching unit is connected to the second input of the subsequent element of the ILL of the first group, and the output of the last OR element of the first group is connected to the second input of the second OR element of the switching unit, the output of which is connected to the second input the first OR element and through the second element NOT with the second input of the AND element of the switching unit, the third control output and the second control input of the microprocessor resource allocation unit are connected respectively with the input and output of the second category of the request register, characterized in that, in order to increase system performance, a microprocessor unit for creating a process, a microprocessor unit for killing a process, a microprocessor unit for transmitting a message, a microprocessor unit for transmitting a message, two control registers, are introduced into the microprocessor control unit, seven OR elements, and the second group of OR elements, NOT elements, and AND elements are introduced into the switching unit, the first control inputs and outputs, the second control output outputs, address outputs, and information inputs and outputs of microprocessor units for creating a process, destroying a process, transmitting a message, receiving a message are connected respectively to the output of the second group of elements And,. with the input of the second group of bits of the request register, with the control input, through the address bus with the address input and through the data bus with the information input-output of the storage device, the first and second control inputs and the second and third control outputs of the microprocessor synchronization unit are connected respectively to the output of the second group AND elements, with the output of the first OR element of the microprocessor control device, with the input of the second group of bits of the request register, with the input of the first register, the third and fourth control guides and outputs the second and third control inputs of the microprocessor unit creation about ³³ 907551 cession 34 are respectively connected to first inputs of first and second OR microprocessor control device, with output of a third OR gate and the first $ The yields house the first register, second, third, fourth and the fifth outputs of which are connected respectively with the third control input of the microprocessor resource allocation unit, 10 with the first inputs of the fourth and fifth OR elements, with the second control input of the microprocess process control unit, the third control input, the third, fourth, fifth, fifth, sixth, seventh control outputs of which are connected respectively to the first output of the second register, to the first control input of the microprocessor distribution block of resources 20, with the second input of the second element OR microprocessor control device, with the first inputs of the third and sixth elements OR with the second input of the first element 25 OR a microprocessor control device, the third input of which is connected to the second output of the second reg- = register, the input, the third, fourth, and fifth outputs of which are connected respectively ₃ θ, respectively, with the fourth control output of the microprocessor resource allocation unit, the second inputs of the third and sixth elements OR, with the first input of the seventh element $ ₃ OR, the second input of which is connected to the third control output of the microprocessor unit for transmitting messages, the second and third control inputs, the fourth, fifth and neck of the _40th control outputs of which are connected respectively to the outputs of the fourth and sixth OR element, to the third input of second OR device for the control of the microprocessor ₄₅ roystva, to a fourth input of the first OR gate control microprocessor device, with a second input of the fifth OR gate, whose output one with a second control input _J0 microprocessor unit receiving the message, the third control input of the third, fourth, fifth, sixth and seventh control outputs of which are connected respectively with the output of the seventh OR gate, to the third inputs of third and sixth OR gate, a second input of the fourth OR , with the fifth input of the first and fourth input of the second OR element of the controlling microprocessor device, the output of the second OR element of the controlling microprocessor device is connected to the fourth th input of the microprocessor resources allocation unit, the last digit output of the second register group requests is connected to the first input of the AND of the second group of bits remaining secondary outputs. a group of request register groups are connected to the first inputs of the remaining AND elements of the second group and to the first inputs of the OR elements of the second group, the second inputs of the AND elements of the second group are connected, with the outputs of the corresponding elements NOT of the second group, the input of the first element of the second group is connected to the output of the second register bit requests, the inputs of the remaining elements of the second group are connected to the outputs of the corresponding elements of the second group, the output of each previous element of the second group is connected to the second input of the subsequent OR gate of the second group, the output of the last element or the second group connected to a second input of said first OR gate first group.