JP3008223B2 - Synchronous processor between processors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a multi-processor
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system, and more particularly to a synchronization device between processors suitable for achieving synchronization between processors.

[0002]

2. Description of the Related Art Conventional synchronous processing in a multiprocessor is basically synchronization (processing ordering) between tasks, and employs a method in which a task is activated by task dripping or data dripping to advance processing. . If this is to be realized on a general-purpose multiprocessor, a task end flag is provided in the shared memory, and it is checked whether all necessary task processes preceding each task have been completed, and the process proceeds in a data flow. And a token control method. For the conventional synchronous processing, see “Multi-microprocessor system, pp. 117-11.
9, pp119-122, Philosophy Publishing, 1984 11
Moon ".

[0003]

The prior art in the above-mentioned general-purpose multiprocessor system has a high ratio of processing by software and has many check items, so that synchronization between tasks (appropriate priorities of task processing). Conversion)
Alternatively, synchronization processing overhead required for synchronization between processors is large. Therefore, task segmentation (fine task division) cannot be performed sufficiently. In addition, there is a problem that the task processing order of the parallel processing is unnecessarily restricted, and the parallelism of the job cannot be sufficiently extracted. Therefore, it is difficult to realize highly efficient parallel processing.

Further, in a multiprocessor system in which a limited number of processors process a large number of tasks, conventionally, when a certain processor ends one task processing and shifts to the next task processing, other necessary processing is performed. Synchronous processing is required to confirm whether task processing has been completed and all necessary results have been obtained. At that time, there is a problem that the processor is occupied by the synchronization check process, and a blank processing time occurs in which the processor does not execute a substantially effective process until the synchronization process is completed.

An object of the present invention is to provide a synchronizing device between processors capable of minimizing a synchronous processing overhead between tasks or between processors involved in parallel processing in a general-purpose multiprocessor.

[0006]

An object of the present invention is to provide a plurality of processors for sharing a plurality of tasks and performing parallel processing, a data sharing circuit for sharing data exchanged between the plurality of processors, and a synchronization processing circuit for taking between processor synchronization, the synchronization processing circuit each Pro
Obtain synchronization information from Sessa and combine those synchronization information.
Matching is a condition given by the corresponding processor in advance.
Or a condition given to the synchronization processing circuit together with the synchronization information.
When a match is found, the same
Means for generating an end-of-completion signal;
When the data sharing circuit is accessed, the processor
If no synchronization complete signal has been generated for
Until the end signal is generated.
Temporarily disable access to the circuit
Local synchronization circuit means for waiting for access
Is achieved by

The object of the present invention is to input task end information output by a processor whose task has been completed by the synchronous processing circuit, and to have all the task end information output by some processors processing related tasks change to active. A processor that outputs an active value to the corresponding processor with the synchronization end information indicating that the processor to be synchronized later has completed the task processing from the task end information, and the local synchronization circuit outputs the task end information. If the synchronization end information corresponding to the access to the data sharing circuit is not output from the synchronization processing circuit as an active value, the access is prohibited and the operation of the processor is stopped.

[0008] The object of the present invention is to form a group of processors that process related tasks when the synchronous processing circuit performs parallel processing, and to synchronize between the processors in the group or between the groups. This is achieved by providing means.

[0009] The object of the present invention is that the synchronizing means includes a synchronizing register for storing information corresponding to the names of the respective processors constituting the group output by one processor in the group, and an access to the synchronizing register. A triggered flip-flop, a first transmission circuit for transmitting the state of the flip-flop to another processor, and comparing the transmitted state of the flip-flop with the content stored in the synchronization register to perform the synchronization. A determination circuit for determining whether or not each processor in the group stored in the register is active, and transmitting a determination result output from the determination circuit to one processor in the group via the flip-flop. And a second transmission circuit.

[0010] The object of the present invention is to provide a synchronization register which stores information corresponding to the name of each processor constituting a group output by one processor in the group, and an access to the synchronization register. A triggered Philip flop and said Philip flop
First signal transmitting means for outputting a trigger signal from the processor to the flip-flop so that the flop outputs task completion information; and the synchronization register transmits a trigger signal for storing a group of processors from the processor to the flip-flop. Signal transmission means for outputting to the synchronization register, and third signal transmission for outputting from the processor to the synchronization register an active signal for setting the value of the synchronization register so that all processors belong to a group. Means are achieved.

An object of the present invention is to provide a synchronous processing device between processors for performing synchronous processing between a plurality of processors and controlling parallel processing without inconsistency, when each processor ends a task corresponding to each processor. Means for outputting appropriate task end information, and means for deactivating the active task end information corresponding to each processor when all the task end information from the processors to be synchronized becomes active and using the information. and, then have the means to make sure that the task termination information the processor to check the synchronization process has been completed
Command to output the active task end information
EO instruction and W for confirming that the synchronization process has been completed.
This is achieved because each processor can issue instructions .

[0012]

[0013] The object of the present invention is to provide, when a task of one processor terminates, a task executed by another processor which terminates execution at the same level from a task to be executed next by the processor, when there is no relation. When an EO instruction is inserted and the processor finishes one task and proceeds with processing to the next task, if the processor does not need information from another processor executed at the same level, the processor executes the EO instruction, This is achieved by having means for unconditionally proceeding to the next task.

[0014] The above-mentioned object is achieved by setting the E
The processor that has executed the O instruction and has shifted to the processing of the task currently being executed, at the end of the task, sets the relation between the next task to be executed and the task executed by another processor whose execution ends at the same level. If it has, execute a W instruction as a synchronization check instruction corresponding to the EO instruction executed at the previous level, check whether the synchronization processing of the previous level is completed, and then perform synchronization processing of the current synchronization level, This is achieved by having means for advancing the process to the next task.

[0015]

According to the structure of the present invention, noting that the number of tasks processed at the same time in a general-purpose multiprocessor does not exceed the number of processors, all synchronization problems caused by parallel processing are eliminated. In addition to implementing hardware processing for finite synchronization between processors, minimizing software overhead by using information when the processor accesses the data sharing circuit, Reduce the idle processing time that occurs.

In order to execute parallel processing with high efficiency without inconsistency while synchronizing the processors, a finite number of bits for the number of processors are prepared, and the bits corresponding to the processors executing the related tasks are activated. At the end of the task processing, the processor sets the set bit string (word data) as task end information in the synchronization register and executes a task end process for activating the task end line, and the information is input to the determination means. It monitors whether all processors corresponding to each bit of the set synchronization register have completed the task termination processing by checking with the corresponding task termination line of each processor, and all are true (the task has been terminated). If it is, it issues synchronization end information to the processor Those hardware the above synchronization processing is not jeopardized a is synchronous processing circuit.

Also, in order to automatically and without overhead reduce the idle processing time (idle time) of the processor generated during the synchronous processing period during the parallel processing, the following data sharing circuit is provided in addition to the above-mentioned synchronous processing circuit. And a local synchronization circuit.

The data sharing circuit is accessible from each processor which holds or provides shared data to be shared between processors required for task processing in the processors.

The local synchronization circuit transmits the task completion information to the above-described synchronization processing circuit, and the processor that has completed the task unconditionally shifts to the next task processing. When I tried to get
If the synchronization end information from the synchronization processing circuit has not been issued yet (remains inactive), the access to the data sharing circuit is suspended and the processor is made to wait.

As a result, the task processing is completed,
And if the synchronization process is not completed, unlike the conventional case where the processor is unconditionally waited and idle processing time is generated, the processor is as much as possible until the next task requires shared data. Since the next task processing can proceed, the idle processing time can be reduced.

Furthermore, assuming that only the value of the synchronization register is set by the software of each processor, and that all other settings are performed by hardware, it is programmable (has versatility) and software overhead is increased. Synchronization between processors as small as about one machine instruction can be achieved.

Further, the means for reducing the idle processing time generated during the synchronous processing period has the effect of shortening the critical path of the parallel processing itself, so that more efficient parallel processing can be automatically executed. .

By combining the control flow for arranging synchronous processing instructions in the software and the automatic tuning of the data flow by hardware utilizing the access condition to the data sharing circuit, the idle time of the processor can be further minimized. , Thereby reducing play time during parallel processing

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The overall structure of the present invention will be described below with reference to FIGS.

The present invention provides a synchronous processing circuit 101 for performing synchronous processing between processors necessary for parallel processing, and a plurality of processing units 100n for sharing and executing the processing of each task.
(N = 0, 1, 2,...), Providing and holding shared data necessary for exchanging necessary data between processors 1 n (n = 0, 1, 2,...) In each processing unit. Data sharing circuit CS on system bus 120 for performing
YS102 or a local data sharing circuit CS existing in each processing unit while maintaining data coherency
YS51n (n = 0, 1, 2,...). The synchronization processing circuit 101 receives a synchronization request Sln (n = θ, 1, 2,...) From the processor 1n in each processing unit at a corresponding input SYNCnREQ, and when all or some of them are activated, , The synchronization check signal TESTn to the processor to be notified is activated.
The active synchronization check signal TESTn is transmitted from the test signal line Tln to the signal control circuit 50n and the processor 1 in the processing unit 100n as synchronization end information.
n TEST inputs. The processor 1n has T
The state of the EST input is checked by hardware or software, and it is determined whether or not synchronization has been achieved between the processors executing the related processing. The basic function of the synchronization processing circuit is that when the synchronization processing circuit 101 receives the synchronization request Sln from the processor 1n, the output of the TESTn is returned to inactive once, and all the synchronization requests Sl from the processors that need to be synchronized become active. When TE
The STn output is set to the active state again. A specific embodiment in the synchronization processing circuit 101 will be described later in detail with reference to FIGS. Each processor 1n (n = θ,
1, 2,...) Are Slns that are active as task end information in the synchronous processing circuit 101 when the task processing ends.
Is output. In response, data sharing circuits 102 and 51 until the corresponding TESTn output turns active.
It is assumed that necessary result data from another processor used in the next task processing is not completely available on n (n = θ, 1, 2,...). Therefore, if the following condition is satisfied, parallel processing can be performed while maintaining synchronization between processors as in the past, without contradiction.

1) All the task end information (information input to the SYNCnREQ of the synchronous processing circuit at Sln) from the processor executing the related task processing has changed to active (all necessary task processing at that level). At the timing after the end of the task, the processing unit and the processor that issued the task end information are notified of the active synchronization end information (output from TESTn and Tl).
n transmitted to the processing unit). Until the synchronization end information changes to active, it is assumed that not all the result information from the task processing executed at that level is available.

2) Data in which the processor shifts to the next level of task processing (task processing to be executed at the next level) and holds data to be shared between processors among the task processing results executed by other processors. Shared circuit 102
Alternatively, when the processor 51n is accessed for the first time, the processor must confirm that the synchronization end information is already active. If the synchronization end information is in an inactive state at the time of accessing the data sharing circuit for the first time in the task processing, access to the data sharing circuit must be pending until the synchronization end information changes to active.

3) Here, the definition of the level boundary is defined as the time when each processor issues active task end information. That is, a break between each process defined as a task is defined as a level boundary. The point in time when the active synchronization end information is issued from the synchronization processing circuit 101 is defined as a boundary of the synchronization level.

In order to execute the parallel processing most efficiently while satisfying the above conditions, the idle processing time generated in the synchronization processing (by waiting for the processor that has reached the synchronization point earlier until the synchronization processing is completed). It is necessary to minimize the resulting processor idle time. For this purpose, it is preferable to adopt a method in which each processor advances the processing of the next level as early as possible. That is, during the task processing, the task processing is advanced by ignoring the synchronization end information until the first access to the data sharing circuit, and the synchronization end information is activated (the other processor is not activated) at the first access to the data sharing circuit. Has completed all necessary task processing, and all necessary shared information exists on the data sharing circuit). In other words, this is a method in which each processor performs processing as early as possible by shifting its own synchronization point as late as possible. This has the effect of dynamically changing the processing time of each task that appears to be generated as a fixedly divided task depending on synchronization conditions, shortening the critical path itself for parallel processing, and increasing the efficiency of parallel processing. There is an information flow parallel processing effect of automatically realizing the processing. This method is different from the conventional method that depends only on the synchronization processing end information, and is different from the data sharing circuit 102 or 51n.
Synchronization processing is executed in close coordination with the access processing to the server. The details of the hardware will be described using the processing unit 100n in FIG. 1 and the signal control circuit 50n in the processing unit shown in detail in FIG. 2 as an example.

The signal control circuit 5 in the processing unit 100n
0n receives control signals 19n including address signals from the processor 1n, decodes them, generates an access request signal 13n for accessing the shared system CSYS 51n and the data shared circuit bus 112, and generates a data sharing circuit and data sharing. This is sent to an arbitration circuit DC103 which determines which processor is to be given access to the circuit bus 120. The arbitration circuit DC103 receives a plurality of access request signals 13n (n = 1, 2,...) Sent from a plurality of processing units, selects one of them, and selects an access permission signal l3n.
4n (n = θ, 1, 2,...) Has a function of activating an access permission signal corresponding to a processing unit selected. When the access permission signal 14n becomes active, the signal control circuit 50n turns on the output buffer 52n.
Then, an address signal, a control signal, and an information signal are output to the data sharing circuit bus 120 via the bus line 15n in the case of a write process. In the case of a read process, data on the data sharing circuit bus is written to the local data sharing circuit CSYS 51n via the bus line 15n and the input buffer 53n,
The processor 1n directly reads the data via the n. The information of the local data sharing circuit CSYS51n is transferred to the processor 1
When n is read, the data is read via the bus line 17n. Each local data sharing circuit CSYS 51n (n = θ, 1, 2,...) In each processing unit 100n (n = θ, 1, 2,...)
Must always keep the same content. Therefore, at the time of read processing from processor 1n, local data sharing circuit CSYS 51 is independent of other processors.
n can be accessed like a local memory, but at the time of write processing, the local data sharing circuits CSYS 51n (n = n) in all the processing units (n = 1, 2, 3,...) via the data sharing circuit bus 120. θ, 1,
2,...), The data sharing circuit bus 120 must be occupied and executed under the control of the arbitration circuit 103. At this time, the local data sharing circuit CS independently executed in each processing unit
An access conflict with the read process from the YS 51n occurs. In this case, conflict control is performed in the signal control circuit 50n so that the access can be performed without contradiction.

FIG. 2 shows an embodiment of the signal control circuit 50n . The decoder 200 decodes an address line and a control line 19n from the processor 1n, and generates a control signal, an enable signal, and the like for an access request when the processor 1n accesses the data sharing circuits CSYS 51n and 102. Data sharing circuit bus access request signal CSREQ (Lo to arbitration circuit 103)
Active) 13 n is supplied from the decoder 200 to the data sharing circuit enable signal CSEN (Lo active) 213.
And synchronization end information SYNCOK (Lo) from the synchronization processing circuit
Active) It is generated by taking the OR theory with Tln. The acknowledge signal 14n from the arbitration circuit 103 is a direct response from the arbitration circuit 103 to the CSREQ signal 13n.
A SACK signal (an access request has been accepted at the time of Lo level) 209 and a common system CSYS 51n (n
= Θ, 1, 2,...) Is occupied by the write processing of any of the processing units. RDYACK signal (Hi
The active (active) 206 is controlled to become inactive (Lo level) when the CSBUSY signal 210 is active, and to the data sharing circuit CSYS 51n when the processor 1n attempts to read data from its own data sharing circuit CSYS 51n. This prevents access conflicts with write processing from other processing units. That is, when there is a write process to the CSYS 51n, the NAND gate 208 becomes inactive (High level), and makes the read enable signal CSRD (Lo active) to the CSYS 51n inactive. For example, it is assumed that the decoder 200 activates the CSEN 213 to access the data sharing circuit 102. At that time, assuming that SYNCOKTln is inactive, CSREQ13n will not be activated by OR gate 212 while SYNCOKTln is inactive, and therefore CSACK
Signal 209 is also inactive and CSACK signal 20
9 also remains inactive. Thereby, CSAC
NOR gate 20 receiving K209 and CSREQ13n
2 is fixed to the Lo level. The decoder 200
CSE until the output of the R gate 202 changes to Hi level
N213 is kept fixed at Lo level. Similarly, the BF controlling the output of the output buffer 52n
The ON signal 12n also receives the output of the NOR gate 202 and remains inactive (High level), and the access to the data sharing circuit bus 120 waits until SYNCOKTln becomes active. The function of temporarily stopping the processor 1n is a READY signal (Lo active) 11n
Is kept inactive and the bus cycle of the processor 1n is not terminated. The READY signal 11n is supplied to the CSRD 18n by the AND gate 211.
Or BFONl2n becomes active when it becomes active and causes the processor to proceed to the next process. This is called a local synchronization function. Similarly, a signal CSRD18 for accessing the supply system CSYS51n
n also converts SYNCOKTln to Hi active by the inverter 207 and inputs it to the NAND gate.
While YNCOKTln is inactive, CSRDl
By making 8n and READY11n inactive, access to the data sharing circuit CSYS51n is temporarily stopped.

FIG. 3 shows an embodiment of the synchronization processing circuit 101. NAND gates UAθ-UAn... Receive the corresponding Q outputs of flip-flops UCθ-UCn... And the corresponding Q outputs of flip-flops UBθ-UBn. , The output of the multi-input NAND gate receiving these outputs becomes Lo level. Philip Flop UC
When Q of θ to UCn is a Hi level, the corresponding NA
The Q outputs of the flip-flops UBθ to UBn input to the ND gates UCθ to UCn become effective. In this example, the validity of the Q output of UBθ to UBn.
The processor 1θ performs the operation of determining invalidity. That is, if the synchronization request Sln (n = θ, 1, 2,...) From the corresponding processor 1 n (n = θ, 1, 2,...) Is ignored for the flip-flops UC θ to UC n. , And corresponding SlDθ to SlDn.
.. UCn... Are set to Lo level (θ) by generating a trigger signal at Slθ. Each processor 1n
(N = θ, 1, 2,...)
By generating a trigger signal at lθ ~ Sln ...
The Lo level of the Q output is set, the Hi level is set for the Q output, and the synchronization end information Tlθ to Tln. The corresponding NAND gates UA whose Q outputs of UCθ to UCn are set to Hi level (1)
The outputs of θ to UAn turn to the Hi level for the first time. All the Q outputs of UBθ to UBn are set to L when the Q outputs of UCθ to UCn are set to the Hi level.
Only after being set to the o level, the output of the multi-input NAND gate UDθ transitions from the Hi level to the Lo level.
By the output of the Lo level of UDθ, the flip-flops UBθ to UBn are preset, and the Q output is H
Return to i-level. On the other hand, the Q outputs of UBθ to UBn return to the Lo level, and the active synchronization end information Tlθ to
Tln... Correspond to a corresponding processor 1n (n = θ, 1,
2, ...).

If it is desired that all the processors participate in the synchronization processing, all the Q outputs of UCθ to UCn... This is called a simultaneous synchronization mode. If only the synchronous mode is used, the flip-flops UCθ to UCn are not required, and UBθ to U
The Q output of Bn...
What is necessary is just to input directly to the AND gate UDθ.

Next, another embodiment of the synchronization processing circuit of the present invention will be described with reference to FIG. In the embodiment,
The processor system is assumed to be composed of m processors, and FIG. 1 shows typical processors 1n and 1n + 1. Each processor is provided with inter-processor synchronization processing circuits 2n and 2n + 1. 2n, 2n
+1 is equivalent to the circuit portion 101A in the synchronization processing circuit shown in FIG. Information communication between the synchronization circuits 2n and 2n + 1 is performed by a signal line 8. According to the present invention, a processor that executes a related task can arbitrarily form a group, and can perform processing while synchronizing within the group. Circuit 2 for inter-processor synchronization described above
n and 2n + 1 correspond to the respective processors, and are triggered by a synchronization register 5 for storing information corresponding to a group name and a timing at which a value is set in the synchronization register 5 or a timing thereafter. The state of the flip-flop is compared with the signal line for broadcasting to each processor and the broadcast information is compared with the contents of the synchronization register 5, and it is checked whether or not all the states of the processors in the group registered therein are true. A judgment circuit 6 to perform
And a signal circuit for notifying the processor of the check result. Reference numeral 4 denotes an access signal signal line, 8 denotes a task end signal line, 9 denotes a status line, and 10 denotes a trigger signal line. The synchronization register 5 corresponds to the flip-flops UCθ to UCn... In the circuit shown at 101A in FIG. In this embodiment, since each processor 1n has a synchronization register 5 corresponding to each processor 1n, each processor can independently select a processor to be subjected to synchronization processing (in the example of FIG. 3, only the processor 1θ has the right to select). Having). In the present embodiment, a configuration is adopted in which synchronization processing circuits are provided in a distributed manner corresponding to each processor, and the distributed synchronization processing circuits 2n (n = θ, 1,... The necessary data is transmitted and received via line 8. Therefore, the synchronous processing circuit 1n shown in FIG. 1 includes all of the synchronous processing circuit 2n (n = θ, 1,... N) and the signal line 8.
01.

Next, a synchronous operation sequence in a group of processors will be described. It is assumed that, for example, processors 1n and 1n + 1 among the processors 10 _{0 to} 1n form a group and execute related tasks. First, the operation of the processor 1n will be mainly described. When the processor 1n completes the task processing, the data line 3 is stored in the synchronization register 5.
(SlDθ to SlDn to SlDm), the nth and (n + 1) th bits are set to “1”, and the other bits are set to “0”.
Is written (this indicates a group of processors). At the time of the write operation, the signal line 4 indicating that the processor n is accessing the synchronization register 5 generates an active pulse, which serves as a write clock signal to the synchronization register 5. At the same time, Philip furo Tsu <br/> flop 7 by a signal line 4 is also triggered, the 0 level of the task termination signal to the terminal Q is outputted, the terminal Q is outputted one level status signals. Task termination signal from the terminal Q is connected to the n of the task termination signal lines 8 are transmitted to the synchronous circuit 2 ₀ to 2n of each processor. The status signal from the terminal Q is sent to the processor 1n by the status line 9.
Is input to the TEST input of the
Processing is suspended until the T input changes to the 0 level. The value set in the synchronization register 5 and the value of the signal line 8 are:
The signals are taken into the judgment circuit 6 while maintaining the correspondence of 0 to m, and the NAND-NAND gate (UAθ of 101A)
To UAn... And UDθ), the value of the task end signal line 8 corresponding to the bit in which 1 is set in the synchronization register 5 becomes 0 level, that is, in this example, the task end signal line 8 N and n + 1
Becomes 0 level, the trigger signal 10 becomes active 0. In response, Philip flop 7 is yellowtail set, the task termination signal 1 from the terminal Q is turned to 1 level, the n of the task termination signal lines 8 1 level to Do <br/> order, decision circuit 6 Trigger signal 10 also changes to one level. At the same time, the status signal at the terminal Q changes to the 0 level, and the TEST input of the processor 1n also changes to the 0 level, so that the processor 1n restarts the processing. Since the same operation is performed in the processor 1n + 1, in this example, as a result, the processors 1n and 1n + 1 are synchronized with each other when the task processing is completed.

The above is the operation sequence of the synchronous processing circuit of the present invention. In the present invention, the synchronization processing by software is only writing a value to the synchronization register 5, and is about one machine instruction at a machine language level. All other processing is performed by hardware, so that the overhead required for the synchronization processing under the condition of being programmable is minimized. Further, according to the present invention, it is possible to group processors by related ones only by using one set of the synchronization processing circuit 101, and the synchronization processing is performed between the processors belonging to each group. It can be done easily. Further, by providing a plurality of sets of the synchronization processing circuit 101 of the present invention, it is possible to multiplex the synchronization processing between groups and the like. The processor grouping and the multiple synchronization provide flexibility in parallel processing, and high-efficiency parallel processing close to data flow can be realized on a general-purpose multi-processor system. FIG. 5 shows a flow of control of parallel processing by the synchronous processing circuit 101 of the present invention. In the example of FIG. 5, local synchronization processing performed in the signal control circuit 50n is not used, and the synchronization processing is executed by the processor 1n checking only the synchronization end information from the synchronization processing circuit 101. . In this figure, it is assumed that four processors from processor a to processor d are controlled by the synchronization processing circuit 101 of the present invention in parallel processing progress from the upper part to the lower part in the figure as time elapses. First, related tasks, task 1 and task 2, are processed by the processors a and b, respectively, and similarly, task 3 and task 4 are processed by the processors c and d, respectively. Processors that execute related tasks can form a group. In this case, the processor a and the processor b form a group 11, and the processor c and the processor d form a group 12.
The solid arrows connecting the tasks indicate the processing flow and data flow between the same processors, and the dashed-dotted arrows indicate the data flow between tasks executed by other processors in the group, that is, between the processors in the group. Is shown. At times t ₁ and t ₂ , it becomes necessary to communicate within each of the two groups.
After the synchronization processing has been performed by 01, the processing data is exchanged between the processors. Thereafter, the groups of the processors a and b shift to the processing of the tasks 5 and 6, respectively, and the groups of the processors c and d shift to the processing of the tasks 7 and 8, respectively. As described above, the synchronization processing by the inter-processor synchronization processing circuit 101 illustrated in FIG. 4 indicates which processor and group have been configured to execute the task processing up to that time. In addition, since data exchange does not occur between groups due to grouping, it is possible to proceed independently of each group, and flexible parallel processing progress control realizes efficient parallel processing It is possible. Thereafter, the groups 13 and 14 are referred to as the groups 12 and 13
Constitute a group with the same processor comrades are performed task processing, communication between the synchronization process is performed the process in the same time t ₃ and t ₄ are made with. At time t _5, all tasks 9-12 relevant occurs, since the independence between groups is exhausted, once after the synchronization processing in the group, is performed again synchronization by the processor synchronizing processing circuit 101 of another system And have all processors synchronized. That is, the inter-processor synchronization processing circuit 10 of another system
It can be considered that the synchronization processing between groups has been performed by 1 and, as a result, the group 15 is a group to which all processors belong. Then, related task 1
Processors a through c that process 3 through 15 are group 16
The processor d to perform independent tasks 16 alone group 17 constitute respectively, reorganize the group, and then execute the parallel processing while performing synchronization processing in the following likewise time t ₆ and t _7, etc. . When a plurality of sets of the synchronization processing circuits 101 are prepared and multiplex synchronization processing is performed as described above, group reorganization and the like can be easily realized, and more flexible and highly efficient parallel processing can be realized.

Next, the specific effect obtained when the inter-processor synchronization processing device shown in FIG. 1 is constructed using the synchronization processing circuit of the present invention shown in FIG. 4 is a minimum unit constituting a task. An example is shown in the figure, decomposed and analyzed to the instruction level of the processor. FIG. 6a shows a case where the synchronization process between processors is performed without relying on the local synchronization method and depending only on the synchronization end information Tln, which can be said to be a conventional type. That is, it may be considered that a part of the parallel processing flow shown in FIG. 5 is cut out. The operating conditions and assumptions of FIG. 6 are shown below.

1) An instruction for inter-processor synchronization in which task end information is sent to the synchronization processing circuit 101 and the end of the task is declared by the processor is denoted by S.

2) The processors Pl, Pm, and Pn form a group, and execute related tasks while synchronizing within the group.

3) After executing the instruction S, each processor Pl, Pm, Pn keeps until the synchronization end information (TEST output) from the synchronization processing circuit 101 becomes active (all of Pl, Pm, Pn remain at that level). Is completed, and the execution of the instruction S is unconditionally waited.

4) Even if the synchronization end information is in an inactive state, each processor does not use external data,
The instruction can be executed as much as possible, limited to instructions existing in an instruction queue or an instruction cache inside the processor. That is, as the synchronization logic, in response to the external bus cycle generated to access the synchronization processing circuit 101 when executing the instruction S, the Ready signal is not returned to the processor until the synchronization end information changes to the active state. It is assumed that a circuit configuration for temporarily stopping the external bus cycle (not ending the external bus cycle) is adopted.

5) Instructions that do not use external data (for example, operations between registers) are denoted by I. On the other hand, an instruction using external data other than data on the shared system is denoted by ID, and an instruction using shared data on the shared system is denoted by ICD.

On the other hand, FIG. 6 shows the first shared system access (IC
The case where the processing is advanced prior to D) is shown. The conditions and assumptions are 1), 2), 5) of FIG.
Is similar. The following conditions are set instead of conditions 3) and 4).

6) Each of the processors Pl, Pm, and Pn executes the instruction S and sends active task end information to the synchronous processing circuit, and then proceeds until a new access command (ICD) to the shared system appears. And proceed to the next level of task processing.

7) When the next level task processing is advanced in advance under the condition of 6), each processor P1, Pm,
If the synchronization end information from the synchronization processing circuit 101 at the previous level is not yet active at the time when the access processing ICD to the shared system is first executed, the external bus generated by the ICD is generated. The Ready signal 19 for the cycle is not returned to the processor until the synchronization end information becomes active. That is, the external bus cycle generated by the ICD is forcibly suspended (the bus cycle is not terminated) until the synchronization end information changes to active. The instruction I on the instruction queue or the instruction cache can be processed further ahead if it can be executed. The synchronization processing based on the combination of the instruction ICD and the synchronization end information is referred to as local synchronization processing as described above.

Here, SYNCk indicates a point in time when active synchronization processing information is returned from the synchronization processing circuit, that is, a point in time when synchronization at level k has been achieved. In FIG. 6, the processors Pl and Pm are used in the latter half of the level k-1.
In the latter half of the level k, idle time occurs in the processors Pl and Pn, and the processors are at rest. In FIG. 6, since each processor can proceed with the processing until the instruction ICD appears, the level k-1 except that the processor Pm has a slight idle time in the latter half of the level k-1. , At level k, there is no idle time. Assuming that the start is M and the end is N, FIG.
6, Pl is tl, Pm is tm, and Pn is tn in the lower part of FIG. In the processor that executes the critical path of the parallel processing, the level k-1 is Pn, the level k is Pm, and the level k + 1 is Pl in the upper part of FIG. Both k and k + 1 are Pn, indicating that the critical path itself has changed. This is because each processor pre-processes task processing across levels, and the actual task processing time itself has dynamically changed, so that the critical path has also changed. As a result, assuming that the start time of the process is M and the end time is N, the processing time in the lower part of FIG. 6 is shorter than that in the upper part of FIG. This is a calculation in which the processing capacity is improved by about 21%, and indicates that the processing capacity can be greatly improved by using the local synchronization method.

In FIG. 6, points A, B, and C indicate the positions of the instructions S for synchronizing P1, Pm, and Pn at the level k-1, respectively. D,
Points E and F are instruction ICDs with shared system access that are executed for the first time among tasks executed at the level k. Similarly, G, H, and I indicate the position of S at level k, and J, K, and L indicate the position of the first appearing ICD in the task executed at level k + 1.

As described above, the present embodiment eliminates fixed task boundaries and precedes until it becomes necessary to access the shared system first and exchange shared data during task processing. Since the task processing can proceed as much as possible, idle processing time (processor pause time) associated with waiting processing between processors during synchronous processing
Can be reduced. This means that the task processing time is dynamically changed according to the synchronization condition of each processor to shorten the critical path itself of parallel processing, obtain the same effect as data-driven, and achieve more efficient Enables execution of parallel processing.

According to the synchronous processing circuit of the present embodiment,
In general-purpose multi-processors, when a fixed job is divided into tasks and parallelized for parallel processing, any processors that execute related tasks are grouped into groups and synchronized between processors in a group or between groups. By using the processing method, the synchronous processing mechanism between processes can be implemented as hardware as possible within a software programmable range.
This has the effect of minimizing software overhead required for synchronization processing.

Next, a description will be given of an embodiment of an instruction set for a synchronizing device between processors in which a synchronous processing instruction is arranged in software so that a play time in parallel processing can be reduced by a control flow. . Although a basic control flow by software can be realized by using the processor synchronization processing circuit of FIG. 4, in order to realize higher functionality, as shown in FIG. , 4b and 4c.

FIG. 7 is a block diagram showing a configuration of a synchronization processing circuit according to another embodiment of the present invention. The signal line 4a is a signal for triggering a flip-flop that outputs task end information, and the signal line 4b is a trigger signal for registering a group in the synchronization register 5. The signal line 4c will be described later.

FIG. 8 shows the contents of the synchronous processing instruction.

In order to operate the synchronous processing circuit shown in FIG. 7, each processor n (n = 0, 1,...) Sends a corresponding synchronous processing element n (n = 0, 1,...) S
A total of eight instructions of YNCO to SYNC7 are commanded. Each instruction has a mnemonic that expresses its function. That is, the basic functions are as follows.

GS: group setting (registering a group in the synchronization register 5 indicates which processor constitutes the group) E
O: End out (Activates task end information and outputs it to task processing end signal line 8 to indicate that the task has ended.) W: Wait (tasks of all processors belonging to the group have ended, Put the corresponding processor in the wait state until the synchronization process is completed.
This is a function for finally confirming whether or not the processing has been completed.) The following composite instructions are provided so that one machine instruction can be executed by combining the above basic functions.

GSEOW: Group setting (G
Each function is sequentially processed in the order of S) → end out (EO) → wait (W), and a series of synchronous processing is realized by one machine instruction.

GSEO ...... Group setting (G
Each function is sequentially processed in the order of S) → end out (EO).

EOW: Each function is continuously processed in the order of end out (EO) → weight (W). Previously GS
A series of synchronous processing is realized by one machine instruction for the group set by the function.

In addition, the following composite instructions are provided to further speed up and simplify the processing on the processor side.

TSEOW ...... Total setting (T
Each function is sequentially processed in the order of S) → end out (EO) → weight (W).

TSEO ...... Total setting (T
Each function is sequentially processed in the order of S) → end out (EO).

Here, the TS is a basic function for instructing all processors to be regarded as one group and performing synchronous processing, and is referred to as total setting. By activating the signal line 4C in FIG. 7, this function sets the value of the synchronization register to a mode in which all processors are considered to belong to the group.

FIGS. 9 and 10 are explanatory diagrams for explaining a task processing method.

The use and effects of the control flow will be described with reference to FIG.

FIG. 9 shows the GSE which is an intra-group synchronization instruction.
FIG. 9 shows a conventional parallel processing control by the synchronous processing performed using only the OW or the EOW and using the synchronous processing circuit shown in FIG. Processor m and processor n form a group. As described above, each processor declares that the processors m and n belong to the group when the tasks are completed. Then, the processors m and n wait for each other until all the task processing end signals from the processors m and n in the group output at that time become active, and then proceed to the next task so that the parallel processing is performed without contradiction. Proceed with the process.

FIG. 10 shows the embodiment shown in FIG. 1 by using an EO instruction (output of only the task end information) and a W instruction (confirming that all the task end information in the group have been obtained). The shared system CSYS described
The same effect as the automatic tuning function using data driven (data flow type) depending on the access condition to
This is an example realized by a control flow (top-down parallel processing is controlled by a synchronization instruction from software). At the stage where the parallel processing is performed, the compiler inserts appropriate synchronization instructions of SYNCO to SYNC 7 shown in FIG. The conditions for properly using SYNCO-7 are as follows.

(1) At the end of a task of a certain processor, a relation from a task executed by another processor that terminates execution at the same level to a task to be executed next by the processor (arrows in FIGS. 9 and 10) Is not present, EO, which is an instruction only to output task end information, is inserted. That is, FIGS.
In this example, the end time of task 3 and the end time of task 4 apply to this condition. In terms of the operation level of the processor, when a certain processor finishes a certain task and proceeds with processing to the next task, it executes an EO instruction unless information from another processor executed at the same level is required. Means that processing can proceed unconditionally to the next task.

(2) The processor that has executed the EO instruction at the previous synchronization level and has shifted to the currently executing task process,
At the end of the task, when the next task to be executed has a relationship with a task executed by another processor that terminates execution at the same level, E executed at the previous level
The W instruction is executed as a synchronization check instruction corresponding to the O instruction, and it is confirmed whether the synchronization processing of the previous level has been completed. Then, the synchronization processing of the current synchronization level (for example, GSEOW)
Or EOW), and proceeds to the next task. That is, in the examples of FIGS. 9 and 10, the end point of task 5 satisfies this condition. In the program, W and EOW may be arranged in this order at the end of the task 5. The synchronization level here corresponds to the SYNC levels 1 to 3 in FIGS. 9 and 10, and indicates the point in time when the task processing at that level ends and the synchronization processing needs to be executed. In addition,
The difference between the GSEOW instruction and the EOW instruction is that the GSEOW has a function (GS) for specifying a processor belonging to a group, whereas the EOW does not have the function. Therefore, when EOW is specified, the processor group configuration set by the previous GS function is used as a default value as it is.

The processing order of FIG. 10 will be described.

(A) Task 0, task 2, task 4, and task 6 are executed by processor m in this order.
It is assumed that task 1, task 3, task 5, and task 7 are executed by processor n in this order. In this example, it is assumed that there is a relation between the tasks indicated by arrows in the figure.

(B) The processing results of task 0 and task 1 are mutually used by task 2 and task 3. Therefore, the processors m and n need to be synchronized at the SYNC level 1, and a series of synchronization processes from the group setting to the synchronization completion check are realized with one instruction by mutually executing the GSEOW instruction.

(C) At SYNC level 2, task 4 uses the processing results of task 2 and task 3, and task 5 uses only the result of task 3. However, there is no change in the group. Accordingly, the processor m executes a series of synchronization processes from the output of the task end information to the synchronization completion check by the EOW instruction, and the processor n executes the EO instruction and continuously performs the next synchronization without performing the synchronization check (W). Proceed to processing.

(D) At SYNC level 3, task 6 requires only the processing result of task 4 and task 7 requires both the processing results of task 4 and task 5. Therefore, the processor m executes the EO instruction and proceeds to the next processor continuously without performing the synchronization check (W).
On the other hand, the processor n executes the W instruction corresponding to the EO in the previous (SYNC level 2) to execute the SYNC level 2
And then execute an EOW instruction to execute SY
After executing a series of synchronization processes of NC level 3 (that is, after confirming that task 4 is completed), the process proceeds to the next task (task 7). From the above, it can be seen that the play times ta and tb generated in FIG. 9 are almost completely eliminated in FIG.

The features of the control flow system in this embodiment are described below.

(1) If the relation between the tasks and the processing time are known accurately, the optimal play time can be optimized by simply inserting an appropriate synchronization instruction into the program according to the rules at the time of the parallelization schedule to be performed in advance. Tuning can be realized. When the automatic tuning is used, the relation between the tasks cannot be determined strictly, so that the optimality is inferior to this embodiment.

(2) Since no special hardware other than the synchronization processing circuit shown in FIG. 7 is required, the configuration is simple.

According to the present invention, a plurality of processors for sharing a plurality of tasks and performing parallel processing, a data sharing circuit for sharing data exchanged between the processors, and a synchronization processing circuit for synchronizing the plurality of processors equipped with a door, the
The synchronization processing circuit obtains synchronization information from each processor.
The combination of those synchronization information
Together with the condition given in advance from the
When the condition given to the synchronous processing circuit matches, the pair
Means for generating a synchronization completion signal for a corresponding processor
And each processor accesses the data sharing circuit.
A synchronization complete signal for that processor is generated.
If not, wait until the synchronization complete signal is generated.
Temporary access to the data sharing circuit of the processor.
Locally forbidden and wait for access of the processor
When the task processing is completed and the synchronization processing is not completed, the processor performs the next task processing as much as possible until the next task requires shared data by having the synchronization circuit means. As a result, the task processing can be advanced, so that the effect of reducing the idle processing time can be obtained.

When jobs are processed in parallel, related processors can be grouped into groups and synchronized between processors in a group or between groups, so that the synchronization processing mechanism can be implemented in hardware. The effect of minimizing the software overhead required for is obtained.

By combining a control flow for controlling the parallel processing from the top down with a synchronization instruction by software and a data flow automatic tuning by hardware, the idle time of the processor can be further minimized, and the optimal parallelization can be achieved. Efficiency can be realized.

[Brief description of the drawings]

FIG. 1 is a hardware block diagram showing an overall configuration according to an embodiment of the present invention.

FIG. 2 is a system diagram showing a configuration of a signal control circuit shown in FIG.

FIG. 3 is a system diagram showing an embodiment of the synchronization processing circuit shown in FIG. 1;

FIG. 4 is a system diagram showing another embodiment of the synchronization processing circuit shown in FIG. 1;

FIG. 5 is an explanatory diagram showing an example of control of parallel processing by synchronous processing between processors according to the present invention.

FIG. 6 is an explanatory diagram showing an effect of shortening the processing time when local synchronization is also used according to the embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a synchronization processing circuit according to another embodiment of the present invention.

FIG. 8 shows the contents of a synchronous processing instruction according to another embodiment of the present invention.

FIG. 9 is an explanatory diagram illustrating a relationship between a task and a synchronous processing instruction according to another embodiment of the present invention.

FIG. 10 is an explanatory diagram illustrating a relationship between a task and a synchronous processing instruction according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 Processor constituting multiprocessor 2 Synchronous processing element 4 Access signal line to synchronous processing element 4a Signal line 4b Signal line 4c Signal line 5 Synchronization register 6 Judgment circuit 7 Philip flop 8 Task processing end signal line 9 Status signal Line (task end information line) 120 shared system bus 121 arbitration line 50n signal control circuit 51n local shared system 100n processing unit 101 synchronization processing circuit 102 shared system 103 arbitration circuit

Continuation of front page (56) References JP-A-2-105961 (JP, A) ASPLOS- ▲ III ▼ SI GPLAN Notices 24 Sp ecial Issue May 1989 p54-63 Rajiv Gupta , "The Fuzzy Barrie r: A Mechanism for High Speed Synchro nization of Proces sors " (58) investigated the field (Int.Cl. ^7, DB Name) G06F 15/177 680 G06F 9/46 360 INSPEC (DIALOG) JICST file (JOIS)

Claims (8)

(57) [Claims] 1. A plurality of processors for sharing a plurality of tasks and performing parallel processing, a data sharing circuit for sharing data exchanged between the plurality of processors, and a synchronization for synchronizing the plurality of processors. and a processing circuit, said
The synchronization processing circuit obtains synchronization information from each processor.
The combination of those synchronization information
Together with the condition given in advance from the
When the condition given to the synchronous processing circuit matches, the pair
Means for generating a synchronization completion signal for a corresponding processor
And each processor accesses the data sharing circuit.
A synchronization complete signal for that processor is generated.
If not, wait until the synchronization complete signal is generated.
Temporary access to the data sharing circuit of the processor.
Locally forbidden and wait for access of the processor
A synchronous processing device between processors , comprising: synchronous circuit means . 2. The synchronization processing circuit inputs task end information output by a processor that has completed a task, and after the task end information output by some processors that process related tasks has all changed to active. Based on the task end information, the processor to be synchronized outputs synchronization end information indicating that the task processing has ended to the corresponding processor, and outputs an active value to the corresponding processor. 2. The method according to claim 1, wherein when the synchronization end information corresponding to the access to the data sharing circuit is not output as an active value from the synchronization processing circuit, the access is inhibited and the operation of the processor is suspended. Synchronous processing device between processors according to claim 1. 3. The synchronization means for forming a group of processors for processing related tasks when performing parallel processing, and for synchronizing between the processors in the group or between the groups. The synchronous processing device between processors according to claim 1, further comprising: 4. The synchronizing means is triggered by a synchronizing register for storing information corresponding to the names of respective processors constituting a group output by one processor in the group, and an access to the synchronizing register. A flip-flop, a first transmission circuit for transmitting the state of the flip-flop to another processor, and comparing the transmitted state of the flip-flop with the content stored in the synchronization register to obtain the synchronization register. A determination circuit for determining whether each processor in the group is active or not, and transmitting a determination result output from the determination circuit to one processor in the group via the flip-flop. The synchronous processing device between processors according to claim 3, further comprising: a transmission circuit. 5. The synchronizing means is triggered by a synchronizing register for storing information corresponding to the names of respective processors constituting a group output by one processor in the group, and an access to the synchronizing register. First flop, first signal transmission means for outputting a trigger signal for the flip-flop to output task completion information from the processor to the flip-flop, and the synchronization register stores a group of processors. Signal transmitting means for outputting a trigger signal from the processor to the synchronization register, and an active signal from the processor for setting the value of the synchronization register so that all processors belong to the group. And third signal transmission means for outputting to the register. 4. The synchronous processing device between processors according to claim 3, wherein: 6. A synchronous process between a plurality of processors,
In a synchronous processing device between processors for controlling parallel processing without inconsistency, means for outputting active task end information when each processor ends a task corresponding to each processor, and Means for deactivating the active task end information corresponding to each processor when all the task end information becomes active and using the information, and that the processor checks the task end information and ends the synchronization processing. It has a means for confirming the action
An EO instruction instructing the output of active task end information;
A W instruction for confirming that the synchronization process has been completed is issued to each program.
A synchronous processing device between processors, which can be issued by a processor. 7. At the end of one processor task,
If there is no relation from a task executed by another processor that terminates execution at the same level to a task to be executed next by the processor, the EO instruction is inserted;
When the processor finishes one task and proceeds to the next task, if the processor does not need information from another processor executed at the same level, the processor executes the EO instruction and unconditionally proceeds to the next task. 7. The synchronous processing device between processors according to claim 6 , further comprising: means for proceeding with the process. 8. The processor which executes the EO instruction at the immediately preceding synchronization level and shifts to the currently executing task processing,
When a task to be executed next at the end of the task has a relation with a task executed by another processor which terminates execution at the same level, as a synchronization check instruction corresponding to the EO instruction executed at the previous level, Execute the W instruction to check whether the previous level of synchronization has been completed,
Then, means for performing a synchronization process of a current synchronization level and proceeding to a next task is provided.
8. A synchronization processing device between processors according to claim 7 .