JPH052568A - Inter-processor synchronizing processor - Google Patents

Abstract

PURPOSE:To provide an inter-processor synchronizing processor capable of minimizing synchronizing processing overhead between tasks or processors which is generated due to the parallel processing of a general purpose multi- processor. CONSTITUTION:The inter-processor synchronizing processor consists of a synchronizing processing circuit 101 for executing synchronizing processing between plural processors necessary for parallel processing, plural processing units 1000 to 100n for executing partial charge of processing of respective tasks, and a data sharing circuit CSYS 102 connected to a system bus 120 for offering and storing shared data necessary for transferring necessary data among respective processors 10 to 1n in respective processing units or a local data sharing circuits CSYS 510 to 51n included in respective processing units while holding the coherence of data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a multi-processor system.
The present invention relates to a system, and more particularly, to a synchronizer between processors suitable for synchronizing processors.

[0002]

2. Description of the Related Art The conventional synchronous processing in a multi-processor is basically synchronization (processing ordering) between tasks, and takes a system in which tasks are activated by task drip or data drip to proceed with processing. . If you try to realize this on a general-purpose multi-processor, you will have a task end flag on the shared memory, and check whether all the required task processes preceding each task have been completed and proceed with the data flow. Method and token control method are adopted. For the conventional synchronous processing, see "Multi-microprocessor system, pp117-11.
9, pp119-122, Philosophy Publishing, 1984 11
The Moon ".

[0003]

In the prior art in the above-mentioned general-purpose multi-processor system, since the rate of processing by software is high and there are many check items, synchronization between tasks (regarding the precedence relationship of task processing is performed). )
Alternatively, the synchronization processing overhead required for synchronization between processors is large. Therefore, the task cannot be subdivided (fine task division). Further, there is a problem that the task processing order of parallel processing is unnecessarily restricted, and the parallelism of jobs cannot be sufficiently drawn out, so that it is difficult to realize highly efficient parallel processing.

Further, in a multiprocessor system in which a limited number of processors process a large number of tasks, conventionally, when a certain processor finishes a task process and shifts to the next task process, another need is required. Synchronous processing is required to confirm whether the task processing has been completed and all the required results have been obtained. At that time, the processor is occupied by the synchronization check processing, and there is a problem that there is an idle processing time in which substantially effective processing is not executed until the synchronization processing ends.

An object of the present invention is to provide a synchronization device between processors capable of minimizing the synchronization processing overhead between tasks or between processors due to parallel processing in a general-purpose multi-processor.

[0006]

The above-described object is to provide a plurality of processors that share a plurality of tasks and perform parallel processing, a data sharing circuit that shares data exchanged between the plurality of processors, and a plurality of the plurality of processors. And a local synchronization circuit for controlling competing access requests to the data sharing circuit from each of the plurality of processors.

The above-mentioned object is to input the task end information output by the processor whose synchronous processing circuit has finished the task, and to change all the task end information output by some processors which process the related tasks to active. A processor that outputs an active value to the corresponding processor as synchronization end information indicating that the processor to be synchronized later has completed the task processing from the task end information, and the local synchronization circuit outputs the task end information. If the corresponding synchronization end information is not output as an active value from the synchronization processing circuit when the data access circuit accesses the data sharing circuit, the access is prohibited and the operation of the processor is suspended.

The above-mentioned object is to form a group of processors which process tasks related to each other when the synchronous processing circuit executes parallel processing, and synchronize the processors in the group or between the processors. It is achieved by providing means.

[0009] The above-mentioned object is that the synchronization means stores a synchronization register for storing information corresponding to each processor name forming a group output by one processor in the group, and an access to the synchronization register. The triggered flip-flop, a first transmission circuit for transmitting the state of the flip-flop to another processor, the transmitted state of the flip-flop and the stored contents of the synchronization register, and the synchronization A decision circuit for deciding whether or not each processor in the group stored in the register for activation is active, and a decision result output by the decision circuit is transmitted to one processor in the group via the flip-flop. And a second transmission circuit.

The above-mentioned object is achieved by the synchronizing means storing information corresponding to the names of the respective processors constituting the group output by one processor in the group, and by accessing the synchronizing register. The triggered Philip Flop and the Philip Flip
First signal transmission means for outputting a trigger signal for the flop to output task end information from the processor to the Philip flop, and a trigger signal for the synchronization register for storing a group of processors from the processor to the synchronization Second signal transmission means for outputting to the register for synchronization, and third signal transmission for outputting an active signal from the processor to the register for synchronization so that the value of the register for synchronization is set so that all processors are regarded as belonging to a group. It is achieved by having means.

The above object is to provide a synchronous processing device for performing synchronous processing between a plurality of processors and controlling parallel processing without contradiction, and active when each processor corresponding to each processor finishes a task. For outputting active task end information, and means for deactivating the active task end information corresponding to each processor when all the task end information from the processors to be synchronized become active And a means for the processor to check the task end information to confirm that the synchronization processing has been completed.

The above object is achieved by each means having a means for instructing an EO instruction for instructing the output of the active task end information and a W instruction for confirming the completion of the synchronous processing.

[0013] The above-mentioned object is that when there is no relation from a task executed by another processor that terminates execution at the same level when the task of one processor ends, to a task to be executed next by the processor, When an EO instruction is inserted and the processor finishes a task and proceeds to the next task, if the information from another processor executed at the same level is not needed, the EO instruction is executed, This is achieved by having a means to proceed unconditionally to the next task.

The above-mentioned object is the above-mentioned E at the previous synchronization level.
The processor that has executed the O instruction and moved to the processing of the task currently being executed has a relation with the task executed by another processor in which the next task to be executed finishes at the same level at the end of the task. When it has, the W instruction is executed as a synchronization check instruction corresponding to the EO instruction executed in the previous level to check whether the synchronization processing in the previous level is completed, and then the synchronization processing in the current synchronization level is performed. This is achieved by having a means for advancing processing to the next task.

[0015]

According to the configuration of the present invention, attention is paid to the fact that the number of tasks being processed at the same time in a general-purpose multi-processor does not exceed the number of processors, so that all synchronization problems caused by parallel processing are synchronized between processors. To minimize the software overhead by using the information when the processor accesses the data sharing circuit, and at the same time, the synchronization processing between the processors is limited. Reduces the idle processing time that occurs.

In order to execute parallel processing in a highly efficient manner without any contradiction while synchronizing the processors, a finite number of bits for the number of processors are prepared and the bits corresponding to the processors executing the related tasks are activated. The processor sets the set bit string (word data) in the synchronization register as task end information at the end of the task processing and executes the task end processing that activates the task end line, and the information is input to the determination means. , Check whether all the processors corresponding to each bit of the set synchronization register have completed the task end processing, by checking with the corresponding task end line of each processor, all are true (task has finished) Then, the synchronization completion information is issued to the processor, assuming that synchronization has been achieved, and general-purpose Those hardware the above synchronization processing is not jeopardized a is synchronous processing circuit.

Further, in order to automatically reduce the idle processing time (play time) of the processor that occurs during the synchronous processing period during the parallel processing without overhead, in addition to the synchronous processing circuit described above, the following data sharing circuit is provided. And a local synchronization circuit.

The data sharing circuit is accessible from each processor that holds or provides shared data to be shared among the processors necessary for task processing in the processors.

The local synchronization circuit sends the task end information to the above-mentioned synchronization processing circuit and the processor which has finished the task unconditionally shifts to the next task processing, and the shared data required from the data sharing circuit is not received until the shared data required for the first time. When trying to get
If the synchronization end information from the synchronization processing circuit has not yet been issued (remains inactive), the access to the data sharing circuit is pending and the processor is made to wait.

As a result, the task processing is completed,
And when the synchronous processing is not completed, unlike the conventional case where the processor is unconditionally made to wait and the empty processing time is generated, the processor can wait until the next task needs the shared data. Since the next task processing can proceed, the idle processing time can be reduced.

Further, if only the setting of the value in the synchronization register is performed by the software of each processor and the rest is performed by the hardware, it is programmable (having versatility) and software overhead is reduced. It is possible to synchronize between one machine instruction and a small processor.

Further, the means for reducing the idle processing time generated during the synchronous processing period has an effect of shortening the critical path of the parallel processing itself and can automatically execute the parallel processing with higher efficiency. .

By combining the control flow for arranging the synchronous processing instruction in the software and the automatic tuning for the data flow by the hardware utilizing the access condition to the data sharing circuit, the idle time of the processor can be further minimized. , Which can reduce the play time during parallel processing.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The overall structure of the present invention will be described below with reference to FIGS.

According to the present invention, a synchronous processing circuit 101 for performing synchronous processing between processors necessary for parallel processing, and a plurality of processing units 100n for sharing and executing the processing of each task.
(N = 0, 1, 2, ...), Provision and holding of shared data necessary for exchanging necessary data between the processors 1n (n = 0, 1, 2, ...) In each processing unit. Data sharing circuit CS on the system bus 120 for performing
A local data sharing circuit CS that exists while maintaining data coherency in the YS 102 or each processing unit
It is composed of YS51n (n = 0, 1, 2, ...). The synchronous processing circuit 101 receives the synchronous request Sln (n = θ, 1, 2, ...) From the processor 1n in each processing unit to the corresponding input SYNCnREQ, and when all or some of them are activated, It is considered that the processors have been synchronized, and the synchronization check signal TESTn to the processor to be notified is activated.
The active synchronization check signal TESTn is used as synchronization end information from the Test signal line Tln and the signal control circuit 50n and the processor 1 in the processing unit 100n.
n TEST input. The processor 1n is T
The state of the EST input is checked by hardware or software to determine if the processors performing the associated processing are synchronized. The basic function of the synchronous processing circuit is that when the synchronous processing circuit 101 accepts the synchronous request Sln from the processor 1n, the TESTn output is once returned to inactive, and all the synchronous requests Sl from the processor that must be synchronized become active. When TE
The STn output is set to the active state again. A specific embodiment in the synchronization processing circuit 101 will be described later in detail with reference to FIGS. 3 and 4. Each processor 1n (n = θ,
1, 2, ...) are Slns that are active as task end information in the synchronous processing circuit 101 when the task processing is completed.
Is output. In response to this, the data sharing circuits 102 and 51 are activated until the corresponding TESTn output becomes active.
It is considered that necessary result data from other processors used in the next task processing are not completely available on n (n = θ, 1, 2, ...). Therefore, if the following conditions are satisfied, it is possible to proceed with parallel processing while maintaining synchronization between the processors as in the conventional case.

1) All the task end information (information input to SYNCnREQ of the synchronous processing circuit at Sln) from the processor executing the related task processing has turned active (all required task processing at that level). At the timing after the completion of the task), the active synchronization end information (Tl output from TESTn is output to the processing unit and the processor that issued the task end information).
information transmitted to the processing unit by n). It is assumed that all the result information by the task processing executed at that level is not available until the synchronization end information becomes active.

2) Data that holds data to be shared between processors among the result of task processing executed by another processor when the processor shifts to task processing at the next level (task processing to be executed at the next level) Shared circuit 102
Alternatively, when the 51n is accessed for the first time, the processor must finish the confirmation that the synchronization end information is already active. If the synchronization end information is in the inactive state at the time of accessing the data sharing circuit for the first time in the task processing, the access to the data sharing circuit must be pending until it becomes active.

3) Here, the definition of the level boundary is defined as the time when each processor issues active task end information. That is, the break of each process defined as a task is set as the level boundary. Further, the time when the active synchronization end information is issued from the synchronization processing circuit 101 is defined as the boundary of the synchronization level.

In order to execute the parallel processing most efficiently after satisfying the above conditions, the empty processing time generated in the synchronous processing (by waiting for the processor that reaches the synchronization point earlier until the synchronous processing ends) It is necessary to minimize the processor idle time that occurs. For this purpose, it is advisable to adopt a method in which each processor advances the processing entrusted to the next level as early as possible. In other words, during task processing, the synchronization end information is ignored until the data sharing circuit is accessed for the first time, and the task processing proceeds, and when the first data sharing circuit is accessed, the synchronization end information is in the active state (other processors). Has completed all necessary task processing and all necessary shared information exists on the data sharing circuit). In other words, this is a method in which each processor advances its processing as much as possible by shifting its synchronization point as late as possible. This has the effect of dynamically changing the processing time of each task that seems to have been created by dividing it at a glance, depending on the synchronization conditions, shortening the critical path of parallel processing itself, and increasing the efficiency of parallel processing. There is an information flow parallel processing effect that automatically realizes processing. This method is different from the conventional method that depends only on the synchronization processing end information, unlike the data sharing circuit 102 or 51n.
The synchronization process is executed in close coordination with the access process to access. Details of the hardware will be described by taking the processing unit 100n of FIG. 1 and the signal control circuit 50n in the processing unit shown in detail in FIG. 2 as examples.

The signal control circuit 5 in the processing unit 100n
0n receives a control signal l9n including an address signal from the processor 1n, decodes them to generate an access request signal l3n for accessing the shared system CSYS51n and the data sharing circuit bus l12, and the data sharing circuit and the data sharing. It is sent to the arbitration circuit DC103 which determines to which processor the access right to the circuit bus 120 is given. The arbitration circuit DC103 receives a plurality of access request signals 13n (n = 1, 2, ...) From a plurality of processing units, selects one of them, and selects an access permission signal l.
4n (n = θ, 1, 2, ...) Has a function of activating the access permission signal corresponding to the selected processing unit. The signal control circuit 50n turns on the output buffer 52n when the access permission signal 14n becomes active.
Then, an address signal, a control signal, and an information signal in the case of write processing are output to the data sharing circuit bus 120 via the bus line 15n. Further, in the case of the read processing, the data on the data sharing circuit bus is written to the local data sharing circuit CSYS51n via the bus line 15n and the input buffer 53n, or the bus line 10n.
It is directly read by the processor 1n via n. Information of the local data sharing circuit CSYS51n is processed by the processor 1
When n is read, it is via the bus line 17n. Each local data sharing circuit CSYS51n (n = θ, 1, 2, ...) In each processing unit 100n (n = θ, 1, 2, ...)
Must always have the same content. Therefore, during the read process from the processor 1n, the local data sharing circuit CSYS51 is independent of other processors.
Although n can be accessed like a local memory, at the time of write processing, the local data sharing circuit CSYS51n (n = n) in all processing units (n = 1, 2, 3, ...) Through the data sharing circuit bus 120. θ, 1,
2, ...), the data sharing circuit bus 120 must be occupied and executed under the control of the arbitration circuit 103. At this time, the local data sharing circuit CS that is independently executed in each processing unit
Although access competition with the read processing from the YS 51n occurs, the competition control is also performed in the signal control circuit 50n with respect to this as well, so that access can be performed without contradiction.

FIG. 2 shows an embodiment of the signal control circuit 100n. The decoder 200 decodes the address line and the control line 19n from the processor 1n to generate a control signal, an enable signal and the like for an access request when the processor 1n accesses the data sharing circuits CSYS51n and 102 . Data sharing circuit bus access arbitration circuit 103 request signal CSREQ (L
o active) L3n, the data sharing circuit enable signal CS EN (Lo active from the decoder 200) 21
3 and the synchronization end information SYNCOK (L
o Active) Created by taking the OR theory with Tln
To achieve. Akunoriddji signal l4n from A over arbitration circuit 103, and the CSR EQ signal l 3n CSACK signal is a direct response from the arbitration circuit 103 for (access request when the Lo level is accepted) 209, a common system CSYS51n
(N = θ, 1, 2 , ...) consists CSBUSY signal indicating that it is occupied by the write processing of the processing unit of purchase Zureka (Lo active). RDYACK signal (H
The i-active) 206 is controlled to become inactive (Lo level) when the CSBUSY signal 210 is active, and when the processor 1n tries to read data from its own data sharing circuit CSYS51n, the data sharing circuit CSYS51n. The access conflict with the write processing from the other processing units does not occur. That, NAND gate 208 if the write process to CSYS51n exists becomes inactive (Hi level), the read enable signal to CSYS51n CSRD the (Lo active) inactive. For example, accessing the data sharing circuit 102
Because, decoders 200 active the CSEN213
Let's say At that time, SYNCOKTln non-A Kute
When a I Bed, CSREQl3n is by OR gate 212, not active Among SYNCO KTln is inactive, therefore, CSACK
Signal 20 9 also non accession Te CSA CK signal 209 also remains inactive. This allows CSACK 209 and C
The NOR gate 202 which receives SREQ13n is fixed at Lo level . De-coder 200, NOR gate 20
Set CSEN213 to L until the output of 2 turns to Hi level.
o level to characterize fixed situ. Similarly, a BFON signal 12n for controlling the output of the output buffer 52n
Receives the output of NOR gate 202 is also inactive (H
i level) remains, access to the data sharing circuit bus l20 is to wait until the SYNCOKT ln becomes active. The function to suspend the processor 1n is R
EADY signal (Lo active) l1n is inactive
To keep, not to terminate the bus cycle of the processor 1n
To realize I'm in particular. REA DY signal 11n is AN
Depending on the D gate 211, CSRD18n or BFON
When any one of l2n becomes active, it becomes active and the processor advances to the next processing. This is called a local synchronization function . Similarly, signals CSRDl8n for accessing the supply system CS YS51n, SYNCO
And enter the NAND gate is converted into Hi active inverter 20 7 KTln, SYNCOKTln
Is inactive, CSRD18n and READ
By making Y11n inactive, access to the data sharing circuit CSYS51n is temporarily stopped.

FIG. 3 shows an embodiment of the synchronization processing circuit 101. The NAND gates UAθ to UAn ... Receive the corresponding Q outputs of the flip-flops UCθ to UCn ... and the corresponding Q outputs of the flip-flops UBθ to UBn ..., and only when all the outputs become Hi level. , The output of the multi-input NAND gate receiving these outputs becomes Lo level. Philip Flop UC
When Q of θ to UCn ... is at the Hi level, the corresponding NA
The Q outputs of the flip-flops UBθ to UBn, which are input to the ND gates UCθ to UCn, become valid. In this example, the Q outputs of UBθ to UBn ... are valid,
The processor 1θ performs the work of determining invalidity. That is, when ignoring the synchronization request Sln (n = θ, 1, 2, ...) From the corresponding processor 1n (n = θ, 1, 2, ...) In the flip-flops UCθ to UCn ... , Corresponding SlDθ to SlDn ...
By setting the level (θ) and generating a trigger signal in Slθ, the Q outputs of the corresponding UCθ to UCn ... Are set to the Lo level (θ). Each processor 1n
(N = θ, 1, 2, ...) Corresponds to S as a synchronization request.
By generating a trigger signal in lθ ~ Sln ...
The Q output Lo level is set, the Q output is set to Hi level, and the synchronization end information Tlθ to Tln ... Is inactivated once. Corresponding NAND gate UA in which the Q output of UCθ to UCn ... Is set to Hi level (1)
The outputs of θ to UAn ... turn to Hi level for the first time. Q outputs of UCθ to UCn ... are set to Hi level. All Q outputs of corresponding UBθ to UBn ... are L.
Only after being set to the o level, the output of the multi-input NAND gate UDθ transits from the Hi level to the Lo level.
The output of the UDθ at the Lo level presets the flip-flops UBθ to UBn.
Return to i level. On the other hand, the Q output of UBθ to UBn ... returns to Lo level, and the active synchronization end information Tlθ to
Tln ... Corresponding processor 1n (n = θ, 1,
2, ...)

If all the processors are to participate in the synchronous processing, all the Q outputs of UCθ to UCn ... Can be set to the Hi level. This is called a simultaneous synchronization mode. If only the simultaneous synchronization mode is used, the flip-flops UCθ to UCn are not necessary and UBθ to U
Inverting the Q output of Bn ...
It may be directly input to the AND gate UDθ.

Next, another embodiment of the synchronization processing circuit of the present invention will be described with reference to FIG. Multi in the example
The processor system is assumed to be composed of m processors, and representative processors 1n and 1n + 1 are shown in this figure. Each processor is provided with circuits 2n and 2n + 1 for inter-processor synchronization processing. 2n, 2n
+1 is equivalent to the circuit portion indicated by 101A in the synchronization processing circuit shown in FIG. Information communication between the synchronizing circuits 2n and 2n + 1 is performed by the signal line 8. According to the present invention, a processor that executes a related task can arbitrarily configure a group, and the process can proceed while synchronizing with each other in the group. Circuit 2 for interprocessor synchronization described above
n and 2n + 1 correspond to each processor, and are triggered at a timing for setting a value in the synchronizing register 5 for storing information corresponding to a group name and a timing for setting a value in the synchronizing register 5 or thereafter. The state of the flip-flop is broadcasted to each processor and the broadcasted information is collated with the contents of the synchronization register 5, and it is checked whether the states of the processors in the group registered therein are all true. Determination circuit 6 for determining and determination circuit 6
And a signal circuit for notifying the processor of the check result. Reference numeral 4 is an access signal signal line, 8 is a task end signal line, 9 is a status line, and 10 is a trigger signal line. The synchronization register 5 corresponds to the flip-flops UCθ to UCn ... In the circuit 101A shown in FIG. In the present embodiment, since each processor 1n has the synchronization register 5 corresponding thereto, each processor can independently select the processor to be the target of the synchronization processing (in the example of FIG. 3, only the processor 1θ has the selection right). Have). In this embodiment, the synchronous processing circuits are provided in a distributed manner corresponding to each processor, and each of the distributed synchronous processing circuits 2n (n = θ, 1, ... The necessary data is transmitted and received by the line 8. Therefore, the synchronous processing circuit 1 shown in FIG. 1 including all the synchronous processing circuits 2n (n = θ, 1, ... N) and the signal line 8 is included.
It can be said that it constitutes 01.

Next, the synchronous operation sequence within the group of processors will be described. It is assumed that, for example, the processors 1n and 1n + 1 among the processors 1 _{0 to} 1n form a group and execute related tasks. First, the operation of the processor 1n will be mainly described. When the processor 1n completes the task processing, the data line 3 is transferred to the synchronization register 5.
Set (1) to the nth and (n + 1) th bits through (SlDθ to SlDn to SlDm), and set 0 to the other bits.
Write the bit string that sets (which indicates the group of processors). During the write operation, the signal line 4 indicating that the processor n is accessing the synchronization register 5 generates an active pulse, which serves as a write clock signal to the synchronization register 5. At the same time, Philip furo Tsu <br/> flop 7 by a signal line 4 is also triggered, the 0 level of the task termination signal to the terminal Q is outputted, the terminal Q is outputted one level status signals. Task termination signal from the terminal Q is connected to the n of the task termination signal lines 8 are transmitted to the synchronous circuit 2 ₀ to 2n of each processor. The status signal from the terminal Q is sent to the processor 1n via the status line 9.
Is input to the TEST input of the
The process is suspended until the T input changes to 0 level. The value set in the synchronization register 5 and the value of the signal line 8 are
The decision circuit 6 is loaded while maintaining the correspondence relationship of 0 to m, and the NAND-NAND gate (UAθ of 101A is
~ UAn ... And UDθ), all the values of the task end signal line 8 corresponding to the bit for which 1 is set in the synchronization register 5 become 0 level, that is, the task end signal line 8 in this example. N and n + 1
Becomes 0 level, the trigger signal 10 becomes active 0. In response, Philip flop 7 is yellowtail set, the task termination signal 1 from the terminal Q is turned to 1 level, the n of the task termination signal lines 8 1 level to Do <br/> order, decision circuit 6 The trigger signal 10 of turns to 1 level. At the same time, the status signal at the terminal Q changes to 0 level, and the TEST input of the processor 1n also becomes 0 level, so that the processor 1n restarts processing. Since the same operation is performed in the processor 1n + 1, in this example, as a result, both the processor 1n and the processor 1n + 1 are synchronized when the task processing is completed.

The above is the operation sequence of the synchronous processing circuit of the present invention. In the present invention, the synchronization processing by software is only the writing of the value to the synchronization register 5, and is about one machine instruction at the machine language level. Since all others are processed by hardware, the overhead required for synchronous processing is minimized under the condition of being programmable. Further, according to the present invention, it is possible to group the processors by related ones only by using one set of the synchronization processing circuit 101, and perform the synchronization processing between the processors belonging to each grouped group. It can be done easily. Further, by providing a plurality of sets of the synchronization processing circuit 101 of the present invention, it is possible to perform synchronization processing between groups in a multiplexed manner. Due to the grouping of processors and multiple synchronization, flexibility in parallel processing is created, and highly efficient parallel processing close to data flow can be realized on a general-purpose multi-processor system. FIG. 5 shows a flow of control of parallel processing by the synchronous processing circuit 101 of the present invention. In the example of FIG. 5, the local synchronization processing performed in the signal control circuit 50n is not used, and the synchronization processing is executed by the processor 1n checking only the synchronization end information from the synchronization processing circuit 101. . In this figure, it is assumed that four processors, processor a to processor d, are controlled by the synchronous processing circuit 101 of the present invention from the upper part to the lower part in the drawing in parallel with the progress of time. First, related tasks, task 1 and task 2 are processed by the processors a and b, respectively, and similarly, task 3 and task 4 are processed by the processors c and d, respectively. Since the processors that execute the related tasks can form a group, in this case, the processors a and b form the group 11, and the processors c and d form the group 12.
Solid arrows connecting tasks indicate the flow of processing and data between the same processors, and the dashed-dotted arrows indicate the flow of data between tasks executed by other processors in the group, that is, between processors in the group. Shows the communication of. At times t ₁ and t ₂ , communication needs to occur in two groups, and the synchronization processing circuit 1 of the present invention
After the synchronous processing is performed by 01, the processing data is exchanged between the processors. After that, the groups of the processors a and b move to the processing of tasks 5 and 6, respectively, and the groups of the processors c and d move to the processing of tasks 7 and 8, respectively. As described above, the synchronous processing by the inter-processor synchronous processing circuit 101 shown in FIG. 4 indicates which processor and group have been configured to execute the task processing up to that point. In addition, because data is not exchanged between groups due to grouping, it is possible to independently proceed with the processing of each group, and flexible progress control of parallel processing realizes efficient parallel processing. It is possible. After that, the groups 13 and 14 are changed to the groups 12 and 13
The same processors form a group to perform task processing, and at the same time t ₃ and ₄ , synchronous processing is performed and communication between processes is performed. At time t ₅ , all the tasks 9 to 12 are related and the independence between the groups disappears. Therefore, after performing the synchronization processing once within the group, the synchronization processing is performed again by the interprocessor synchronization processing circuit 101 of another system. , All processors are in sync. That is, the inter-processor synchronization processing circuit 10 of another system
It can be considered that the synchronization processing between the groups is performed by 1, and as a result, the group 15 is a group to which all the processors belong. Then related task 1
The processors ac for processing 3 to 15 are group 16
The processor d that executes the independent task 16 configures each single group 17, rearranges the groups, and executes parallel processing while performing synchronous processing at times t ₆ and t _{7 and the} like in the same manner. . Thus, by preparing a plurality of sets of synchronization processing circuits 101 and performing multiple synchronization processing, group reorganization and the like can be easily realized, and more flexible and highly efficient parallel processing can be realized.

Next, the concrete effect when the inter-processor synchronous processing device shown in FIG. 1 is constructed by using the synchronous processing circuit of the present invention shown in FIG. 4 is the minimum unit that constitutes a task. The figure shows an example of analysis by disassembling to the instruction level of the processor. FIG. 6a shows a case where the synchronization processing between processors is performed without relying on the local synchronization method and depending only on the synchronization end information Tln, which is, so to speak, conventional. That is, it may be considered that a part of the parallel processing flow shown in FIG. 5 is cut out. The operating conditions and assumptions of FIG. 6 are shown below.

1) An instruction for inter-processor synchronization, in which task end information is sent to the synchronous processing circuit 101 and the end of the task is declared by the processor, is denoted by S.

2) The processors Pl, Pm and Pn form a group and execute related tasks while synchronizing with each other in the group.

3) Each of the processors Pl, Pm, and Pn executes the instruction S and then the synchronization end information (TEST output) from the synchronization processing circuit 101 becomes active (all of Pl, Pm, and Pn are at that level). Task processing is completed, and the instruction S is executed, and the task is unconditionally waited.

4) Even if the synchronization end information is inactive, each processor does not use external data,
The instructions can be executed as much as possible by limiting to the instructions existing in the instruction queue or the instruction cache inside the processor. That is, as the synchronization logic, for the external bus cycle generated for accessing the synchronization processing circuit 101 when executing the instruction S, the Ready signal is not returned to the processor until the synchronization end information becomes active, and it is forced. It is assumed that the external bus cycle is temporarily stopped (the external bus cycle is not terminated).

5) An instruction that does not use external data (for example, calculation between registers) is denoted by I. On the other hand, an instruction that uses external data other than the data on the shared system is referred to as an ID, and an instruction that uses shared data on the shared system is referred to as an ICD.

On the other hand, FIG. 6 shows the first shared system access (IC
It shows the case where the processing is advanced to D). The conditions and assumptions are 1), 2), 5) of that in FIG.
Is the same. The following conditions are set instead of the conditions 3) and 4).

6) Each processor Pl, Pm, Pn executes the instruction S and sends the active task end information to the synchronous processing circuit, and then precedes until an access command (ICD) to a new shared system appears. And proceed to the next level of task processing.

7) When the task processing of the next level is advanced under the condition of 6), the processors Pl, Pm,
Pn is the external bus generated by the ICD when the synchronization end information from the synchronization processing circuit 101 at the previous level is not active at the time when the access processing ICD for accessing the shared system is first executed. The Ready signal 19 for the cycle is not sent back to the processor until the sync done information becomes active. That is, the external bus cycle generated by the ICD is forcibly suspended (the bus cycle is not ended) until the synchronization end information turns active. If the instruction I on the instruction queue or the instruction cache can be executed, the processing can be further advanced. The synchronization processing by the combination of the instruction ICD and the synchronization end information is called the local synchronization processing as described above.

Here, SYNCk indicates the time when the active synchronization processing information is returned from the synchronization processing circuit, that is, the time when the synchronization at the level k is achieved. In FIG. 6, the processors Pl and Pm are provided in the latter half of the level k-1.
In the second half of the level k, idle time is generated in the processors Pl and Pn, and the processor is halted. In FIG. 6, since each processor can advance the processing until the instruction ICD appears, the level k-1 is generated except for a slight idle time in the processor Pm in the latter half of the level k-1. , Level k, no idle time is generated. If the start is M and the end is N, then FIG.
In the lower part of FIG. 6, the processing time is shortened by Pl for tl, Pm for tm, and Pn for tn in the lower part of FIG. Also in the processor executing the critical path of parallel processing, level k-1 is Pn, level k is Pm, and level k + 1 is Pl in the upper part of FIG. 6, whereas level k-1 is in the lower part of FIG. Both k and k + 1 are Pn, and it can be seen that the critical path itself is changing. This is because each processor performed the task processing in advance across the levels, and the actual task processing time itself dynamically changed, so that the critical path also changed. As a result, when the processing start time is M and the processing end time is N, the processing time in the lower part of FIG. 6 is shortened by tc from the upper part of FIG. 6 in the entire parallel processing shown in the figure. This is a calculation in which the processing capacity is improved by about 21%, and shows that the processing capacity can be significantly improved by using the local synchronization method.

In FIG. 6, points A, B, and C respectively indicate the positions of the synchronization instruction S of Pl, Pm, and Pn at the level k-1. D,
The points E and F are the instruction ICD with shared system access executed for the first time in the tasks executed at the level k, respectively. Similarly, G, H, and I indicate the position of S at level k, and J, K, and L indicate the position of the first ICD appearing in the task executed at level k + 1.

As described above, this embodiment eliminates the fixed task boundary and precedes until it becomes necessary to access the shared system to exchange shared data first during task processing. Since it is possible to proceed with task processing as much as possible, idle processing time (processor idle time) accompanying waiting processing between processors during synchronous processing
Can be reduced. This makes it possible to dynamically change the task processing time according to the synchronization condition of each processor, shorten the critical path of parallel processing itself, obtain the same effect as data driven, and improve efficiency. Allows execution of parallel processing.

Further, according to the synchronous processing circuit of the present embodiment,
In a general-purpose multi-processor, when a fixed job is divided into tasks and parallelized for parallel processing, arbitrary processors that execute related tasks are grouped into a group and synchronized between processors within a group or between groups. By using the processing method, the synchronous processing mechanism between processes can be implemented as hardware in the software programmable range as much as possible.
This has the effect of minimizing the software overhead required for synchronization processing.

Next, a description will be given of an embodiment of an instruction set for a synchronizer between processors in which synchronous processing instructions are arranged in software so as to realize reduction of idle time during parallel processing by control flow. . Although a basic control flow by software can be realized by using the processor synchronous processing circuit of FIG. 4, in order to realize higher performance, each signal line 4 has a specific function 4a as shown in FIG. 4b and 4c are separated and used.

FIG. 7 is a block diagram showing the structure of a synchronization processing circuit according to another embodiment of the present invention. The signal line 4a is a signal for triggering a flip-flop that outputs task end information, and the signal line 4b is a trigger signal for registering a group in the synchronization register 5. The signal line 4c will be described later.

FIG. 8 shows the contents of the synchronous processing instruction.

In order to operate the synchronous processing circuit shown in FIG. 7, each processor n (n = 0, 1, ...) Has a corresponding synchronous processing element n (n = 0, 1, ...). S
Command a total of eight instructions YNCO to SYNC7. Each instruction has a mnemonic that expresses its function. That is, the basic functions are as follows.

GS ... Group setting (By registering a group in the synchronization register 5, it is indicated which processor composes the group) E
O: End-out (task end information is activated and output to the task processing end signal line 8 to indicate that the task has ended) W ... Wait (tasks of all processors in the group have ended, Puts the corresponding processor into a wait state until the synchronization processing is completed.
This is a function for finally confirming whether or not the processing is completed.) The following is provided as a composite instruction that can execute one machine instruction by combining the above basic functions.

GSEOW ... Group setting (G
Each function is continuously processed in the order of S) → end out (EO) → wait (W), and a series of synchronous processing is realized by one machine instruction.

GSEO ... Group setting (G
S) → End out (EO) in this order, each function is processed continuously.

EOW: Each function is continuously processed in the order of end out (EO) → wait (W). Previously GS
A series of synchronous processing is realized by one machine instruction for the group set by the function.

In addition, the following complex instructions are provided in order to speed up and simplify the processing on the processor side.

TSEOW ... Total setting (T
Each function is continuously processed in the order of S) → end out (EO) → wait (W).

TSEO ... Total setting (T
S) → End out (EO) in this order, each function is processed continuously.

Here, the TS is a basic function for instructing that all the processors are regarded as one group and synchronous processing is performed, and is called total setting. This is a function of activating the signal line 4C in FIG. 7 to set the value of the synchronization register to a mode in which all the processors are considered to belong to the group.

9 and 10 are explanatory views for explaining the task processing method.

The use and effect of the control flow will be described with reference to FIG.

FIG. 9 shows GSE which is an intra-group synchronization instruction.
8 shows parallel processing control by conventional synchronous processing performed using the synchronous processing circuit shown in FIG. 7 using only OW or EOW. The processor m and the processor n form a group. As described above, the respective processors declare each other that the processors m and n belong to the group when their respective tasks are completed. Then, the processors m and n wait for each other until all the task processing end signals from the processors m and n in the group output at that time become active, and thereafter, the processing is advanced to the next task so that parallel processing is performed without any conflict. Proceed with processing.

FIG. 10 shows the embodiment shown in FIG. 1 by using an EO instruction (outputting only task end information) and a W instruction (confirming that all task end information in the group has been output). Explained sharing system CSYS
The same effect as the automatic tuning function using data driven (data flow type) depending on the access condition to
This is an example realized by a control flow (top-down parallel processing is controlled by a command of a synchronization instruction by software). At the stage of performing the parallel processing, the compiler inserts appropriate synchronization instructions up to SYNCO to 7 shown in FIG. 8 at the point where the synchronization processing is performed in the program. The conditions for proper use of SYNCO to 7 are as follows.

(1) When a task of a certain processor ends, the relation between a task executed by another processor that terminates execution at the same level and a task to be executed next by the processor (arrows in FIGS. 9 and 10) ), Which is an instruction for outputting the task end information, is inserted. That is, FIG. 9 and FIG.
In the above example, the end time of task 3 and the end time of task 4 apply to this condition. In terms of the operation level of a processor, when one processor finishes a task and proceeds to the next task, it executes the EO instruction unless it needs information from another processor executed at the same level. It means that the process can proceed unconditionally to the next task.

(2) The processor that has executed the EO instruction at the previous synchronization level and moved to the task processing currently being executed,
When the next task to be executed at the end of the task has a relation with a task executed by another processor that ends execution at the same level, E executed at the previous level
The W instruction is executed as the synchronization check instruction corresponding to the O instruction to check whether the synchronization processing of the previous level is completed. After that, the synchronization process of the current synchronization level (for example, GSEOW
Or EOW) to proceed to the next task. That is, in the example of FIGS. 9 and 10, the end time point of task 5 applies to this condition. On the program, W and EOW may be arranged in this order at the end of task 5. The synchronization level here corresponds to the SYNC levels 1 to 3 in FIGS. 9 and 10, and refers to the point in time when the task processing at that level ends and the synchronization processing needs to be executed. In addition,
The difference between the GSEOW instruction and the EOW instruction is that GSEOW has a function (GS) of designating a processor belonging to a group, whereas EOW does not have that function. Therefore, when EOW is specified, the processor group configuration set by the previous GS function is used as it is as the default value.

The processing order of FIG. 10 will be described.

(A) It is assumed that task 0, task 2, task 4, task 6 are executed by processor m in this order.
It is assumed that task 1, task 3, task 5, and task 7 are executed by processor n in this order. Further, in this example, it is assumed that there is a relation shown by an arrow in the figure between each task.

(B) The processing results of task 0 and task 1 are used by task 2 and task 3 mutually. Therefore, it is necessary for the processors m and n to synchronize at SYNC level 1, and a series of synchronization processes from group setting to synchronization completion check are realized by one instruction by mutually executing GSEOW instructions.

(C) In SYNC level 2, task 4 uses the processing results of task 2 and task 3, and task 5 uses only the result of task 3. However, the group has not changed. Therefore, the processor m executes a series of synchronization processes from the output of the task end information to the synchronization completion check by the EOW instruction, and the processor n executes the EO instruction and continuously executes the next synchronization without performing the synchronization check (W). Go to processing.

(D) In SYNC level 3, task 6 needs only the processing result of task 4, and task 7 needs both processing results of task 4 and task 5. Therefore, the processor m executes the EO instruction and continuously advances to the next processor without performing the synchronization check (W).
On the other hand, the processor n executes the W instruction corresponding to the EO in the previous (SYNC level 2) to execute the SYNC level 2
SYNC check is performed, then the EOW instruction is executed and SY
After executing a series of synchronization processing of NC level 3 (that is, after confirming that task 4 is completed), the processing is advanced to the next task (task 7). From the above, it can be seen that the play times ta and tb generated in FIG. 9 are almost eliminated in FIG.

The features of the control flow system in this embodiment are listed below.

(1) If the relation between the tasks and the processing time are accurately known, it is only necessary to insert an appropriate synchronization instruction in the program according to the rule at the time of the parallelization schedule to be performed in advance, so that the play time is optimized. Tuning can be realized. When the automatic tuning is used, the relation between tasks cannot be strictly determined, and therefore the optimality is inferior to that of the present embodiment.

(2) Since no special hardware other than the synchronous processing circuit shown in FIG. 7 is required, the structure is simple.

[0076]

According to the present invention, a plurality of processors that share a plurality of tasks and perform parallel processing, a data sharing circuit that shares data exchanged between the processors, and a synchronization that synchronizes the plurality of processors. The task processing is completed and the synchronization processing is completed by including the processing circuit and the local synchronization circuit that controls conflicting access requests from the respective processors in the plurality to the data sharing circuit. If not, the processor can advance the next task processing as much as possible until the next task needs the shared data, so that the empty processing time can be reduced.

Further, when jobs are processed in parallel, the synchronous processing mechanism can be implemented by hardware by collecting related processors in a group and synchronizing them between processors within a group or between groups. The effect of minimizing the software overhead required for is obtained.

By combining the control flow for controlling the parallel processing in a top-down manner with the software synchronous instruction and the automatic tuning of the data flow by the hardware, the idle time of the processor can be further minimized and the optimum parallelization can be achieved. It is possible to achieve efficiency.

[Brief description of drawings]

FIG. 1 is a hardware block diagram showing an overall configuration according to an embodiment of the present invention.

FIG. 2 is a system diagram showing a configuration of a signal control circuit shown in FIG.

FIG. 3 is a system diagram showing an embodiment of the synchronization processing circuit shown in FIG.

FIG. 4 is a system diagram showing another embodiment of the synchronization processing circuit shown in FIG.

FIG. 5 is an explanatory diagram showing an example of control of parallel processing by synchronous processing between processors of the present invention.

FIG. 6 is an explanatory diagram showing the effect of shortening the processing time when using local synchronization according to the embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a synchronization processing circuit according to another embodiment of the present invention.

FIG. 8 shows the contents of a synchronization processing instruction according to another embodiment of the present invention.

FIG. 9 is an explanatory diagram illustrating a relationship between a task and a synchronization processing instruction according to another embodiment of the present invention.

FIG. 10 is an explanatory diagram illustrating a relationship between a task and a synchronization processing instruction according to another embodiment of the present invention.

[Explanation of symbols]

1 Processors that make up a multi-processor 2 Synchronous processing element 4 Access signal line to synchronous processing element 4a signal line 4b signal line 4c signal line 5 Synchronization register 6 Judgment circuit 7 Philip Flop 8 task processing end signal line 9 Status signal line (task end information line) 120 shared system bus l21 arbitration line 50n signal control circuit 51n Local sharing system 100n processing unit 101 Synchronous processing circuit 102 sharing system 103 Arbitration circuit

Claims (9)

[Claims] 1. A plurality of processors that share a plurality of tasks and perform parallel processing, a data sharing circuit that shares data exchanged between the plurality of processors, and a synchronization that synchronizes the plurality of processors. A synchronization processing device between processors, comprising: a processing circuit; and a local synchronization circuit for controlling competing access requests from the respective processors in the plurality of data sharing circuits. 2. The synchronous processing circuit inputs task end information output by a processor that has completed a task, and after all the task end information output by some processors that process related tasks have changed to active. From the task end information, the processor to be synchronized outputs an active value to the corresponding processor as the synchronization end information indicating that the task processing has ended, and the local synchronization circuit outputs the task end information to the processor that outputs the task end information. The access is prohibited and the operation of the processor is suspended if the synchronization end information corresponding to the access to the data sharing circuit is not output as an active value from the synchronization processing circuit. A synchronous processing device between processors according to. 3. The synchronization processing circuit forms a group of processors that process related tasks when performing parallel processing, and synchronizes between the processors in the group or between the groups. The synchronous processing device between processors according to claim 1, further comprising: 4. The synchronization means is triggered by access to the synchronization register, which stores information corresponding to the names of the respective processors forming the group output by one processor in the group, and access to the synchronization register. Flip-flop, a first transmission circuit for transmitting the state of the flip-flop to another processor, the transmitted state of the flip-flop and the stored contents of the synchronization register, and the synchronization register A decision circuit for deciding whether or not each processor in the group stored in the group is active, and a decision result output by the decision circuit for transmitting to the one processor in the group via the flip-flop. 4. The inter-processor synchronization processing device according to claim 3, further comprising: 5. The synchronization means is triggered by access to the synchronization register, which stores information corresponding to the names of the respective processors forming the group output by one processor in the group, and access to the synchronization register. A flip-flop, a first signal transmission means for outputting a trigger signal for outputting the task end information from the processor to the flip-flop, and the synchronization register storing a group of processors. Second signal transmission means for outputting a trigger signal to the synchronizing register from the processor, and an active signal from the processor for setting the value of the synchronizing register so that all the processors belong to the group. And a third signal transmission means for outputting to the register. The synchronous processing device between processors according to claim 3. 6. Synchronizing processing between a plurality of processors,
In a synchronous processing device between processors that controls parallel processing without contradiction, means for outputting active task end information at the time when each processor finishes a task corresponding to each processor, and a processor to be synchronized When all the task end information becomes active, and means for deactivating the active task end information corresponding to each processor using the information, and that the processor checks the task end information and finishes the synchronization processing. And a means for confirming that the synchronous processing device between processors. 7. The processor comprises means for instructing each processor to issue an EO instruction for instructing the output of the active task end information and a W instruction for confirming that the synchronization processing has been completed. A synchronous processing device between processors according to. 8. At the end of the task of one processor,
If there is no relation from a task executed by another processor that terminates execution at the same level to a task to be executed next by the processor, insert the EO instruction,
When the processor terminates a task and proceeds to the next task, if the information from another processor executed at the same level is not needed, the EO instruction is executed to unconditionally proceed to the next task. 8. The inter-processor synchronization processing device according to claim 7, further comprising means for advancing the processing by. 9. The processor which executes the EO instruction at the previous synchronization level and shifts to the currently executed task processing,
When the next task to be executed at the end of the task has a relation with a task executed by another processor that ends execution at the same level, as a synchronization check instruction corresponding to the EO instruction executed at the previous level. Execute the W command to check whether the previous level synchronization processing has finished,
9. The inter-processor synchronization processing apparatus according to claim 8, further comprising means for performing a synchronization processing of the current synchronization level and advancing the processing to the next task.