SU1749896A2 - Multichannel priority device for interfacing common bus - Google Patents

Abstract

The invention relates to computing and can be used in 5 multi-machine and multiprocessor computing systems. The purpose of the invention is to expand the field of application of the device by servicing requests with discipline with both relative and absolute priorities, taking into account the waiting time in the queue. Achieving the goal is provided by introducing 14 pulses, counters 15, I TB, 17 elements and AND elements into the device. - NOT 18, 19 The device allows to connect sources of information to a common highway taking into account the priorities of the channels and to move from a discipline with relative priorities to a discipline with absolute values. ioritetami if the waiting time of the service request exceeds the threshold 1 yl / J- U E VI 00 4 U O O N3

Description

The invention relates to computing, can be applied in multi-machine and multiprocessor computer systems using a common trunk for data exchange, and is an improvement of the invention according to the author. St. No. 1386994.

A multichannel priority device is known for connecting to a common highway containing signal outputs, channels, each of which includes a request input, AND elements, triggers, a delay element, a pulse shaper, and an information output, each request channel being connected to the first inputs of the first and second And elements and the pulse driver input, the output of which is connected to the reset inputs of the first and second triggers, the zero output of the first trigger is connected to the second input of the first element I, the output of which is It is connected to the second input of the second element I and the single input of the first trigger, the unit output of which is connected to the third input of the second element I, the output of which is connected to the input of the delay element whose output is connected to the first input of the third element I whose output is connected to the single input of the second a trigger whose unit output is an information output, the zero output of the second trigger is connected to the second input of the third And element and the second signal output of the device, the first signal output of the devices and is connected to the zero outputs of the first triggers of all channels, the third signal output of the device is connected to the reset inputs of the second triggers of all channels. The device provides priority access to a common trunk (OM) of information sources for transmitting messages to consumers, regardless of the length of waiting for these messages (service requests) in the transmission queue.

However, in a number of cases in real-time computing systems, it is advisable to apply such a priority discipline, in which the importance of a request increases abruptly when the waiting time reaches a threshold value, and an interruption in service of a lower priority request occurs in order to service a higher priority request, time waiting for which reached the threshold value (the interruption of higher priority requests by lower priority does not occur). Such a discipline is mixed, since at certain stages of the operation of a computer-to-machine computer system

(interprocessor) exchange is carried out in accordance with the discipline with relative, and at other stages with absolute priorities. When using this

discipline rises equivalent system performance compared to discipline with relative priorities.

The known device does not provide

0 implementation of a mixed discipline of servicing requests for the capture of a common highway.

The purpose of the invention is to expand the field of application of the device by servicing requests with discipline with both relative priorities and absolute ones, taking into account the waiting time in the queue.

Into the multichannel device of priority for connection to the common highway, they are additionally introduced into the first channel - the pulse generator, the counter and the AND element, into the Mth channel - the AND element and two AND-NES elements, into the K-channel (K 2 .. M-1) - generator

5 pulses, a counter, two AND elements and two NAND elements, and on the N-th channel (H 1 ... M-1) the output of the pulse generator is connected to the first input of the fourth And element, the second input of which is connected to the request input. device and the reset input of the counter, the counting input of which is connected to the output of the fourth element I, in the nth channel (P 2. .M) the output of the first element AND-NOT connected to the first input of the second element n5 that IS-NOT, the second input of which is connected with a single output of the second trigger, and an output with the first input of the fifth element I, the second input of which from It is one with the device's request input, and the output is with the pulse forwarder input, the output of the N-th channel counter (H 1 ... M-1) is connected to the N-th input of the first AND-NOT element of each of the subsequent channels.

The drawing shows a structural

5 device diagram.

The device contains signal outputs 1-3, M channels 4, which include request inputs 5, elements 6-8, flip-flops 9 and 0, delay elements 11, shaping 12 pulses, information outputs 13, generators 14, counter 15. elements And 16 and 17. elements AND-HE 18 and 19

The device works as follows.

5In the initial state, triggers 9 and 10 and

the counters 15 of all channels are in the zero state; the inputs 5 of all channels 4 from the corresponding information sources (for example, computers) receive logical zero signals, which causes the presence of

signals of the logical unit (high levels) at the first and second signal outputs of the device and logic zero signals at the information outputs of 13 channels (computers can output information in the OM if there are single signals at the outputs of 13 corresponding channels) and the third signal output of the device 3, at the outputs of counters 15 set the signals of the logical unit.

Combining the outputs of the device elements on the first and second signal outputs of the device implements the function Wired AND, and on the third signal output - Wired OR.

At random points in time, computers are pushed into their buffer memory cells for messages to be transmitted through a common backbone (GM). Each source of information is connected via request input 5 and information output 13 to the corresponding channel 4 (sources of information and OM are not shown). When a computer has a computer, a message on input 5 of the corresponding channel 4 sets a signal of logical unit (this signal disappears when the corresponding memory cell is released).

Next, we consider the operation of the K-th channel 4 (K 2 ... M-1), since there are most of them in the device, and for the first and last channels there are features caused by the fact that the first channel is the highest priority (the priority of the channels decreases with increasing number channel) i.e. its operation cannot interrupt another channel; therefore, it does not contain elements 17–19 intended for other channels for channel interruption, and the last channel is the least priority, i.e. it cannot interrupt other channels, so it does not contain elements 14–16 intended for other channels to form a signal to interrupt lower priority channels when the message waiting time for transmission through the OM has reached a threshold value.

A single signal from the request input 5 in the channel under consideration (for example, the second one), having passed through the open element 6, sets trigger 9 into one state, which causes the signal 0 to establish the first signal output of the device and, therefore, close the 6 elements all channels 4 (i.e. requests from a computer to acquire OM from a given point in time on the triggers of 9 channels are not fixed). The same signal (from the request input 5) opens the element AND 16, through which the counter 15 begins to receive pulses from the generator of 14 pulses, counting the waiting time of the message in the transmission queue through the OM (in the last

channel this does not occur, as it is the least priority).

After the logical unit signal of the trigger 9 is established at the single output and until the single unit is lost

0 signal at the output of the element And 6 at the output of the element And 7 sets the signal of the logical unit, which, after passing through the delay element 11 and the open element And 8 sets the trigger 10 to unity. The delay on the delay element 11 in each channel, starting from the first one, increases compared with the previous channel by an amount of time interval greater than that necessary for the passage

0 signal on elements 8 and 10 and signal

the second output of the device between two

the most distant channels 4. At the same time

the possibility of simultaneous

 Connect several channels to OM.

5 The signal from the single output of the trigger 10 via the information output 13 of channel 4 signals the corresponding computer that the OM is captured and information can be transmitted. At the same time, the signal of the logical zero from the zero output of the trigger 10 through the signal second output of the device closes 4 And 8 elements in all channels, and if simultaneous attempts were made to capture OM from other channels that have a lower priority (more than the signal delay time element 11) than this channel 4, they (attempts) are blocked. After the computer connected to this channel 4 finishes transmitting the message, it sets the logical zero signal at the request input 5 of its channel. By the negative signal level difference at the request input 5, the counter 15 is reset and the pulse shaper 12 in this channel 4 generates a single pulse that sets the triggers 9 and 10 of this channel (and through the signal output 3 of the trigger, 9 where the implementation is a simultaneous attempt to capture the OM in the zero state. If, when a signal arrived at the request input 5 of the second channel, 4 MDs were occupied by a less priority channel (a channel with a large

5 by the number, for example, the last) and by the time T TCH + Tn (where Ti is the time of arrival of the message in the cell of the buffer memory of the second computer, Tn is the waiting time of the message in the transmission queue, after which the service should be interrupted

any less priority message) the last channel did not release the OM, then at this moment at the output of the counter 15 of the second channel there is a zero signal that will go to the last channel to the second input of the AND-HE element 18, causing its output, i.e. at the first input of the element AND-NOT 19, the signal of the logical unit. Since the signal of the logical unit is also set at the second input of the NANDI element 19 (since the last channel captured the OM and its trigger 10 is in the one state), the output of the NANDI element 19 results in a zero signal, which will provide the output of the AND 17, a zero signal, at the occurrence of which the pulse shaper 12 will form a single pulse, which will set the triggers 9 and 10 to the zero state, and the channels will start to pick up the OM again, as a result of which the second channel will capture the OM minutes than the last), and computers, the connection to the last channel, is forced to interrupt issuing messages to the OM, since the information output 13 of its channel at Vits zero signal. After the second computer has finished transmitting the message and has released the OM (if during this time no more priority request has been received), the last computer will capture the OM and continue the transmission of the interrupted message. Further, the operation of the device is repeated. Since the first channel is the highest priority, its messaging sessions cannot be interrupted by other channels.

Thus, the proposed device allows to realize a mixed discipline of servicing requests for seizing OM, taking into account the priorities of information sources and the waiting time of messages in the queue for transmission through OM.

Due to the fact that the proposed device does not create savings, but gives a different positive effect - it takes into account the importance of requests, which increases with an increase in the time they wait in the service queue, which improves the equivalent performance of the computing system, performs a comparative analysis of the proposed and known devices, since the well-known most effectively implements the functions of priority connection of information sources to the common highway.

The known device implements the processing of requests on the basis of a discipline with relative priorities, the proposed one allows, in cases where requests are long waiting for service, to switch to discipline with absolute priorities and get a gain in equivalent performance, since the delay in processing less important messages leads to

less loss of computational system efficiency than the delay of more important messages. From the methodology for evaluating the effectiveness of a mixed discipline compared to a discipline with relative priorities, it follows that with a device load of 0.9, the gain in equivalent performance when applying the proposed device compared to the known one is about

15%.

Claims (2)

Multi-channel priority device for connecting to a common trunk via auth. St. No. 1386994, except that, in order to expand the scope of application by servicing requests with discipline with both relative priorities and absolute ones, taking into account the waiting time in the queue, it is additionally entered into the first channel - the generator impulses, the counter and the element And, in the M-th channel - the element And and two elements AND-NOT, in the K-th channel (K 2 ... M-1) - generator pulses, a counter, two AND elements and two NAND elements, in addition, in the NM (H 1 ... M-1) channel, the output of the pulse generator is connected to the first input of the fourth And element, the second input of which is connected to the request input of the device and the reset input of the counter, the counting input of which is connected to the output of the fourth element I, on the П-м channel (П 2 ... М) the output of the first AND-NOT element is connected to the first input of the second AND-NOT element, the second input of which is connected to the unit the output of the second trigger, and the output with the first input of the fifth element I, the second input of which is connected n with the device's request input, and the output with the pulse driver input, the output of the N-th channel counter (... M-1) is connected to the N-th input of the first AND-NOT element of each of the subsequent channels,