SU1241252A1 - Device for studying parameters of graph - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to solve problems of research of communication systems, computer networks, etc. on graphs. The purpose of the invention is to extend the functionality by defining essential vertices between two end points (L C JE 4 a A

Description

tops. The device contains the first 1 and second 2 switches, the first 3 and second 4 encoders, register 5, the third group of elements 6 AND, the first 7 and second 8 groups of multiplexers, the group of registers 9, the matrix of keys 10, the matrix 1 of switching diodes 12, the first 13 and The second 14 groups of elements are And, the decoder 15, the third invention relates to computing technology and can be used to solve problems of research of communication systems, computer networks, etc. on graphs.

The purpose of the invention is to expand the functionality by defining essential vertices of me: u two end peaks.

The drawing shows a functional diagram of the device.

The device contains the first 1 and second 2 switches, the first 3 and second 4 encoders, register 5, / third group of elements AND 6, first 7 and second 8 groups of multiplexers group of registers 9, matrix of pn keys 10 (n is the number of graph nodes) , the matrix 11 of the switching diodes 12, the first 13 and the second 14 groups of elements And, the decoder 15, the third switch 16, the element NOT 17, the first 18 and the second 19 elements And, the generator 20 clock pulses and the counter 21.

Initially, the topologies of the graph under study are dialed using switching diodes 12, and the registers 5 and 9 and the counter 21 are fed to the device installation signal. Using switch 1, the number nd is dialed, and using switch 2, the number of the i-th vertex is the set of essential vertices belonging to at least one path from the xth vertex to the jth is determined. Using switch 16, the number of vertices in the graph under study is dialed.

The device works as follows.

switch 16, element NOT 17, first 18 and second 19 elements And, 20 clock pulse generator, counter 21. By sequentially polling matrix 11, it is determined that all graph vertices from each vertex are reached jKHMOCTb, and on the basis of this - a set of essential graph vertices, 2 silt

After a single potential is applied to the starting input of the device. The pulses from the generator output 20. Through the element 18, arrive at the first input of element 19, the second input of which supplies a single potential from the output of the element 17. The clock pulses from the output of the element 19 19 TIOC Yes, the information input of the counter 21. Depending on the state of the counter 21, the corresponding output of the decoder 15 appears as a single potential, which opens the corresponding keys 10 of the corresponding register 9, and also goes to the corresponding pole tsy matrix I1. Since a single potential from the output of the element NOT 17 is supplied to the second inputs of the AND 13 elements, the single potential from the corresponding output of the decoder 15 through the corresponding column of the matrix 11 and the corresponding element AND 13 enters the inputs of the corresponding element And 14, as well as the information inputs of the corresponding keys 10 Through the key 10, the control input of which receives a single potential from the output of the decoder 15 ,, eDinitsa is recorded in the corresponding bit of the corresponding register 9. If between line e and column d Since the matrix 11, diode 12 is installed in the conducting direction, which corresponds to the arc from the vertex e to the vertex d, then the unit potential from the output of the element AND 14e enters the column d and through the element 13 and records to the discharge d of the corresponding register 9 unit. This continues until the counter 21 receives k clock pulses.

3

In this case, in each register 9, the corresponding row of the reachability matrix of the graph under study will be written, and the register number corresponds to the number of the row of this matrix. After the appearance at the k-th output of the decoder 15 of a single potential (in the counter

2, the number k is written. At the output of the element NOT 17, a potential of zero appears, which prohibits the passage of pulses of the generator 20 through the element And 19, and the number 21 is recorded in the counter 21. The same potential from the output of the element HE closes the elements AND 13. The multiplexers 7 and 8 have, according to n, information inputs connected to the outputs of the corresponding register bits 9 so that the multiplexers 8 commute to the first inputs of the elements AND 6 bits of the corresponding register 9 the number of which is dialed by switch 2 and converted to binary code by encoder 4 (i.e., elements of the corresponding row of the accessibility matrix), and multiplexers 7 commute to the second inputs of elements And 6 the corresponding bits of registers 9 depend ing on the vertex number dialed switch 1 and converted into a binary code encoder 3 (i.e., elements corresponding inverse reachability matrix rows). After the k-ro clock arrives at the counter 21, at the output of the switch 16, a single potential appears, which enters the third inputs of the And 6 elements and allows the multiplication of the row elements of the corresponding reachable matrices and inverse reachability matrices. The results of the multiplication are recorded in the corresponding bits of register 5 and are indicated, for example, by means of LEDs.

Invention Formula

A device for studying graph parameters containing a clock pulse generator, two AND elements, a NOT element, a counter, a decoder group of registers, a matrix of keys (n is the number of graph vertices), two groups of And elements, and a php matrix of switching diodes, the lines of which through commuting the diodes are connected to the corresponding columns according to

2524

topology of the graph, the rows of the matrix of commenting diodes are connected to the outputs of like elements of the first group, the outputs of the columns of the matrix of switching diodes are connected to the first inputs of like elements of the second group, the outputs of which are connected to the inputs of like elements of the first group and the information inputs of keys of the same name rows of matrix keys, the key outputs of the columns of the matrix of keys are connected to the information inputs of the same name registers of the group, the installation inputs of which are combined with the installation inputs the house of the counter and the driver the installation input of the device, the starting input of which is the first input of the first element AND, the second input of which is connected to the output of the clock generator, the output of the first element AND is connected to the first input of the second element AND whose output is connected to the information input of the counter The output of which is connected to the input of the decoder, the outputs of which are connected to the control inputs of the keys of the same name columns of the matrix of keys and the inputs of the same columns of the matrix of switching diodes, This is NOT connected to the second input of the second element AND and the second inputs of the elements of the second group, characterized in that, in order to extend the functionality by defining the essential vertices of the Melsda with two terminal vertices, two multiplexer groups are introduced into it, a third group of elements AND, register, two encoders and three switches, where the inputs of the first and second switches are combined and are the input of the unit potential of the device, and the outputs are connected to the inputs of the same encoders, the outputs of the first and second encoders are connected to the address inputs of multiplexers of the same name, the outputs of multiplexers of the second group are connected to the first inputs of the same elements of the third group, the outputs of the multiplexers of the first group are connected to the second inputs of the same elements of the third group, the outputs of which are connected to the information inputs of the register, the installation input of which is the installation input of the device, the third inputs of the elements AND the third.

5 -12412526

the groups are combined with the input of the element () register groups are connected to

NOT and connected to the output of the third i-th informational input of the j-ro multi switch, the inputs of which are a sub-typelexer of the first group and the j-th are connected to the same output by the decoding input of the i-ro multiplexer, and the i-th (, n) output j-rosor of the second group.

Claims (1)

Claim A device for studying the parameters of a graph containing a generator of 50 clock pulses, two AND elements, an element NOT, a counter, a descrambler> a group of registers, a matrix of n * n keys, (n is the number of vertices of the graph), two groups of AND elements and a matrix ηχη comm diodes, the rows of which are connected through switching diodes to the corresponding columns according to 252 4 graph topologies, and the rows of the matrix of commuting diodes are connected to the outputs of the elements of the same name And the first group, the column outputs of the matrices of commuting diodes are connected to the first inputs of the same elements And the second group, the outputs of which are connected to the inputs of the same elements And the first group and information inputs of the keys of the same lines key matrices, key outputs of the key matrix column columns are connected to the information inputs of the group registers of the same name, the installation inputs of which are combined with the installation inputs the meter’s house is the installation input of the device, the starting input of which is the first input of the first element And, the second input of which is connected to the output of the clock generator, the output of the first element And is connected to the first input of the second element And, the output of which is connected to the information input of the meter, the output of which connected to the input of the decoder, the outputs of which are connected to the control inputs of the keys of the same name columns of the key matrix and the inputs of the same name columns of the matrix of switching diodes, the output of the element is NOT connected to the second input of the second AND element and the second inputs of the AND elements of the second group, characterized in that, in order to expand the functionality by defining significant vertices between the two end vertices, two groups of multiplexers are introduced into it, a third group of AND elements, a register, two encoders and three switches, and the inputs of the first and second switches are combined and are the input of setting the unit potential of the device, and the outputs are connected to the inputs of the encoders of the same name, the outputs of the first and second the speakers are connected to the address inputs of the multiplexers of the same groups, the outputs of the multiplexers of the second group are connected to the first inputs of the same elements And the third group, the outputs of the multiplexers of the first group are connected to the second inputs of the same elements And the third group, the outputs of which are connected to the information inputs of the register, the installation input of which is the installation the input of the device, the third inputs of the elements And the third. s groups are combined with the input of the element NOT and connected to the output of the third switch, the inputs of which are connected to the outputs of the decoder of the same name, and the ith (i = l, n) output of the jth (j = l, n) register of the group is connected to ί- m information input j-ro mul ¹ typlexer of the first group and j-m. information input of the ί-th multiplexer of the second group.