SU1238164A1 - Multichannel device for checking memory - Google Patents

Abstract

This invention relates to. computing and can be used in the control of storage devices. The purpose of the invention is to increase the reliability of the control and speed of the device. The device contains L-IN memory access channels connected via switch 15 to block 17 of monitored memory. The synchronization of the channels is carried out by the synchronization unit 14 and the generator of 16 clock pulses. The control unit 17 is carried out by serially connecting channels to it, which allows the control unit 17 to be monitored at its maximum working frequency and with various combinations of addresses. The device can operate in control modes modulo three, check totalization, comparison with reference information. 1 hp ff, 5 ill. CO 1C with 00 O5 4:

Description

The invention relates to computing and can be used to control memory blocks.

The purpose of the invention is to increase the reliability of the control and speed of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - the same block synchronization; in fig. 3 - the same, the additional device operates as follows.

Initially, using the switches 31 of the control unit 6, the channels are tuned to perform a specific mode (control modulo three, check totaling, comparison with a reference block or comparison with a standard punched tape). In the initial state, the clock signal frequency of the clock from the generator 16 is fed to one of the inputs of the element 22. At the other

tator of control channels; in fig. 4 - Yu input element 22 is allowing

that

the same, control unit; in fig. 5, the clock generator.

The device contains (Fig. 1) channels li - IN of the access to the memory, each of which consists of counter 2, the decryption potential from the element OR 21. This potential changes to forbidding only when the device detects a malfunction in the memory 17 being checked . From the output of the element I.22 signal arrives at

3, the generator of 4 cycle signals, the input of the generator 19, generating modulo three convolution unit 5, the control unit 6, the initial start signal, and the division input, switch 7, the input unit 8, the frequency generator 20. From the outputs of the splitter formation, register 9 control information-20, the frequency signals are received according to the error analysis block 10, gen- erally at the inputs of the first and second channels, the clock of the synchronization signal 11, the first 12 and the second. the elements of the OR of the block 17, then to one, then to the other. The device also contains a block of the 14th control channel,

synchronization, additional 15 switch and generator 16 clock pulses. The device is connected to a monitored memory unit 17. The control output 18 25 of the unit 14 is connected to the control input of the switch 17.

The synchronization unit 14 comprises (FIG. 2) a single pulse generator 19, a frequency divider 20, an OR element 21, an AND element 22 and a delay element 23.

Switch 15 contains (FIG. 3) elements AND 24 intended for switching information transmitted from block 17 of monitored memory to the channels of elements

Consider the operation of the device in one of the control modes, for example, in the control mode modulo three.

When starting the device, the start signal from the generator 19 output goes through the element 21 to the control units 6 of both channels. Let the li channel be the first to turn on. In the first cycle, channel 1i transmits from counter 2 through switch 7, the element AND 25i 30 and the element OR 26 to block 17, the address (say, A1) and control signals. In the same cycle, channel 1 receives from block 17 through the element AND 24i and the switch 7 controlled information into register 9. After the exchange

And 25, intended for switching information, switching of the address and control signals, the OR element by switching the trigger 27 | to zero, and 26, intended to combine the signal trigger 27 into one. On your work

Frequency comes to work channel b. In the first cycle, exactly the same actions as for the channel occur, but the address in block 17

The control unit 6 of each channel will arrive differently - the one that is contained in contains (fig. 4) the first 28, the second 29 and the meter 2 of the channel b (for example, B1). The rooms are transmitted to the block 17 and the triggers 27, designed to control the switching elements And 24 and 25.

the third 30 single signal generators, switches 31 for setting the channel operation mode, triggers 32, starting address register 33 and AND elements 34-39.

The clock signal generator 11 contains (FIG. 5) a switch 40, a decipher 41, a counter 42, an OR element 43, AND 44 and 45 elements, a clock frequency generator 46 and a trigger 47.

When assembling a device (choosing its specific structure), it is necessary to determine the number of memory access channels required from the ratio N -j-, where N is the number of channels; F - maximum operating frequency controlled

so again, switching channels, etc. Thus, channels b and b, operating in optimal modes, provide control of memory block 17 at its operating frequency, which is twice the working frequency of the channels. In this particular control mode, in the second call, information from block 17 will go to error analysis block 10 for comparison with the information stored in register 9 and received from block 17 at the same address in the first call to it. Such references and comparisons of information will continue as long as in block 5 the convolution is modulo.

memory blocks; f - operating frequency of the channel. Three control codes are not generated.

addresses and data. After that, they arrive at block 10 for comparison with the control codes obtained from block 17. If these codes are equal, block 6 is transmitted

To explain the operation of the system, let us specify the value MHz, f 1 MHz, then.

The device works as follows.

Initially, using the switches 31 of the control unit 6, the channels are tuned to perform a specific mode (control modulo three, check totaling, comparison with a reference block or comparison with a standard punched tape). In the initial state, the clock signal frequency of the clock from the generator 16 is fed to one of the inputs of the element 22. At the other

 input element And 22 enters allowing

goma control channel,

Consider the operation of the device in one of the control modes, for example, in the control mode modulo three.

When starting the device, the start signal from the generator 19 output goes through the element 21 to the control units 6 of both channels. Let the li channel be the first to turn on. In the first cycle, channel 1i transmits from counter 2 through the switch 7, the AND 25i element and the OR 26 element to the block 17, the address (say, A1) and the control signals. In the same cycle, channel 1 receives from block 17 through the element AND 24i and the switch 7 controlled information into register 9. After the exchange

information is switching kate again switching channels, etc. Thus, the channels b and b, operating in optimal modes, provide control of the memory block 17 at its operating frequency, which is twice the working frequency of the channels. In this particular control mode, in the second call, information from block 17 will go to error analysis block 10 for comparison with the information stored in register 9 and received from block 17 at the same address in the first call to it. Such conversions and comparisons of information will continue until block 5 modifies the convolution codes.

the signal on which it generates a signal to add one to the contents of counter 2, which enters it through the element OR 12. Next, the device proceeds to perform similar work at the following address. Similarly, there is work in other control modes.

In all modes, the operation of the channels is performed within the array, limited by the start and end addresses. These addresses are set by the operator before starting work and can be either the same or different (within the addressing address of the monitored unit 17). The cyclic check of the specified array is organized by the formers 4. For this purpose, the formers, at the time of coincidence of the current and end addresses, give the channel setting signal to the initial state, then organize the transfer of the starting address to the counter 2, and generate a signal for the starting start of the corresponding channel.

Checking the memory block 17 when monitoring devices are accessed to different parts of the checked array ensures its control during various (inconsistent) references to it. For example, if in the first channel we set the start address of the tested array A1, and in the second B1, then the sequence of calls to the monitored block will look like A1, B1, A1, B1, A2, B2, A2, B2, A3, BZ, A3, BRs, etc. From this sequence it can be seen that in each call to memory block 17 occurring at its operating frequency, the addresses change from sequence A to sequence B.

The reaction of the device when a failure is detected in the memory block 17 will be the same in all control modes. It consists in generating a signal “Fault by the error analysis block 10 in the channel that detected this fault. This signal will go in this channel to block 6 and to block 14 of the synchronization on the input of the element OR 21. Block 6 will stop the channels on this signal and record the address and nature of the fault, and in block 14 of the synchronization, the inhibit signal from the output of the OR 21 will go to input element And 22 and provide a blocking signal clock frequency. The device will stop working. In the channel that detected the error, the address and nature of the fault will be fixed, in the other channel the address will be fixed, after which the detected error occurred. According to this data, it is possible to start the device under the conditions that led to the detection of a malfunction. ,

Claims (2)

Invention Formula I. A multichannel memory control device containing a access channel. Oh 0 five 0 5 five memory consisting of a counter, decipher, control unit, switch, information input unit, error analysis unit, clock generator, loop generator, modulo three convolution unit and control information register, whose input is connected to the first switch output , the first input of which is connected to the first output of the counter, the first input of the loop signal generator and the input of the decipher, the output of which is connected to the second input of the switch, the second output of which is connected to the first input of the error analysis block, the second input and the first output of which are connected respectively to the first output and input of the control unit, the second output and input of which are connected respectively to the input and the first output of the information input unit, the second output of which is connected to the third input of the switch, the third output and the fourth input of which the first output and the channel input, respectively; the fifth input of the switch is connected to the output of the clock signal generator, one of the inputs of which is connected to the third output of the control unit, the fourth output of which is connected It is connected to the second input of the cycle signal generator, the output of which is the second output of the channel, the fifth output of the control unit is connected to the first input of the convolution unit modulo three, the output of which is connected to the third input of the error analysis unit, the fourth input of which is connected to the output of the control information register and the second input of the convolution unit modulo three, the third input of which is connected to the second output of the counter, characterized in that, in order to increase the reliability of the control and speed of the device, additional memory access channels, a clock generator, a synchronization unit and an additional switch, and the first and second OR elements are inserted into each memory access channel, the clock pulse output is connected to the input of the synchronization unit, the outputs of the first group of which are connected to the first the inputs of the first OR elements, the outputs of the second group are connected to other inputs of the sync signal generator, the inputs of the synchronization unit group are connected to the outputs of the error analysis blocks, and the output is connected to the control input additional switch, one of the inputs and outputs of which are connected respectively to the fourth outputs and the other inputs of the channel switches, and the other inputs and outputs are the inputs and outputs of the device, the second input of the first OR element of each channel is connected to the output of the corresponding cycle signal generator, the output of the second element OR of each channel is connected to the input of the corresponding counter, the first input is the second input of the channel, the second input is connected to the other output of the corresponding control unit, the third input is connected to the output of the corresponding first OR gate. 2. The device according to claim 1, characterized in that the synchronization unit comprises a single pulse generator, a frequency divider, delay elements, an OR element and an AND element, the first input of which is connected to the output of the OR element, and the output of the AND element are connected to the input of a single pulse generator and to the input of a frequency divider, the outputs of which are connected to the inputs of the delay elements whose outputs as well as the frequency divider and output of the single pulse generator are the outputs of the block whose inputs are the second input element AND the inputs of elements OR. n1ek 8 FROM KP From b omfO fae. five