SU1236556A1 - Analog storage - Google Patents

Abstract

The invention relates to computing and instrumentation. The purpose of the invention is to increase the speed of an analog memory device. The device contains a switch, the first and second memory cells, respectively, with inversion and without inverting the output voltage, three resistors and an operational amplifier (op-amp). In the sampling mode, the first memory cell repeats the input voltage of the device, inverts its sign, and the second memory cell included in the negative feedback circuit of the OU stores the error voltage introduced by the first memory cell and the OU. In the storage mode, the errors of the active elements in the memory cells and OU are compensated. Unlike the known devices with remembering the input voltage and the error voltage on the corresponding memory cells, the proposed device is characterized by a higher speed, because in it the OU in sampling mode monitors the error voltage, the amplitude and rate of change of which is much less than the corresponding parameters of the input voltage wives 1 il. sl N5 SA :) 05 ate C71 ot

Description

The invention relates to an analog technique and can be used to store selective values of an analog signal.

The purpose of the invention is to increase the speed of an analog device.

The drawing shows a functional diagram of the device.

The analog memory device contains a switch 1, cells 2 and 3, respectively, with inversion and without inverting the output voltage, three matching elements on resistors 4-6 and an operational amplifier 7.

Analog storage device operates as follows.

In fetch mode, switch 1 connects the input of the device to the output of resistor 5, with the memory cells 2 and 3 having a closed state of the keys and operating in tracking mode. At the same time, the voltage at the output of the memory cell 2 repeats the input voltage of the device, but with the opposite sign, and the memory cell 3 of the memory connected to the negative feedback circuit of the operational amplifier 7 monitors the sum of the input voltage of the device and the output voltage memory cells 2, i.e., the inversion of the input voltage at the memory cell 2, taking into account the summation error introduced by the operational amplifier 7. When switching to the storage mode, memory cells 2 and 3 remember the inverted input voltage, respectively. and the total error of the active elements of the device, reduced to the output of the operational amplifier 7, and the switch 1 connects the output of the resistor 5 to the output of the device. At the same time, the output voltage of the operational amplifier 7 sets the input voltage of the device at the moment of transition from the sampling mode to the storage mode, and the faults introduced by the active elements (voltage followers in the memory cells 2 and 3 and the operational amplifier 7) are suppressed.

In the proposed device, it is advisable to use the most high-speed voltage repeaters in the composition of the cells 2 and 3 of memory, made on open

scheme, since rather significant faults of such repeaters in the device are compensated. In contrast to the known devices with memory input voltage and error voltage on the corresponding memory cells, the proposed device has a higher speed, because the operational amplifier 7 in this device in sampling mode monitors the error voltage, the amplitude and rate of change of which is significantly

less than the corresponding input voltage parameters. Consequently, with respect to the known devices, the operational amplifier of which, in the sampling mode, monitors the input voltage, the proposed device makes it possible to remember more

rapidly varying input signals whose rate of change exceeds the maximum slew rate of the operational amplifier.

Claims (1)

Invention Formula An analog storage device containing the first and second memory cells, an operational amplifier whose output is the output of the device and is connected to the input of the second memory cell and the first input of the switch, the second input of which is the input of the device, in order to improve speed devices, the first, second and third matching elements on the first, second and third resistors are entered into it, one pins of which are connected to the inverting input of an operational amplifier, the non-inverting input of which th is connected to zero potential bus, the other terminals of the first, second and third resistors connected respectively to the output of the first memory cell, a switch output and a second output of the memory cell, the first input of the memory cell connected to the first input ko.mmutatora.