SU1223328A1 - Digital sinusoidal oscillator - Google Patents

Abstract

The invention relates to radio engineering. The range of generated frequencies is expanded and the spectral purity of the output signal increases. The digital generator contains the supported generator 1, the phase storage 2, the 3 pulse distributor, the Permanent Memory Unit (BPZ) 4, "(} analog adder 9, low pass filter (LPF) 10 and four calculators 5,6,7,8 sinusoidal increments functions, each of which consists of register 11 of memory, subtractor 12, accumulating adder 13 and digital-to-analog converter (DAC) 14. The code K (F) of the synthesized frequency is accumulated in phase accumulator 2, then stored in BPZ 4 and in registers 1I of memory These are recorded sinusoidal value codes. Phase function. Then the difference codes generated by the subtractors 12 enter accumulative adders 13. They are cyclically transformed. The sine value increment codes generated by them are converted into 11AP 14 to analog values, which are formed in the analog adder 9 into a step sinusoidal signal. After filtering in the low-pass filter 10, a sinusoidal signal of the corresponding frequency is generated at the output of the digital oscillator. 2 nl. i W N9 tC 00 SA to 00

Description

The invention relates to radio engineering and can be used in radiolocation and in long-distance communication systems in the construction of wide-range sinusoidal oscillators with a precision waveform of the output signal.

The aim of the invention is to expand the range of generated frequencies and increase the spectral purity of the output signal.

Figure 1 shows the structural electrical circuit of a digital generator of sinusoidal signals; Fig. 2 shows diagrams explaining the principle of operation of the generator.

The proposed generator comprises a reference generator 1, a phase storage 2, a distributor 3 pulses, a constant storage unit 4, the first 5, the second 6, the third 7 and the fourth 8 calculators of the increment of the sinusoidal function, the analog adder 9, the low-pass filter 10 Each of the calculators 5 - 8 consists of register 11 of memory, subtractors 12, accumulating adder 1, and digital-analog converter (D / A) U.

Digital generator of sinusoidal signals works as follows.

In the initial state, the output code of accumulating adder 13 and register 11 is zero. With the arrival of the first clock pulse from the second output (Fig. 2g) of the distributor 3, the memory value register of the sinusoidal phase function (4 j), i.e. the sincf code that enters the input of the subtractor 12. The input of the subtractable (i.e., the number has a negative sign or comes in the additional code) receives the code of the sinusoidal phase function (Cf), i.e. sin code O,, while the difference code is generated at the output of subtractor 12

TO

eleven

 sin CP - sin cf,,

where K is the output code of the subtractor 1 2,

This code of the difference of two consecutive values of the sinusoidal function is fed to the input of the second term of the accumulating adder 13, at the input of the second term of which there is a code zero. From 12233282

the house of the first clock pulse from the fourth output of the distributor 3 to the recording input of the accumulating amount of the device 13; a code is formed at its output

K. (, 0+ (sin cf. siri H) sinCf - - sin q), Ar,

where K is the output code accumulating

common adder 13; , d g - increment of the second calculator 6,

Since sin qij sin c, (figd) on the ascending branches of the sinusoid, and Lg O (figa, E).

Then, with the arrival of the second clock pulse from the second output (Fig. 2g) of the distributor 3, the code of the value of the sinusoidal phase function (Q), i.e. sin q- code, which is input to the term of the subtractor 12, the input of the subtracted which receives the code of the value of the sinusoidal phase function (t,), i.e. sinCp code, while the difference code is generated at the output of subtractor 12

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2 This code of successive values of the sinusoidal function enters the input of the second term accumulating adder 13, the second term of which has a code C d g. With the arrival of the second clock pulse from the fourth output of the distributor 3 to the recording input of the accumulating adder 13 at its output form. code is

i Kj + CsinCf. j-sin J) ir + &g;

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Since sin Cf2 sin t | i, (FIG. 2 (h) on the falling branch of the sinusoid, lh O (fig. 2a, 6), i.e. the difference code k | d goes to accumulating adder 13 with a minus sign ( or in an additional code.) Thus, the value of the code at the output of accumulating adder 13 is now reduced by the value of dg (Fig. 2o).

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those. TO

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and K

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 K ,, - 4G

With the arrival of the last clock pulses from the second and fourth outputs of the distributor 3, respectively, to the recording inputs of the register 1 1 and the accumulating adder 13, the code value at the output of the accumulating adder 13 decreases, since the sinusoidal value of the cf is always less values of sintf, (previous point). On the ascending branch of the sinusoid, when the sin value (always greater than the sin tj value), the output value of the accumulating adder 13 increases.

Thus, the value of the code at the output of accumulating adder 13 is cyclical: on the increasing branch of the sinusoid, the value of the code increases, on the falling, branch of the sinusoid, the value of the code decreases. In order not to overflow the accumulating adder 13 with the maximum code value, the bit length of the latter is chosen equal to the bit width of the applied DAC 14, since the maximum code value is always less than the maximum code value of the synthesized signal (Fig. 2a, D). Similarly, calculators 5 - 8 work.

At the same time, phase accumulator 2 is a discharge accumulating adder, which, for example, can be built according to a well-known scheme, including an adder and a buffer register with feedback from the output ra: of the last to the corresponding input bits of one of the adder's components, the input of the second term of which receives the code K (F) (number) of the synthesized frequency, and the pulse from the output of the reference generator 1 is fed to the recording inputs of the buffer registers.

Thus, at the output of each of the accumulating adders 13 successively each time clock of the reference frequency, an increment code of the sine value is generated according to the algorithm

I N iU S (-sin i / n -L-i).

These increment codes are sent to

The digital inputs 1DAP 14 each computer 5-8, which convert x to analog values (Fig.28, a). output ШШ 14 / signals of increments of functions are received at the inputs of the tax adder 9, which forms a step at the output ;;; isusoidal signal (Fig.26).

After filtering the resulting sig0

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0

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0

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0

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A sinusoidal signal of the corresponding frequency is formed at the output of the IO filter.

Fo rm ula invention

A digital generator of sinusoidal signals containing a series-connected reference oscillator, a pulse distributor, a series-connected analog adder and a low-pass filter, characterized in that, in order to expand the range of generated frequencies and increase the spectral purity of the output signal, a phase accumulator is inserted into it. storing, the first, second, third and fourth calculators of increment of sinusoidal funkts, each of which consists of serially connected registers The memory ram whose input is the input of each of the increment calculators of the sinusoidal function, the subtractor, the accumulating adder and the digital-analog converter, the output of which is the output of each of the increment calculators of the sinusoidal function, while the clock input of the phase accumulator is connected to the output of the reference oscillator. , the outputs of the phase accumulator are connected to the corresponding address inputs of the permanent storage unit, the outputs of which are connected to the corresponding inputs of the first, second, third and its fourth calculators increments sinusoidal function, the register is clocked by input memory and the adder nakalivayu- present each increment a sine function calculators connected to respective outputs of pulse distributor ,. the output of each calculator is connected to the corresponding analog output of the analog adder; the second group of inputs of the subtractor of the first calculator of the increment of the sinusoidal function is connected to the corresponding outputs of the memory register of the fourth calculator of the increment of the sinusoidal function; memory register of the first calculator increment of the sinusoidal function.

the second group of inputs of the subtractor of the third calculator of the increment of the sinusoidal function is connected to the corresponding outputs of the memory register of the second calculator of the increment of the sinusoidal function, second J4 12J41234r2J412341234 1 2 3 4 f 2 J 12

 I and I I I I I I I I I I I I I I I I I I I I

The group of inputs of the subtractor of the fourth calculator of the increment of the sinusoidal function is connected to the corresponding outputs of the memory register of the third calculator of the increment of the sinusoidal function.

Editor A.Shishkin

FIG. 2

Compiled by V.Ruday Tehred O.Sopko

Order 1722/57 Tiral 816 Subscription

VIISHI State Committee of the USSR

for inventions and discoveries 1) 3035, Moscow :, Zh-35, Raushsk nab., d.4 / 5

Branch GShP Patent, Uzhgorod, Proektna St., 4

Proofreader M. Demchik

Claims (1)

Digital generator of sinusoidal signals, comprising a series-connected reference oscillator, the pulse distributor ¹⁰ thus connected analog adder and a low pass filter, characterized in that, in order to expand the range of generated frequencies and enhance spectrum ¹⁵ chiral purity of the output signal, the phase accumulator introduced therein , a block of permanent storage, the first, second, third and fourth calculators of the increment of the sinusoidal function, each of which consists of series-connected reg a memory cache, the input of which is the input of each of the calculators of the increment of the sinusoidal function, the subtractor, the accumulating adder and the digital-to-analog converter, the output of which is the output of each of the calculators of the increment of the sinusoidal function, while the ³⁰ clock input of the phase storage device is connected to the output of the reference generator, the outputs of the phase storage connected to the corresponding address inputs of the permanent memory block 35, the outputs of which are connected to the corresponding inputs of the first, second, t of the third and fourth calculators of the increment of the sinusoidal function, 40 inputs of the memory register and glowing adder of each of the calculators of the increment of the sinusoidal function are connected to the corresponding outputs of the pulse distributor. 45, the output of each of the calculators is connected to the corresponding analog adder, the second group of inputs of the subtractor of the first sinusoidal function increment calculator50 is connected to the corresponding outputs of the memory register of the fourth sinusoidal function increment calculator, the second group of gel subtractor inputs of the second calculator of the sinusoidal function increment calculator co $. is one with the corresponding outputs of the memory register of the first calculator of the sinusoidal function increment, s the second group of inputs of the subtractor of the third calculator of the increment of the sinusoidal function is connected to the corresponding outputs of the memory register of the second calculator of the increment of the sinusoidal function, the second group of inputs of the subtractor of the fourth calculator of the increment of the sinusoidal function is connected to the corresponding outputs of the memory register of the third calculator of the increment of the sinusoidal function.