SU1529403A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the speed and purity of the output spectrum. The synthesizer contains accumulator adder (NS) 1, converters 2.8 and 9 codes, limiter 3 with an adjustable limiting threshold, switch 4, DAC 5, low-pass filter 6 and r-r 7 reference frequency. The input code, after conversion in converters 8 and 9, as well as in series HC1 and converter 2, goes to limiter 3. In this case, a periodic parabolic function is formed in HC1 by double integration of the code. If the obtained paraboloid is limited, then the harmonic components of the paraboloids have a coefficient which depends on the limit threshold. With the limiting threshold, it is possible to vary the harmonic ratios in the output spectrum up to the complete absence of any harmonic. Determining the optimal threshold for various values of the input codes of the synthesizer for the minimum spurious spectral components in the output signal and writing it into the memory of converters 8 and 9, you can improve the x-ki of the output spectrum. In the synthesizer, the execution of the limiter 3 and HC1 can be different. 2 Cp f-crystals, 2 ill.

Description

SP

1C

with

Fig.}

The invention relates to radio engineering and can be used in communication technology dd for producing a discrete set of frequencies.

The purpose of the invention is to increase the speed and purity of the output spectrum.

FIG. Figure 1 shows the electrical block diagram of a digital frequency synthesizer; in fig. 2 is an electrical block diagram of the accumulating adder.

The digital frequency synthesizer contains a accumulating adder (NS) 1, the first converter 2 codes, limiter 3 with an adjustable limitation threshold, switch 4, a digital-analog converter (DAC) 5, a low-pass filter 6, a generator 7 of the reference frequency, the second 8 and the third 9 code converters. When limiter 3 contains a register of 10 codes, the first 11 and the second 12 code comparators, the first 13 and the second 14 JK-trig.

The accumulating adder 1 forms the first adder 15 codes, the first register 16 of memory, the block of elements EXCLUSIVE OR 17, the second adder 18 of codes, the second register of memory 19 and the element EXCLUSIVE OR 20.

Digital frequency synthesizer works as follows.

Depending on the input code, the current value of the set frequency code appears at the input of the digital frequency synthesizer at the output of NS 1. Since NS 1 is made as a serially connected adder 15, memory register 16, block EXCLUSIVE OR 17, accumulator 18 and memory register 19, and ELIMINANT lUffl 20, the code change at its output is described as

The parabolic periodic function is Y X X.

If the high bit of the output code NS 1, which is specified by the output state of the second block of EXCLUSIVE OR 20 elements, is zero, then the code from its output passes through the first code 2 converter without changing, a negative half-wave of the paraboloids is formed. If the high bit of the output NA code 1 is one, then the code is reversed and a positive half-wave is formed. As a result, the signal to

the output of the first code 2 converter is described by the function:

+

Sin SX

B

+ ...).

five

five

0

five

0

If the paraboloid is limited, then the harmonic components of the paraboloids have a coefficient depending on the limit threshold. Me-g n threshold limit, you can change the ratio of the harmonics in the spectrum of the output signal up to the complete absence of any harmonics.

The code from the output of the first converter 2 of the code enters the limiter 3 at the inputs of register 10 and comparators 11 and 12. If the value of this code is less than the code at the output of converter 9 of the code, but greater than the code at the output of converter 8, then the K-inputs of JK-flip-flops 14 and 13 is 1, and at the J-inputs it is O. According to the clock pulse coming from generator 7, this code is written to register 10. And JK-flip-flops 13 and 14 have level 1 on inverse outputs. At that, switch 4 passes the code from the output of register 10, which is converted to a DAC 5 and filter 6 to analog voltage. If the code from the output of converter 2 is greater than the code at the output of converter 9, then the J-input of the second JK - trigger 14 contains level 1, and the K-input - level O, and the inputs of the first JK-trigger 13 reverse. After the clock pulse, the second JK flip-flop 14 is set to one, and the first JK flip-flop 13 goes to zero, the switch 4 skips the code set at the output of the third converter 9 of the code. If the code from the output of the first converter 2 of the code is less than the code set at the output of the second converter 8 of the code, the output state of the JK flip-flops 13 and 14 is reversed relative to the second variant and the switch 4 skips the code set at the output of the second converter 8 code.

The formation of a periodic parabolic function in NA 1 is performed by double integration of the code at the NA 1 code input. The first integrator consists of the adder 15 and the memory register 16 and forms a ramp signal. If the (M − 1) th bit of the first memory register 16 is zero, then

the block of EXCLUSIVE OR 17 elements passes the code from the code output of the first register of the 16 memory without change; if (m -1) —and the bit is equal to one, the code is inverted. Thus, at the output of the block EXCLUSIVE OR 17, a signal with a triangular characteristic is generated, which is fed to the input of the second integrator containing the adder 18 and the memory register 19. To obtain a positive half-wave of paraboloids at the output of the EXCLUSIVE OR 20 element, a high-order signal of the NS 1 signal is generated. The EXCLUSIVE OR 20 element implements the function

F m (m-1) + m (m-.} Where X, X (dd, are signals from the M-th and

(M-1) th high-order bits of the first register of 16 memory.

Having determined the optimal threshold for various values of the input codes of the digital frequency synthesizer using the minimum parasitic spectral components in the output signal and having written it into the memory of the converters 8 and 9 of the code, one can significantly improve the performance of the output spectrum of the digital frequency synthesizer.

Claims (3)

1. A digital frequency synthesizer containing a serially connected reference oscillator, an accumulator and an initial code converter, a serially connected switch, a digital-to-analog converter and a low-pass filter, while the code input of the accumulator adder is a setting input of a digital frequency synthesizer characterized in that the purpose of improving the speed and purity of the spectrum of the output signal, introduced a second code converter, a third code converter and a limiter with p An adjustable limit threshold, the first, second, third inputs, the first and second outputs of which are respectively connected to the output of the first code converter, the output of the second code converter, the output of the third code converter, the first input of the switch and the second input of the switch, the third and fourth inputs which accordingly d 0 5 o about 0 five connected to the output of the second code converter and to the output of the third code converter, the limiter clock input with an adjustable limitation threshold is combined with the clock inputs of the switch, the digital-analog converter, the second code converter and the third code converter and connected to the output of the reference frequency generator, and the code inputs of the second and the third code converters are connected to the code input of the accumulating adder. 2. A synthesizer according to claim 1, characterized in that the limiter with an adjustable limit threshold comprises a first code comparator, a second code comparator, a first JK trigger, a second JK trigger, and a code register, the code input of which is combined with the first input of the first code comparator and The second input of the second code comparator is the first input of the limiter with an adjustable limit threshold, the second input of the first code comparator and the first input of the second code comparator are the second and third inputs of the limiter detectable threshold limit, the first and second outputs of the first code comparator are connected respectively to the J-input and K-input of the first JK-flip-flop, first 1 and second outputs of the second code comparator are connected respectively to the J-input and K-input of the second JK-flip-flop which is united The clock input of the first JK flip-flop and the clock input of the code register are the clock input of the delimiter with an adjustable limitation threshold, the first and second outputs of which are respectively the register code output and the combined outputs of the first and second JK triggers. 3. Synthesizer according to claim 1, which is based on the fact that the accumulating adder contains serially connected first code accumulator, nepBbifi memory register, block of elements EXCLUDE1 1EE OR, second adder of codes and second register of memory, as well as an EXCLUSIVE OR element , the first input of which is connected to the output of the most senior M-th digit of the first memory register, the second input of the element is EXCLUSIVE OR OR is combined with the second input of the first block of elements IS1 SHOCK OR1 connected to the output (M-1) of the first memory register, the code output of which is connected to the first input of the first code adder, the second input of which is the code input of the accumulating adder, clock inputs of the first and second memory registers are combined and are the clock input of the accumulating adder, the code output of the second memory register is connected to the second input of the second adder of codes, while the code output of the second memory register and the output of the EXCLUSIVE OR element are the code output of the accumulative ora