SU1215110A1 - Device for multiplying frequency - Google Patents

Abstract

The invention relates to devices for multiplying a frequency by a number given by the ratio of two integers in a bidet of parallel codes, and can be used in specialized automatic control devices. The aim of the invention is to expand the scope by increasing the allowable multiplication factor. The device contains a clock pulse generator. 3 controllable frequency dividers, with the frequency divider being designed as a subtractor and a digital comparator, a counter, a register, two pulse drivers, a delay element, and an OR element. A clock pulse generator generates signals with a frequency fНг. A signal from the output of a digital comparator with a frequency, - receives jM N - a counter a to the counting input (M and I - codes of multiplication coefficients, moreover). The output signal of the device is generated with the frequency ffrbix M 1 sludge.

Description

one

The invention relates to devices for multiplying a frequency by a number given by the ratio of two integers in the form of parallel codes, and can be used in specialized automatic control devices,.

The aim of the invention is to expand the scope by increasing the allowable multiplication factor.

The drawing shows the functional scheme of the device for multiplying the frequency.

The device contains 1 clock pulse generator, the first controlled frequency divider, implemented in the form of a detracting counter 2 and a digital comparator 3, the inputs of the first group of the co. Second are connected respectively to the discharge outputs of the subtractive counter 2, the output of the digital comparator 3 is connected with the enable input of the rewriting of the parallel code of the subtracting counter 2, counter 4, register 5, second and third controlled frequency dividers 6 and 7, the first driver 8 pulses, the delay element 9, the second driver 10 pulses 5 elements t OR 11 and inputs 12 and 13 for setting the first and second multipliers of the device, respectively, and the output of the clock pulse generator 1 is connected to the subtractive input of counter 2 and the information input of the second controlled frequency divider 6, the output of which is connected to the information input of the third controlled divider 7 frequencies, the control inputs of the second controlled frequency divider 6 are connected respectively to the inputs of the second group of digital comparator 3 and to the inputs 12 of setting the first smart factor of the device, and The formation inputs of the subtracting counter 2 are connected respectively to the inputs 13 of setting the second multiplier; the output of the digital comparator 3 is connected to the counting input of counter 4, the discharge outputs of which are connected respectively to the discharge inputs of the register 5, the discharge outputs of which are connected respectively to the control inputs of the third controlled frequency divider 7, the output of which is

ten

2151102

dinen with the entrance of the second shaper. 10 pulses, the device is connected to the input of the first pulse driver 8, the output of which is connected to the input of the delay element 9, the register clock input and the first input of the OR element 11, the second input of which is connected to the output of the second pulse driver 10, the output of the delay element 9 is connected to the input of the installation in About counter 4, and the output of the element OR 11 is connected to the output of the device

The device dp multiplying the frequency of 5 TY works as follows.

Preliminarily, the control inputs of the second controlled frequency divider 6 and the information inputs of the down-reading counter 2 come from inputs 12 and 13 of the multiplication factor codes AND and (H under condition.

The clock pulse generator 1 generates signals with a frequency, arriving at the subtracting input of counter 2. At the time when the codes at the inputs of the first and second groups of the digital comparator 3 are equal, a signal at the output of the counter 2 rewriting code of the parallel code of the counter 2 is generated. - the rum is recorded in the last information coefficient for the coefficient M. In addition, the signal from the output of the digital comparator 3

t

20

25

thirty

35

With frequency

; MN

enters the counting

the input of the counter 4. During the period between the two pulses generated by the first driver of the 8 pulses, a code is formed from the input frequency gx in the counter 4, equal to

(mmkbh

This code for the next input pulse enters the register 5 and further to the control inputs

The third controlled frequency divider 7 determines its division ratio. After the time determined by the delay element 9, the counter 4 is zeroed with the same pulse. The signals from the output of the clock generator 1 also arrive at the information input of the second controlled frequency divider 6, the output of which is formed by the sigal with the frequency

Insofar as

Since this signal is informational for the third controlled frequency divider 7, then a signal with the frequency

f riiNK

 i - - N

g - M bx - m

which, through the second driver 10 pulses, arrives at the first input of the element OR 11. And since its second input receives signals generated by the first driver 8 pulses from the input frequency f g, the output signal of the structure will be generated with a frequency. M

Sbix-fsx f iq ffex

Invention Formula

A device for frequency multiplication containing a clock pulse generator, the first, second and third controlled frequency dividers, a register and a counter, the output of the clock pulse generator connected to the information input of the second controlled equalizer frequency divider, the control inputs of which are connected respectively to the inputs of the first multiplication factor setting and the second code of the controlled variable frequency divider are connected to the information input of the third controlled frequency divider, the control inputs of which are s, respectively, with discharge dnymi register outputs The discharge counter outputs are respectively connected to discharge dnymi register inputs of m- lichayuschees in that, in order to expand the field of application by increasing the allowable multiplying factor, the first

five

151104

the controlled frequency divider is designed as a subtracting counter and a digital comparator, the inputs of the first group of which are connected. 5, respectively, with the bit outputs of the detracting counter, the output of the digital comparator is connected to the input of the resolution for rewriting the parallel code of the deducting counter, the input

The 0 subtracting is the information input of the first controllable frequency divider and is connected to the output of the clock pulse generator, the information inputs of the subtractive counter are the first group of control inputs of the first controllable frequency divider and are connected respectively to the input inputs of the second device clever factor , inputs second

The digital comparator groups are the second group of control inputs of the first controlled frequency divider and are connected respectively to the inputs of specifying the first device multiplication factor, in addition, the first and second pulse shapers, the element, g delay and the shsh element are entered into the device, and the input

0 the device is connected to the input of the first pulse generator, the output of which is connected to the input of the delay element, the clock input of the register and the first input of the SHS element whose output is connected to the output of the device, the output of the digital comparator of the first controlled frequency divider is connected to the counting

the input of the counter, the installation input of O which is connected to the output of the delay element, the output of the third controlled frequency divider is connected to the input of the second pulse shaper, the output of which is connected to the second input of the KTIHt element

about 5

M t

73

 n

Oj

"

 Th

Lb

Compiled by V. Gusev Editor A. Lezhnina Tekhred O. Neze

Order 907/56 Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PPP Patent, Uzhgorod, st. Project, 4

Proofreader G. Reshetnik.

Claims (3)

Claim A device for frequency multiplication, containing a clock generator, a first, second and third controlled frequency dividers, a register and a counter, and the output of the clock generator is connected to the information input of the second unit. an inventive frequency divider, the control inputs of which are connected respectively to the inputs of the task of the first multiplication coefficient of the device; and the output of the second controllable frequency divider is connected to the information input of the third controllable frequency divider, the control inputs of which are connected respectively to the bit outputs of the register, the bit outputs of the counter are connected respectively to the bit inputs of the register, which is characterized by the fact that, in order to expand the scope by increasing permissible multiplication factor, the first controllable frequency divider is made in the form of a subtracting counter and a digital comparator, the inputs of the first group of which are connected neny. 5, respectively, with the discharge outputs of the subtracting counter, the output of the digital comparator is connected to the enable input of overwriting the parallel code of the subtracting counter, the input 10 subtracting which is the information input of the first controllable frequency divider and is connected to the output of the clock generator, the information inputs of the subtracting counter are the first group of control inputs of the first controllable frequency divider and are connected respectively to the input inputs of the second device multiplier, the inputs of the second group of the digital comparator are the second group of control inputs of the first controllable frequency divider and are connected respectively to the inputs of the job of the multiplication factor of the device, in addition, the first and second pulse shapers, the delay element g * and the OR element are introduced into the device, the input 30 of the device being connected to the input of the first pulse shaper, the output of which is connected to the input of the delay element, the clock input of the register and the first the input of the OR element, the ₃₅ output of which is connected to the output of the device, the output of the digital comparator of the first controlled frequency divider is connected to the counting input of the counter, the input of which is connected to the output of the element delays, the output of the third controlled frequency divider is connected to the input of the second pulse shaper, the output of which is connected to the second input of the OR element.