SU1372591A1 - Device for controlled delay of pulsed signal - Google Patents

Abstract

The invention relates to a pulse technique. The device contains an analog shift register 4, a converter 5 and a stop 11. The introduction of the element BAN 6, the two-input pulse-width modulator 8, the driver 7, the subtraction unit 12 and the formation of new functional connections expands the range delays and improves the accuracy of the pulse delay. In the description, an example of the implementation of a two-input pulse width modulator is given. 1 hp f-ly, 4 ill.

Description

(Rig.1

The invention relates to a pulse technique and electronics and can be used to delay pulsed signals of an arbitrary shape. The aim of the invention is to expand the range of delays and improve the accuracy of the delay of the pulse signal.

FIG. 1 shows a block diagram of the device; FIG. 2 and 3 are timing diagrams explaining its operation; FIG. 4 is a block diagram of a digital pulse-width modulator.

The device contains the first 1 and second 2 inputs, output 3, analog shift register 4 (APC), the output of which is output 3 of the device, converter 5, BAN 6, shaper 7 short pulse, pulse width modulator (PWM) 8, having a start input 9 and a control input 10, a limiter 11 and a subtraction unit 12.

Input 1 of the device is connected to the input of the analog shift register 4 and through the shaper 7 short pulses connected to the start input 9 of PWM 8, the input 10 of which is connected to the second input 2 of the device and the input of the limiter 11, the output of which is connected to another input of the block 12 is subtracted and through converter 5 to the input of the BAN 6 element, the other input of which is connected to the output of PWM 8, and the output to the clock input of the analog shift register 4.

An additional third input 13 PWM B in its digital version is connected to the output of the converter 5

Digital PWM 8 contains the first 14 and second 15 counters, the outputs of which are connected to the inputs of the element BLANKING OR-HE16, the output of which is the output of PWM, input 9 of which is connected to the resolution enable inputs, input 10 - to the D input of the first counter 14, and the third input 13 is connected to the clock inputs of the counters 14 and 15.

The device works as follows.

The main input 1 of the device receives, for example, a pulse signal having a duration t,, the following frequency F

and K (integer) significant harmonics in the spectrum. At the input 2

in

0

five

0

five

0

five

0

five

A regulating signal is present in the device, for example, in the form of a constant voltage U, the level of which sets the required delay. With the help of limiter 11, the range of possible voltage variation U is limited at level U, thereby limiting the frequency range of converter 3 to condition F KF.

The purpose of the limiter 11 diminished „,. MQKC

shifts the range O ... U, j of the variation of the control voltage to O ... Uo. The need for it arises when the delay of the pulse signal requires, as shown above, the narrowing of the frequency range of the converter. The subtraction unit 12 forms the PWM control voltage. The characteristic and, node 11 corresponds to a converter having an inverse relationship F. f (Ugj,). Thus, by means of nodes 11,12, the whole range 0 ... and the variation of the control voltage are divided into two sub-bands: 0.,. and and cmox

The analog shift register, made similarly known, performs the function of a delay line. The number of memory elements in the APC, the frequency F of the converter, and the duration (t) of the pulse signal at input 1 of the APC satisfy the condition n t F. The former 7 generates a short pulse that matches with a cut (or front) of the input pulse signal.

PWM produces a wide interlocking pulse, the duration of which is proportional to the voltage at input 10.

In the interval of action of the input pulse (Fig. 2a), the element BAN 6 is open, as a result of which the input pulse is recorded in the APC. Under the action of pulses at the clock input of the APC (clock pulses), the input pulse is written to the ARS in the form of charge packets proportional to its current values. With each clock pulse, the previously recorded charge packets are rewritten into the adjacent (on the output side) APC elements, and The first is a new charge packet.

In the case when the voltage level and input 2 lies in the first sub-band, the signal (log. O) at the PWM output 8 is absent, due to

which the element BAN 6 is open and the APC clock input is fed continuously to a sequence of pulses from generator 5. Under the action of the latter, a pulse recorded in the APC is shifted to its end, after a time of 7 n / F appears at the device output.

In the case when the voltage level and 2 at the input 2 of the device lies in the second subrange, the voltage U ,, at the output of the limiter is constant, and the output voltage U. of the subtraction unit 12 is different from zero. Under the action of these voltages, the frequency of the converter is fixed (F F) and put into operation PWM 8. The latter is triggered by input 9 at the end of the input pulse. The ilMM output strobe (Fig. 4c) blocks the supply of clock pulses through AND 6. The strobe width, for example, is proportional to the voltage 11.2. At the end of the strobe, the action of the pulses (Fig. 2d) on the clock input of the ARS is resumed and the input pulse recorded in the ARS is shifted to its end. Upon the arrival of the nth clock pulse, the input pulse is recorded in n, n-1, n-2, and so on, elements of the APC. Therefore, with the arrival of (n + l) and subsequent clock pulses, a delayed pulse is formed at the output of the device (Fig. 2e). The delay time in this case is 7 (n + n) / Fg where n T F is the number of locked clock pulses.

The work of digital PWM is as follows.

On the pre-installation inputs of D-counters 13, 14, codes of numbers N are set N. The number N determines the required delay and is chosen from the condition N p. With the arrival of the Dronta input pulse short

by a pulse at the input 9, the numbers n and N are recorded in the counters, and then begin to decrease to zero in the latter under the action of clock pulses.

The output signals of the counters using the EXCLUSIVE OR-NOT element are converted into strobe pulses in the action interval (from

ten

15

20

25

thirty

35

40

45

50

recording the number n until it decreases to zero) the output signal of the counter 1A, is written to the APC and advances to the output pulse. In the interval between the output slices of the counters, the strobe from the code of the EXCLUSIVE OR NOT element is input pulse recorded in the APC (clock pulses are not received), and at the end of it the delayed pulse is read out at the APC output.

Claims (2)

1. An adjustable delay device for a pulse signal containing an analog shift register and a converter (voltage-frequency or code-frequency), whose input is connected via a limiter to the regulating input of the device, characterized in that, in order to extend the range of delays, two-input a pulse-width modulator, a BANNER element, a driver, and a subtractor; the inputs of the BAN element are connected to the outputs of the pulse-width modulator and converter — and its output is connected to the analog register input pa shift inputs of the pulse width modulator connected respectively to the output of the subtracting unit, and whose inputs are connected respectively to the input and output of the limiter and the input of the other input is connected to an analog shift register. 2. The device according to claim 1, characterized in that, in order to improve accuracy in controlling the code signal, the pulse-width modulator is digital, provided with an additional third input that is connected to the output of the converter, the pulse-width modulator contains an element EXCLUSIVE OR NOT and two counters, the outputs of which are connected to the inputs of the EXPLOSIVE element - PARTNER OR NOT, and the preset input of one of the counters, the generalized recording inputs and the generalized counting inputs of the counters are respectively the first, second and third Odes of the pulse width modulator .. 1 1/7 / Illl I I Mille I t, fPuz. 2  - u (Puz: j