SU1211751A1 - Multichannel device for determining maximum harmonic in walsh spectrum - Google Patents

Description

the house of the first trigger, and with the output of the second element AND, the first input of which is connected to the output of the fifth OR element and the second installation input of the logic multiplication unit, at the output of which overflow is connected by the second input of the second element and, the output of the overflow of cycle counters is connected to the second information input logical multiplication unit and the first input of the seventh element And, the second input of which is connected to the output of the comparator, the reset input of the device is connected to the first inputs of the third and fifth elements of W, the second input of the first The first OR element and the first input of the fourth OR element, the output of which is connected to the installation input of the cycle counter and the first input of the second OR element, the output of which is connected to the installation input of the fourth trigger, the installation input of the poll counter and the reset input of the logic multiplication unit, the seventh output element AND is connected to the input of the second pulse generator, the output of which is connected to the second input of the fifth element OR, the output of the fifth element AND is connected to the second input of the third element OR, the output of which Connected to the first installation input of the fifth trigger, the second installation input of which is connected to the output of the sixth element AND, the output of the fourth element AND connected to the input of the first pulse shaper, the output of which is connected to the second input of the second element OR, and the analysis block contains the first second and the third pulse-formers, the first and second registers, the counter, the first, and the third triggers, the first, second, third, and quarter elements OR, the first, second, third, fourth, fifth and sixth elements AND, the delay element first, second, third and fourth, reversible counters, four transducers code - voltage, four analogue quadrants, two analog adders, a comparator, a NOT element - the first and second inputs of the first OR element of the analysis unit are connected to the outputs of the first and second pulse shapers analysis and with the inputs of the recording, respectively, of the first and second registers, the information inputs of the first and second registers are connected to the information input of the counter, the counting input of which is connected to the output of the second gager of the analysis unit and with the first inputs of the fifth and sixth elements And the analysis block, the second inputs of which are connected to the output of the delay element of the analysis block, the outputs of the fifth and sixth elements And the analysis block are connected to the first inputs of the third and fourth elements of the OR block, respectively - analysis, the output of the sixth element And the analysis unit is connected to the input of the second pulse generator of the analysis unit, the first installation input of the first trigger of the analysis unit and the first input of the second element OR the analysis unit, the second input of which о is connected to the output of the third element OR of the analysis unit, with the reset input of the first register, the input of the first pulse generator of the analysis unit and the second installation input of the first trigger of the analysis unit, the direct output of which is connected to the first inputs of the first and second elements of the And block, respectively analysis, inverse, the output of the first trigger of the analysis block is connected to the first inputs of the third and fourth elements of the analysis, respectively; the output of the 1st (k 1, 2, 3, 4) element And the analysis block is connected to the counting input of the k-th reverse the counter, the information output of which is connected to the input of the k-th converter of the code-voltage, the output of which is connected to the first and second inputs of the k-th analog quad, the outputs of the first and second analog quadratures are connected respectively to the first and second the inputs of the first analog adder, the output of which is connected to the first input of the comparator of the analysis unit, the second input of which is connected to the output of the second analog adder, the first and second inputs of which are connected to the outputs of the third and fourth, respectively tax Quad, .analiza comparator block output being coupled to the third member and the sixth vhodo.m analysis unit and through the NOT element - the third input of the fifth AND element analysis unit, the third vkod Hilti element analysis unit is connected to the reset inputs of the first and second

Eversivnye counters, the output of the fourth element OR analysis block dinene with the reset inputs of the third and

the fourth reversible counter, the direct output of the third block trigger is connected to the counting input of the second trigger of the analysis block, the second inputs of the first and third elements AND the analysis block and the third pulse generator of the analysis block, the output of which is connected to the third input of the first OR element, inverse

the output of the third trigger of the analysis unit is connected to the second inputs of the second and fourth elements And the analysis unit, the output of the first element I is connected to the third inputs of the first, second, third and fourth elements And the analysis unit, the device reset input is connected to the installation inputs of the second i third trigger the analysis unit, the second inputs of the third and fourth elements, OR the analysis unit, the installation input of the counter, the direct output of the fifth trigger is connected to the control inputs of the direct count of the reversible control counters Led counting inputs are connected to each other.

With the inverse output of the fifth trigger, the output of the second pulse driver is connected to the counting input of the third trigger of the analysis unit and the input of the delay element of the analysis unit, the output of the first OR element of the analysis unit is connected to the third input of the third OR element and the second input of the fourth OR element.

2. The device according to claim 1, wherein the logical multiplication unit contains a discrete number counter, a harmonic number counter, a pulse distributor,

-.

The invention relates to the technical means of spectral analysis of signals and can be used in various systems for locating objects based on the spectral analysis of signals in the basis of Walsh functions.

the first and second elements are OR, the group of elements is AND, the group of adders modulo two, the first information input of the logic multiplication unit is connected to the information input of the discrete number counter, whose bit outputs are connected to the first inputs of the AND elements of the group, in the output of the i -th element

And the groups (1 1, 2, ..., N, where N is the dimension of the Walsh transform) are connected to the i-th output of the pulse distributor, the reset input of which is connected to the output of the first

the OR element, the first input of which is the first installation input of the logical multiplication block and connected to 1px with the installation input of the sample numbers counter, j -and and (5 + 1) -th (j 1, 2, ..., M -1) The bit outputs of which are connected respectively to the first and second inputs of the j-th modulo-2 adder, the output of which is connected to the third input of the j-th element of the I group, the output of the N.-ro discharge of the harmonic number counter is connected to the third input of the M-th element And the group, the outputs of the elements of the group are connected to the same inputs of the second element And, the output which is the information output of the logic multiplication unit, the second information input of which is connected to the information input of the harmonic number counter, the overflow output of which is the overflow output of the logic multiplication unit, the reset input of which is connected to the second input of the first OR element, the clock input of the pulse distributor is a clock input of the logical multiplication unit, the second information input of which is connected to the installation input of the digit number counter ..

The Walsh ordered transformation is calculated by the expression

I mi p.

w sixa-o

N „o

(one)

, - 0, N- 1 k- 1, N- 1 3 -1

the current number of the discrete value of the measured value;

process amplitude component number

p, 4i, (k, (2)

n logjN;

 5-6th bit of the binary P-bit representation i;

MI. ; (3)

Un-S n-S-n S kj is the j-th binary bit n-times I of the regular representation k.

The purpose of the shadow invention is to increase the speed of the device by combining in time the coding and calculation of the harmonics of the spectrum and also the determination of the maximum harmonic from the calculated ones.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a block multiplication circuit diagram; in fig. 3 is a block diagram for determining the maximum harmonic.

A device for determining the maximum harmonic of the Walsh spectrum contains (Fig. 1): information input 1 of the device, digital-analog converter (D / A converter) -2, comparator 3, device start input 4, first trigger 5, counter 6 cycles, generator 7 pulse pulses, key 8, the generator 9 counting pulses, the first element And 10, the second trigger 11, the first element OR 12, the second 13, the third 14 and the fourth 15 elements And the delay element 16, the third 17 and the fourth 18 triha gera, the counter 19 polls, fifth 5 , sixth 21 and seventh 22 elements And, the second 23 and third 24 elements STI, p second trigger 25, pulse formers 26 and 27, fourth 28 and fifth 29 OR elements, logical multiplication block 30 with first information 31, clock 32, second information 33 inputs, reset input 34, overflow output 35, first us. setting input 36, information output 37, the second installation

11751 -4

an input 38, an analysis block 39 with the first 40, second 41, third 42, fourth 43, fifth of 44 inputs and output 45; input 46 reset the device. 5 The logical multiplication block 30 contains (FIG. 2): a counter 47 discrete numbers; 48 harmonic number counter; pulse distributor 49; the first 50 and second 51 elements OR,

0 group of elements And 52 and group of adders 53 modulo two.

Block 39 of the analysis contains (Fig. 3): the first 54 and the second 55 pulse formers; first 56 and second 57 re5 gistra; counter 58; first 59, second 60 and third 61 triggers; the first 62 and second 63 elements OR; first-sixth elements And 64-69, third 70 and fourth 71 elements

0 OR, delay element 72; first to fourth reversible counters 73-76; a code-to-voltage converter 77; analog quad 78; analog adder 79; comparator 80;

5 element NOT 81; the third pulse shaper 82.

The device works as follows.

By an external reset signal received at input 46 (Fig. 1), the device switches to the initial (static) state in which the contents of counters 6 and 19 and the output voltage of the DAC 2 become zero; the output of counter 6 becomes one; trigger 5 blocks key 8; the trigger 11 blocks the element And 10; the trigger 17 blocks the element And 14; the trigger 18 is set to a position where a single signal is input to the input of the AND element 20; trigger 25 is set to position. at which the input signal 42 of the block 39 receives a single signal.

Trigger Exterior Circuit

5, 11 and 27 in FIG. 1 for simplicity, not indicated. They can be attached to the common reset bus directly or, if necessary, through the OR elements. Through the OR element 12, an external reset signal is simultaneously transmitted to the input 36 of block 30 and through the elements OR 28 and 29, respectively, to the inputs 34 and 38 of this block, in which (Fig. 2) this signal;

5 resets the counter 47 to the zero state, switches the first digit of the counter 48 to one, and the remaining bits of the counter 48 to zero.

0

five

0

five

then it is transmitted through the element OR 5 and switches the distributor 49 to the initial state, in which its first output is open.

At the same time, the external reset signal is transmitted to block 39 through its input 41. According to this signal, the block switches to the initial state, in which the contents of the register 57 and counters 73-76 become zero; the trigger signal 59 at the inputs of elements I. 64 and 65 becomes single; the output signal to the flip-flops 60 becomes zero and blocks the elements AND 68 and 69; the trigger signal 61 at the inputs of the elements 64 and 66 becomes single and thus the element 64 is released for transmitting the counting pulses to the input 40 of the block; elements 65-67 are blocked; the first bits of register 56 and counter 58 are entered in one, and the contents of the remaining bits become zero.

According to the external trigger signal received on bus 4, trigger 5 switches and unlocks key 8. The first generated impulse at the output of generator 7 and transmitted through switch 8 (prepared when the device was reset to the initial state by the output single signal of counter 6) switches the trigger 11 and 17, and for the first discharge of the counter 6, as well as the counter 47 of the block 30, is recorded 1.

The frequency of the oscillator 7 is set in accordance with the required sampling frequency of the process being measured and it is limited above by the cycle time for determining one harmonic of the spectrum (two harmonic components).

When trigger 11 is switched, element 10 is unblocked and the counting pulses of the reference oscillator 9 are transmitted to the D / A converter Z. This starts the cycle for determining the magnitude of the first (k 1, recorded in counter 48) component of the Walsh amplitude spectrum for h, 0, N - 1.

In each kth cycle, the value of k is determined according to expression (1). For this, discrete values of X are encoded; measured value and during coding

7516

X; The value ,, for the next value i is determined in accordance with the expression (2).

Encoding X; is performed in a known manner — by balancing it with stepwise varying voltage generated by a DAC 2. DAC 2 contains a code to voltage converter based on a resistive matrix and a counter that converts the sequence of counting pulses from the generator 9 to its input into a code. The frequency of the pulse generator 9 substantially exceeds the frequency of the sampling signals generated by the generator 7.

Simultaneously with the formation of a counterbalancing voltage, the counting pulses are transmitted through the input of the DO to one of the accumulating reversible counters of the block 39, in which the code of the next component W of the harmonic is formed in accordance with the expression (1). R,

Since (-1) in this expression is always +1 or -1, the definition of W is reduced to the algebraic summation of the current codes X, -, Therefore, with increasing i, the codes in the corresponding accumulating counter of block 39 are algebraically summed up in accordance with the current value, and when i N - 1, the content of said counter becomes equal to W.

In order to raise an integer nonnegative power of magnitude (-1), it is necessary to know not the value of the exponent P; , but only its multiplicity is 2, i.e. parity and odd

The multiplicity is determined by block 30 and trigger 18 as follows.

The counter 47 of block 30 (Fig. 2) accumulates a number corresponding to the number 1 + 1 of the next discrete value X-,, and the counter 4 accumulates a number corresponding to the number k of the current amplitude component of the spectrum.

The block, in accordance with expression (2), implements a logical multiplication of the individual bits of two numbers. The first number is the counter code 47. The second number is determined by pairwise modulo two every two adjacent bits of the counter code 48 in accordance with expression (3). Definition of bits g, (k) second

the numbers carry out the adders 53 according to the scheme shown in FIG. four.

Immediate. logical multiplication of the bits of the villages is carried out by the elements of AND 52. The results of multiplications are obtained by polling these elements. the signals of the distributor 49. The distributor switches the counting pulses of the generator 9 transmitted to its input through the released element 14 and the input 32 of FIG. one). The triggering of this element is triggered by the start signal of the cycle - a generator pulse 7 with a delay in the element 16 necessary to pre-record this signal in the counter 47 of block 30. The counting pulse is transmitted through the open distributor output to the connected: element 52 at this output and simultaneously switches the distributor, by which the adjacent outlet of the distributor is prepared (opened).

As the AND 52 elements are polled, at the output of the OR 51 element, there are single signals from those AND elements 52, to the inputs of which single signals are applied.

Signals from the output of the RShI element 51 are transmitted via the output 37 of the block to the digital trigger 18, which determines the evenness (oddness) of the sum of the products of Gd fg (), i.e. evenness (oddness) P; ... Number of bits

counters 47 and 48 is equal to and. Therefore, the same amount is used for the elements And 52. The number of polls of these elements counts the counter 19. With the occurrence of the m-th counting pulse when encoding the current sampling X; the output signal of the counter 19 is generated, by which the trigger 17 is switched and thereby blocking the element AND 14 BEFORE the coding of the next sample starts, 41

After encoding is complete, the X samples; by. the coincidence in the element "AND 15 single signals" - the output signal of the counter 19 and the trigger signal 11 (the conversion signal) formed by the delayed pulse in the element 26 transmitted through the OR element 23, the counter 19 and the distributor 49 in the block 30 are reset to the initial state. Shaper 26 pulses is, for example, a one-shot. The delay is necessary for the analysis of conditions.

20

2117518

neither the trigger 18 in the case that the coding is completed before the determination of P (i,

If, after n polls of elements 5 and 52, the state of trigger 18 turned out to be similar to the initial one, then this indicates that the parity of P () k has not changed with respect to P and therefore the value of X- must be summed up with the contents of the corresponding. block 39 with the same value. with which the value was summed) (i. Otherwise, the sign of summation 15 is reversed, which is achieved by switching signals at inputs 42 and 43 of block 39 to the opposite direction of algebraic summation. trigger 18 and the required reversal of reversal is performed after completing the encoding of the current value X; and polling the AND elements 52 of block 30. An analysis of the state of the trigger 18 is performed with elements AND 20 and 21, the single signal of which is confirmed a state of a trigger 25 or switches it. This trigger and controls the reversing unit 39 into account.

At the time of balancing X; the comparator 3 switches the trigger 11 to the initial state, the output signal of which blocks the transmission of counting pulses through the element I 10 I and the DAC 2 to the zero state. With the advent of the next generator 7 sampling signal, encoding the current value of X; and definition, 4, is repeated as described.

In the manner described, N values of X are determined; of the measured value and their algebraization, taking into account the value

25

thirty

35

40

45

e sum- (

Each time X- and (4ti) vc are determined by the output signal of counter 19, trigger 17 is switched and element 14 is blocked, and thus the transmission of counting pulses is blocked in block 30..

With the occurrence of the M -1th discretization signal in the cycle, the output signal of the counter 6 locks key 8, prepares And 22, and encodes X; with i N - 1, with the appearance of a signal to balance the comparator

3, at the output of AND 22, a single signal appears, which, after being converted into a pulse signal in the shaper 27, is passed through input 44 to block 39, and at the same time this signal transmitted via OR 29 to input 38 of block 30, is reset to initial state 47 Thus, block 30 is prepared to determine P; for an alternate value. The signal from shaper 27 in block 39 compares the current harmonic with the previous one. The completion of this operation is signaled by the appearance of a pulse at the output of the block 45. This pulse is transmitted through the corresponding OR elements and switches the trigger 25 and the counter 6 to the initial state, and also confirms the initial state of the counter 19 and the Zb block. After resetting the counter 6 to the initial state, the key 8 is unlocked and with the appearance of the sampling signal, the cycle of determining the current component of the amplitude spectrum begins.

Spectrum components with indices from 1 to N are determined in this way.

With the appearance of a single overflow signal at the output of counter 48 (corresponding to the N -th component of the amplitude spectrum), which is transmitted to the output 35 of block 30, the last cycle, the determination, is performed. Nth part, With the completion of coding, the Xj discretes, in the loop

Separating the N th and the amplitude spectrum component with a single signal of the And element 13 switches the trigger 5, which blocks the key 8 and thereby the subsequent operation of the entire device. Simultaneously, the signal of the driver 27 in block 39 completes the selection of the maximum harmonic of the spectrum.

Block 39 is designed to determine the maximum harmonic of the Walsh spectrum and works in the following way.

Two sets of reversible counters were used to encode the current components of the amplitude spectrum in the block. Counters 73 and 75 are for encoding the odd components, and counters 74 and 76 are for the even components of the harmonics. In counter 58, the current number is fixed.

five

five

harmonic wave, determined by a pair of components (odd and even) amplitude spectrum. Register 56 is rewritten from counter 58 number 5 of that harmonic, whose components will be encoded in the next cycle by counters 73 and 74, and register 57 rewrites the number of the harmonic whose components will be encoded

0 in the next cycle, in the first discharge of counter 58 and register 56, one is recorded, which indicates the coding of the components of the first harmonic (H 1).

5 In the initial state, the reversible counter 73 is prepared for receiving the counting pulses (transmitted through the input 40 of the block), since in this state the element

0 and 64.

As the current Kj values are coded as k 1 (the first component of the amplitude spectrum), the corresponding groups of counting pulses

5 arrive at counter 73, in which

they are algebraically summed up in accordance with the change. With the arrival at input 44 of the block of the signal for encoding the N -th disk, the network triggers trigger 61, the output signals of which block AND 64 and unlock AND 65. The others. the block elements remain in their original state. The trigger 60 divides the signal at input 44 into two. At its output, a single signal appears only when determining the even components of the amplitude spectrum. Element 82 forms a pulse from the corresponding transition of the output signal of the trigger 61 only when determining the odd components of the amplitude spectrum. This pulse is transmitted through the WL 62 element to the output 45 of the block, in which the definition of the next component of the spectrum begins.

With the arrival of the second signal at input 44 of the block, trigger 61 and trigger 60 are switched. A unit signal of trigger 60 records the unit (second harmonic number of the Walsh spectrum) in counter 58 and simultaneously prepares for deblocking the elements I 68 and 69 ,,.

five

0

The codes of the counters 73 and 74 are converted into equivalent voltages of code-voltage converters 77, which are then square in the elec

78 and are summed by adder 79. Typical voltage of adder 7 is equivalent to the harmonic value of the Walsh spectrum. The summator voltages are compared with a comparator 80. When the harmonics whose component codes are stored in counters 73 and 74, the harmonics whose component codes are stored in the second pair of meters 75 and 76, are exceeded, a single signal appears at the output of the comparator 80 and the output element is NOT 81 - a zero signal.

: With the element 72, which is necessary to establish the signal at the output during the comparator 80 after the transfer of the counting pulses to the block through its input 40, the pulse signal from the input 44 enters And 68 and 69. If there are single signals on all the inputs of one of these the elements of the mentioned pulse signal is transmitted through this: element AND in the reset circuit of the corresponding pair of reversible counters. In this way, the pair of counters in which the codes of the components of the smallest of the two selected harmonics of the Walsh spectrum are accumulated are reset to the zero state. When k 1 in counters 75 and 76, the content is zero.

When determining the components of the second harmonic (k 2), their codes accumulate in counters 75 and 76. Further, depending on the value of the signals of the comparator 80 and the element HE 81, this or that pair of counters is reset to zero state in the described manner. When a single signal is transmitted through AND 69 (pairs of counters 75 and 76), this signal also switches the trigger 59, resets the register .57 code of the harmonic number to the zero state and, with a delay in the element 55 necessary to complete the reset, is transmitted to the input register 57 for the census from counter 58 to register 57 of harmonic number p, whose components will be determined in the next cycle. Similarly, the previous harmonic is reset and the next harmonic number is recorded in register 56. The trigger 59 provides for the recording of counting pulses and the coding of the components of the current harmonic in a certain pair of reversing counts 1175112

chix If several consecutive harmonics are less than the previous ones calculated before these harmonics, their coding should be performed in the same pair of reversible counters. In this case, the impulse signal from the output of the corresponding element AND 68 or I 69 is fed to the same input.

10 flip-flops 59 and each time the same corresponding register 56 and 57 rewrite from the counter 58 a sequence of current harmonic numbers.

15 The signal from the outputs of the time delay elements 54 and 55 is transmitted through the OR element 62 to the output 45 of the block as an indication of the completion of coding the current even-numbered 20th peak of the amplitude spectrum and the selection of the largest of the two calculated harmonics.

The coding of odd components ends essentially with the appearance of

25 odd (in the order of their following) signals at the input 44 of the block (formed by the device shaper 27). These signals switch the trigger 61 to a position where

30 transmit counting pulses to counters 74 or 76 encoding the even components of the amplitude spectrum. With the above-mentioned switching of the flip-flop 61, its signal at the input of element 82 changes from one to zero and in this element im is formed. pulse is a sign that the current odd code has been completed, is a short. If necessary, element 82 may

It can be realized that the delay of the generated pulse is at the time of setting the signals in the elements 64-67.

The signal at the output of flip-flop 60 becomes single only when the

In fact, even components of the amplitude spectrum.

In this way, sequential coding of the pairs of components of the amplitude spectrum and selection of each of the two calculated harmonics of the largest is performed. With the beginning of the coding of the last even component of the amplitude spectrum at k N at the output 35 of the device block 30 and, accordingly, at the input of the And 13 element, a single signal appears. With the appearance of a single pulse at the input 44 of block 39, a sign of the error and the encoding of the last

five

0

five

the calculated harmonics of the spectrum, at the output of the element And 13 also appears a single signal. It is a sign of the selection of the largest harmonic of the Walsh spectrum. This signal switches the trigger 5 to the initial state, and the operation of the device is completed.

Repeated operation of the device is performed as described. .

The device determines the harmonics: the spectrum without the zero component, i.e. harmonics of the centered Walsh spectrum. It is possible to eliminate the zero component, for example, by switching on a capacitor at the output of the measuring transducer to which the proposed device is connected.

} CLOSE

4c

2 43

four

Fi.3

Claims (2)

1. DEVICE FOR DETERMINING THE MAXIMUM HARMONICS OF THE WALSH SPECTRA, comprising a digital-to-analog converter, a comparator, first and second triggers, a cycle counter, a cycle pulse generator, a key, a counting pulse generator, the first AND element, a logical multiplication unit, and the information input of the device is the first input of the comparator the second input of which is connected to the output of the digital-to-analog converter, the information input of which is connected to the output of the first AND element, the first input of which is connected to the direct output to the second trigger, the first installation input of which is connected to the output of the key, the enable input of which is connected to the output of the first trigger, the first installation input of which is the device start input, the output of the cycle pulse generator is connected to the information input of the key, the output of which is connected to the counting input of the cycle counter, the output the overflow of which is connected to the key inhibit input, the comparator output is connected to the second installation input of the second trigger, the direct output of which is connected to the digital-analog reset input a converter, characterized in that, in order to improve performance, 'it contains the first, second, third, fourth and fifth elements of OR,' the second, third, fourth, fifth, sixth and seventh elements of And, the delay element, third, fourth, fifth triggers, polling counter, first and second pulse shapers, analysis unit, the key output being connected to the first information input of the logical multiplication unit and to the g input of the delay element, the output of which is connected to the first installation input of the third trigger, the output of which is. of which is connected to the first input of the third AND element, the second input of which is connected to the output of the counter pulse generator, the output of the third AND element is connected to the clock input of the logical multiplication unit and to the counting input of the polling counter, the overflow output of which is connected to the second installation input of the third trigger and to the first the inputs of the fourth, fifth and sixth elements And, the second inputs of which are connected to the inverse output of the second trigger, the third inputs of the fifth and sixth elements And are connected respectively to direct and inverse the outputs of the fourth trigger, the counting input of which is connected to the information output of the logical multiplication unit, the first installation input of which is connected to the output of the first OR element, the first input of which is connected to the second installation input SU, 1211751, the house of the first trigger, and the output of the second element And, the first input which is connected to the output of the fifth OR element and to the second installation input of the logical multiplication unit, the overflow output of which is connected to the second input of the second AND element, the output of overflow of the cycle counters connected to the second information input of the logical multiplication unit and the first input of the seventh AND element, the second input of which is connected to the output of the comparator, the device reset input is connected to the first inputs of the third and fifth OR elements, the second input of the first OR element and the first input of the fourth OR element, the output of which is connected to the installation input of the cycle counter and to the first input of the second OR element, the output of which is connected to the installation input of the fourth trigger, with the installation input of the polling counter and reset input CA of the logical multiplication unit, the output of the seventh element AND is connected to the input of the second pulse generator, the output of which is connected to the second input of the fifth OR element, the output of the fifth element AND is connected to the Second input of the third OR element, the output of which is connected to the first installation input of the fifth trigger, the second installation the input of which is connected to the output of the sixth element And, the output of the fourth element And is connected to the input of the first driver im-g pulse, the output of which is connected to the second input of the second element OR, Liza contains the first, second and third pulse shapers, first and second registers, counter, first, second and third triggers, first, second, third and fourth elements OR, first, second, third, fourth, fifth and sixth elements of Y, delay element, first, second, third and fourth. reversible counters, four code-voltage converters, four analog quadrators, two analog adders, a comparator, a NOT element, and the first and second inputs of the first OR element of the analysis unit are connected to the outputs of the first and second pulse shapers of the analysis unit and to the recording inputs, respectively, of the first of the second and second registers, the information inputs of the first and second registers are connected to the information input of the counter, the counting input of which is connected to the output of the second trigger of the analysis unit and with the first the inputs of the fifth and sixth elements AND of the analysis block, the second inputs of which are connected to the output of the delay element of the analysis block, the outputs of the fifth and sixth elements of the And analysis block are connected * with the first inputs of the third and fourth elements of the OR analysis block, the output of the sixth element AND block the analysis is connected to the input of the second pulse former of the analysis unit, the first installation input of the first trigger of the analysis unit and the first input of the second element OR analysis unit, the second input of which is connected to the output of the third element nt OR analysis unit, with the input of the first register reset, the input of the first pulse shaper of the analysis unit and with the second installation input of the first trigger of the analysis unit, the direct output of which is connected to the first inputs of the first and second elements AND of the analysis unit, inverse, the output of the first trigger of the analysis unit connected to the first inputs of the third and fourth elements AND of the analysis unit, respectively, the output of the k-th (k = 1, 2-, 3, 4) element of the AND of the analysis unit is connected to the counting input of the k-th reverse counter, the information output where the code-voltage converter is connected to the input of the k-th converter, the output of which is connected to the first and second inputs of the k-th analog quadrator, the outputs of the first and second analog quadrators are connected respectively to the first and second inputs of the first analog adder, the output of which is connected to the first input of the comparator of the analysis unit, the second input of which is connected to the output of the second analog adder, the first and second inputs of which are connected to the outputs of the third and fourth analog quadrators, respectively, the output of the computer The analysis unit is connected to the third input of the sixth element AND of the analysis unit and through the element NOT to the third input of the fifth element AND of the analysis unit, the output of the third element OR of the analysis unit is connected to the reset inputs of the first and second ‘1211751. reversible counters, the output of the fourth element OR of the analysis unit is connected to the reset inputs of the third and fourth reversible counters, the direct output of the third trigger of the analysis unit is connected to the counting input of the second trigger of the analysis unit, the second inputs of the first and third elements AND of the analysis unit and the input of the third pulse generator of the block analysis, the output of which is connected to the third input of the first element OR of the analysis unit, the inverse output of the third trigger of the analysis unit is connected to the second inputs of the second and fourth element comrade AND analysis block, the output of the first element AND is connected to the third inputs of the first, second, third and fourth elements of the Analysis block, the reset input of the device is connected to the installation inputs of the second and third triggers of the analysis block, the second inputs of the third and fourth elements, OR block analysis, installation input of the counter, the direct output of the fifth trigger is connected to the control inputs of the direct counting of reversible counters, the control inputs of the counting of which are connected to the inverse output of the fifth trigger, the output is second pulse shaper is connected to the counting input of the third flip-flop and the input of the analysis block analysis unit delay element, an output of first OR analysis unit connected to the third input of the third OR gate and the second input of the fourth OR gate. 2. The device according to claim 1, wherein the logical multiplication unit comprises a discrete number counter, a harmonic number counter, a pulse distributor, the first and second OR elements, a group of AND elements, a group of adders modulo two, the first information input of the logical multiplication unit is connected to the information input of the discrete number counter, the bit-wise outputs of which are connected to the first inputs of the AND elements of the group, the output of the ΐth element AND groups is good (х - 1, 2, ..., N, where N is the dimension of the Walsh transform) connected to ϊ -m in the output of the pulse distributor, the reset input of which is connected to the output of the first 'OR element, the first input of which is the first installation input of the logical multiplication unit and is connected to the installation input of the counter of discrete numbers, jth and (j + Dth (j = 1, 2, M -1) the bit-wise outputs of which are connected respectively to the first and second inputs of the jth adder modulo two groups, the output of which is connected to the third input of the [th element of the And group, the output of the N '.th discharge of the harmonic number counter is connected to the third input of the Mth element AND group, the output elements And groups are connected to the inputs of the same name of the second element And, the output of which is the information output of the logical multiplication block, the second information input of which is connected to the information input of the counter of harmonic numbers, the overflow output of which is the overflow output of the logical multiplication block, the reset input of which is connected to the second input of the first element OR,. the clock input of the pulse distributor is the clock input of the logical multiplication unit, the second information input of which is connected to the installation input of the discrete number counter.