SU1203537A1 - Walsh spectrum analyzer - Google Patents

Description

The invention relates to automation and computing and can be used in digital filtering devices, communication systems, as well as in other devices where it is necessary to obtain the spectral composition of the signals used.

The aim of the invention is to simplify the scheme.

The drawing shows the functional scheme of the spectrum analyzer.

The analyzer contains a generator of 1 pulses, a block of 2 frequency dividers, a counter 3, an analog-digital converter 4, a Walsh function generator 5, an accumulating adder 6, a ring shift register 7, an adder-subtractor 8, switches 9-13 , a group of shift registers 14 and a result registration block 15.

Spectrum analyzer works as follows.

The calculation of the decomposition coefficients of the analyzed signal over the set of orthonormal Walsh functions is performed in accordance with the expression. , 2 (p-)

With W (i) -I, (1)

where Cj, is the Kth decomposition coefficient i, the calculation step,, 2,.,.,

2 (p-1); n - the highest order of function

Walsh, W) (i) - the value of the K-th Walsh function

i-M step,

 - i is the sum of the samples of the analyzed signal, calculated on a time interval equal to the step duration. The duration of the 5th step is taken equal to the minimum period of time at which the Uz does not change its

th value

Yes.

those. half of it is calculated according to the formula

2SL-OTO J OTj,

(2)

where T is the decomposition period, T

2 (p-1)

duration maraj

Td is the sampling period vp I - j - the sample of the analyzed signal (j is measured independently at each step).

The generator 1 generates pulses with a frequency f 1 / Tg. The analog input signal, converted into a 1-dish form, with a frequency f is fed to the input of accumulating adder 6, in which the value I, is calculated according to formula (2). At the beginning of each i-ro step, the generated value C is transmitted by a parallel code to the ring shift register 7 by the signal from the output of the block 2 frequency dividers. In this case, the adder 6 is zeroed, and in it begins

form value i

1-I

Value

I- is stored in sequential code in register 7 at a shift frequency f. The values of the indices K (the numbers of the Walsh functions and the corresponding coefficients: s) and i are counted by the groups of lower and higher bits of counter 3, respectively. The index K determines the state of the switches 9-12 and the number of the output of the generator 5 Walsh functions connected to the Control input of the adder-subtractor 8. ) together with the adder-subtractor 8 (via switches 13, 11 and 10). Registers 14 store intermediate coefficient values. Clock pulses from generator 1 through switch 12 are received by a packet at the shift synchronization input of register 14 with number K. The number of pulses in a packet corresponds to the size of the shift registers and determines the frequency division factor in block 2.

At the additional calculation step, which corresponds to a certain state of the group of higher bits of the counter 3, the switch 13 switches to the input of the result recording unit 15.

Compiled by V. Baikov

g

Editor O. Yurkovetska Tehred L. Mikesh

8419/53 Circulation, 709Subscription

VNIIGSh of the USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch ShSh Patent, Uzhgorod, Proektna St., 4

Proof-reader I.Erdeyi

Claims (1)

A WALSH FUNCTION SPECTRUM ANALYZER containing a pulse generator, an analog-to-digital converter, a counter, a ring shift register, an adder - a subtractor and a result recording unit, the input of an analog-to-digital converter being an information input of a spectrum analyzer, the output of a shift shift register connected to the first information input the adder-subtractor, the output of the pulse generator is connected to the synchronizing inputs of the annular shift register and the adder-subtracter, characterized in that, in order to simplify In this scheme, it contains a Walsh function generator, accumulating an adder, a group of shift registers, five switches and a frequency divider block, the output of an analog-to-digital converter connected to the information input of the accumulating adder, the output of which is connected to the information input of the ring shift register, the outputs of the group of lower digits the counter is connected to the control inputs of the first, second, third and fourth switches, the outputs of the high-order bits of the counter are connected to the control inputs of the fifth comm the output of the Walsh function generator, the outputs of the Walsh function generator through the first switch are connected to the control input of the adder-subtractor, the output of which is connected to the information input of the fifth switch, the first output of the fifth switch is connected to the input of the registration unit. of the result, the second output through the second switch is to the information inputs of the group shift registers, the outputs of which through the third switch are connected to the second information input of the adder-subtractor, the output of the pulse generator is connected to the input of the frequency divider block, which synchronizes the input of the accumulating adder, and through the fourth switch to the synchronization inputs group shift registers. N9 O 00 SP 00 <1