SU1529217A1 - Random signal generator - Google Patents

Abstract

The invention relates to computing and can be used to generate vector random symbols described by a multidimensional distribution law. The purpose of the invention is to expand the functionality by obtaining at the output a random number generator with a multidimensional distribution law. The random signal generator contains a normal noise generator 1, a quad 2, a sampling and storage unit 3, a clock 4, a shift register 9. Entering a group of accumulating adders 5, a group of elements OR 6, a group of dividers 7, allows you to get a random signal described by a multidimensional distribution Dirichlet 1 il.

Description

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The invention relates to the field of computing and can be used to generate random vector signals described by the multidimensional distribution law that simulate multi-channel communication telemetry equipment with frequency separation channels.

The aim of the invention is to extend the functionality by obtaining random signals at the output with correlated readings that are subject to a multidimensional distribution.

The drawing shows the structural scheme of the proposed generator.

The generator consists of the generator 1 of normal noise, the output of which is connected to the input of the quadrant 2, and the output of the latter is connected to the information input of the sample and storage unit 3. The clock input unit 3 sampling and storage is connected to the output of the generator 4 clock pulses. The output of block 3 of sampling and storage is connected to the first inputs of accumulating adders 5. The inputs of the summation A and C of accumulating adders 5 are connected to the outputs of the corresponding elements OR 6. The outputs of accumulating adders 5 are connected to the inputs of the Divisible corresponding dividers 7 and to the corresponding inputs of the accumulating adder 8. (/ (+ 1) th input of accumulating adder 8 is connected to the output of sampling and storage unit 3. (/ (+ 2)) and input of accumulating adder 8 is connected to output of the OR element. Inputs "Engine divider 7 wiring The outputs are to the output of accumulating adder 8. The zeroing inputs of accumulating adders 5, the {/ (- 4-3) th input of accumulating adder 8 are connected to the 20 (K +) shift register output 9. The inputs of the first element OR 6 are connected to the bit outputs from number 1 to 20 of the shift register 9 through the first switch 10. The inputs of the first element of the OR 6 (, ..., / (4-1) are connected to the bit outputs of the shift register with the number 20 ("-) + 1 to 20" through, ".-and switch 10. The input shift register 9 shift is connected to the output of the generator 4 clock pulses.

The device works as follows.

The normal noise generator 1 generates a random signal, subject to the normal distribution law. This signal enters square 2 and is squared, and then arrives at the information input of sample and storage block 3. At the clock input of the sampling and storage unit, short pulses are received from the 4 clock pulse generator. Sampling and storage unit 3 forms at its output samples of the normal square R, squared. These counts are fed to the information inputs / from accumulating adders 5. In the first accumulating adder 5, the counts are summed up, starting from H9 measure to the number. The beginning and end of the summation are determined by the switch 10 and the element OR 6, from the output of which to the enabling input of the accumulating adder a pulse arrives. The operation of the first element OR 6 controls the shift register 9, to the shift input of which pulses are received from the generator of 4 clock pulses. After the end of the pulse in the first element OR 6 in the first accumulating adder 5, the accumulated value is

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i.Y AND IT stops the summation. After that, the accumulation of samples from the sampling and storage unit 3 is similar to that of the other accumulating adders 5 successively one after the other. The sums 20 accumulated in all adders 5 are transferred to the total accumulating adder 8, as a result of which it has the accumulated value:

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25.J, (../ In addition, after the accumulation of values by accumulating adders 5, the accumulation of the sum 2,.

The samples of this amount are fed to the accumulating adder 8 from the output of the block 3 for sampling and storage and are regulated (/ (+ 1) -th element OR 6.

35 After this, the value accumulated by the adder 8 is fed to the inputs of Divider 7. Dividers of these dividers are connected to the corresponding outputs of adders 5. The division results by .Q are given to the information outputs of the generator and are random signals that follow the Dirichlet distribution .

The cycle of the generator is completed by the appearance of a pulse at the output of the older

45 bit yes register 9 shift. This pulse is applied to the zero inputs of all adders 5 and (/ (+ 3) -th input of adder 8 and zeroed them. The same pulse starts the generator for a new cycle of operation.

The proposed generator generates a random signal described by the multidimensional Dirichlet distribution, so the readings are correlated.

Claims (1)

Invention Formula  Random signal generator, containing a normal noise generator, quad, sample and hold unit, generator clock pulses, ring shift register, divider, two accumulating adders, Java switch, two OR elements, and the output of the normal noise generator is connected to the quad input, the output of which is connected to the information input of the sampling and storage unit, the clock input of which is connected to the generator output clock pulses and with the shift input of the ring shift register, the higher bit output of which is connected to the zeroing inputs of accumulating adders, whose information inputs are connected to the output of the and storage, the first group of bit outputs of the shift register is connected through the first switch to the group of inputs of the first OR element, the output of which is connected to the summing resolution input of the first accumulating adder, the output of which is connected to the input of the divisible divider, the second group of bit outputs of the regular shift register connected via a second switch with a group of inputs of the second OR element, the output of which is connected to the input of the summation resolution of the second accumulating adder, the output of which is connected to the input "D A splitter divider, the output of which is an information output of a generator, characterized in that, in order to expand its functionality by forming a multidimensional distribution law, a group of accumulating adders, a group of switches, a group of dividers and a group of OR elements are entered into it, and the group of inputs of each element of OR group is connected through the corresponding switch with the corresponding group of bit outputs of the ring shift register, the outputs of the elements OR of the group are connected to the resolution inputs of the summation of accumulating adders of the group, whose information inputs connected to the output of the sampling and storage unit; the outputs of the accumulating adders of the group are connected to the inputs of the Divisible Group Dividers and the group of information inputs of the last accumulating adder of the group whose output is connected to the inputs of the Group Divider Dividers whose outputs are the group of information outputs of the generator, the zero-in inputs the accumulating adders of the group are connected to the output of the higher bit of the shift register.