SU1196953A1 - Parallel asynchronous register - Google Patents

Description

The invention relates to computing and can be used to build digital computers. '

The purpose of the invention is to increase the speed of the register.

The drawing shows the scheme of the register. '

The register contains memory I-3 cells, each of which consists of the first 4 and second 5 AND-OR-NOT elements and the OR-NOT 6 element, control trigger 7, consisting of the AND-OR-NO element 8 and the HE element 9, the first Yu and second II elements are NOT, control input .12, information inputs 13-15 and control output 16. The information outputs of the register are the outputs of elements 4 and 5 of each memory cell.

The register works as follows,.

In the initial state, the control input of the register 12 is given a signal corresponding to the logic level "1". In this case, the signal at the outputs of the elements NOT 10, OR-NOT 6, AND-OR-NOT 8 correspond to the level of logical "0", and the signal on the inputs of the AND-OR-NOT elements 4 and 5, NOT 9 and 11 - to the level of logical "G ". This state of the register is transit. Then, the information inputs of 13–15 memory cells receive single-phase signals of the input number and the control input 12, the signal of the logical “0”.

At the same time, if a single-phase signal at the information input of one of the memory cells corresponds to the logic level “1”, then at the output of the E-ALINE 4 element the logical level “0” is set only when the output element NO 10 of the logical level “G ′ ¹ ” appears. If a single-phase signal at the information input of one of the memory cells corresponds to the logic level "0", then the output of the OR-NOT 6 element and the output of the NOT 10 element sets the logical level "1", then the output of the AND-OR-HE element 5 the logical level is set to "0" After installation in all the memory cells of the element 96953 .2

Comrades AND-OR-NOT 5 and 4 in opposite states (x; - x;) and the level of logical "0" at the output of the element NOT 11, the signal of the logical "1" is set at the output of the element AND-OR-NOT 8, but at the output of the element NOT 9 - a logical signal "0", which indicates the end of the transient processes when writing code to the register and ·

Setting the paraphase information code at the corresponding outputs of the register memory cells.

Register transfer to the transit state is as follows

15 way.

At the control input 12 signal level} logical "1". At the same time, if the unit code is written in one of the memory cells, i.e.

20 x; ~ 1 · x ί = 0, then at the output of the AND-OR-NO element 4 of this cell, the logical level "элемента" is set

(x; = 1), only after setting the level of the logical "0" at the output of the element NOT 10. Setting the level

logical "1" at the output of the element AND-ILY-NOT 4 in this case indicates the transfer of the memory cell in a transit state.

₃₀ If the zero code is written in one of the memory cells, the output signals of the elements OR NOT 6, AND-OR-NOT 5 are reversed.

Thus, the installation of logical levels "1’ ’at all exits of memory cells indicates its transit state.

After the installation of the NOT 11 logical level “1” at the output of the AND-OR-NO 8 element, the logic level “0” is set, and the output of the HE element 9 - the logical level “1”, which indicates the end of the transients and setting the trailing state

40

45

x = x ^ = 1) at the outputs of each

50

(

memory cells. Thus, when managing the process of recording information in a register and resetting it with a signal at control output 16, the influence of the spread of logic elements on the operation of the register is eliminated.

one

1196953

Claims (1)

PARALLEL ASYNCHRONOUS REGISTER containing the first element NOT, memory cells, each of which consists of the first AND-OR-NOT element, the first input of the first group of which is the information input of the register, and the first input of the second group is connected to the output of the element NO, the input of which is controlling register input, and a control trigger consisting of ele. NOT and an element AND-OR-NOT, the output of which is connected to the input of the element NOT a control trigger, the output of which is connected to the first inputs η + of the 1st group of the element AND-OR-NOT a control trigger, where η is the number of register bits, and is the manager of the register output of the l. I have the fact that, in order to increase the speed of the register, the second element NOT is entered into it, whose input is connected to the output of the first element NOT, and the output to the second input η + 1 and the first input η + 2 of the groups of the I- element OR NOT control trigger, in each memory cell entered the second element AND-OR-NOT, 'the output of which is connected to the second inputs of the first and second groups of the first element AND-OR-NOT of this memory cell, the output of which is connected to the first inputs of the first and second groups of the second element AND-OR-NOT, and the element OR-NOT, the output of which is connected to the second input the house of the first group of the second element is AND; OR — NO; the first input is connected to the input of the first element NOT; the second input is to the first input of the first group of the first AND-OR-NOT element of this cell, the third input of the second group of which is the third input of the element OR NOT and the second input of the second group of the second element AND-OR-NOT of the given memory cell is connected to the input of the NOT element of the control trigger, the outputs of the first and second elements of the AND-OR-NOT of the ΐth memory cell (Ιίΐίη) are connected to the second and third inputs- group and with inputs of the η + 2nd control trigger group, output of the first element is coupled to the third inputs of the first group of first and second group of second AND-OR-NO element of each memory cell. 5 and „„ 1196953 ¹ 11