SU1188754A1 - Device for constructing histograms - Google Patents

Abstract

A DEVICE FOR CONSTRUCTING HISTOGRAMS containing a group of registers, a group of N comparison blocks, a group of (N) elements AND, a group of (L4-1) counters, a number receiving register, the first counter, the input of the number receiving register is an information input of the device, the output of the i-th register of the group (g 1, L) is connected to the first input of the g-th group comparison unit, the output of "Not more than which is connected to the first input of the g-th element of the AND group, the output of which is connected to the counting input of the g-th counter of the group , characterized in that, in order to expand the function Opportunities by calculating the distribution function and performing the histogram level skimming operation, a group of N elements OR, AND elements, multiplexers, decoder, OR elements, triggers, second counter, delay element, controlled delay element, divider, register output are entered into it. receiving a number through a delay element connected to the first information input of the first multiplexer, the second information input of which is combined with the information inputs of the registers of the group and connected to the output of the register receive numbers, the second inputs of the group comparison units are combined and connected to the output of the first multiplexer, the control input of which is combined with the first input of the first element AND, the control input of the second multiplexer and connected to the inverse output of the first trigger, the output of the first element I is connected to the counting input of the first the counter and the information input of the second multiplexer, the clock input of which is connected to the output of the second element AND connected to the input of the divider, the first inputs of the elements OR of the group are combined and soy dinene with the output of the first element OR, the output of the “More than gth group comparison unit is connected to the second input of the gth element OR group, the output of which is connected to the second input of (g + 1) -th element AND group, the second input of the first AND element combined with the third inputs of the remaining elements of the AND group and the first (N 1) -th element (L AND group and connected to the output of the second multiplexer, the input of setting the zero of the g-th group counter connected to the g-th output of the decoder, L-th output which is connected to the installation output to zero (L + 1) -th group counter, ne the first input of the second OR element, the output of which is connected to the installation input to zero of the second trigger, the installation input to the unit of which is combined with the installation input at 00 zero of the first trigger and connected to the output of the third OR element, the first input of which is connected to the first The inputs of the fourth and fifth OR elements are the first input of the Device Mode Setting, the installation input into the unit of the first trigger is combined with the second inputs of the second, fourth and fifth OR elements and is the second input of the The device mode, the installation input into the unit of the third trigger is combined with the second input of the third element OR and the third input of the fourth element OR, and is the third input of the device mode setting, the output of the first element OR is connected to the input of the installation of the third trigger zero, connected to the first input of the first element OR, the second input of which

Description

connected to the information input of the controlled delay element and connected to the forward output of the first trigger, the output of the controlled delay element connected to the first input of the second And element, the second input of which is combined with the first input of the third And element and the second input of the first And element and the clock input of the device, the output of the fourth element OR is connected to the reset input of the controlled delay element and the reset input of the second counter, the output of which is connected to the input of the decoder, the counting input of the second counter is connected to the output of the sixth And element, the second input of which is connected to the forward output of the second trigger, the inverse input of which is connected to the third input of the first And element, the second input of the sixth element OR is connected to the output of the divider, the recording input of the ith group register is connected to the Jth output the decoder, the outputs of the count, the taps of the group and the first counter are the output of the device.

The invention approaches computational and measurement techniques and can be used to process one-dimensional and two-dimensional digital signals, including voice and video signals. The purpose of the invention is to expand the functionality of the device by providing a calculation of the frequency distribution function and performing a sliding alignment of the histogram of digital signals. The frequency distribution function of the appearance of individual digital signal values, which is a discrete analogue of the probability distribution function of signal values, is one of the most important statistical characteristics of signals. The frequency distribution function is usually calculated from the histogram H of the digital signal in accordance with the formula a, where L is the number of histogram formations; Xmm is the minimum value of a digital signal; X is the upper limit of the analyzed interval for changing the values of a digital signal. In order to speed up the calculation, expression (1) is rewritten as y, (x ,.) rO, where f (l: y) x "(e 1, N) are the upper limits of the analyzed intervals of changes in the values of the digital signal X, is the current value of the digital signal signal. Such a representation allows parallel calculation of the frequency distribution functions ye, without preliminarily forming a histogram of a digital signal. A glide alignment of the histogram of the distribution of digital signal values is that each X value of a digital signal is transformed according to a histogram H constructed over a certain neighborhood of its L elements in accordance with formula (1). In a slidable transformation, each next neighborhood is shifted from the previous one by one element in the case of a simultaneous digital signal (LN) and by a row of M elements in the case of a two-dimensional digital signal (L M XN), therefore each element of the digital signal contributes to the N histogram histograms and the process of moving histogram alignment is parallelized into N independent parts. In the case of a one-dimensional digital signal, the sum of | Zn, .-. Is calculated in parallel. L), where 4 (/ 1, L) are the central elements of N neighboring neighborhoods. In the case of a two-dimensional digital signal, the sums of m: n1 (- - + - .. /) are calculated in parallel: f, (/ 1, / V) are the central elements of the N neighboring neighborhoods. In both cases, the elements of the digital signal are delayed by i counts until the central element of the neighborhood arrives with which to compare. The histogram sliding alignment operation allows nonlinear filtering of the low frequencies of a digital signal to be implemented, which automatically corrects the signal values to the full range of its change and ensures that the result does not fall into one of the extreme areas of its change. This operation has the greatest advantages for digital signals in which it is necessary to detect information that is in the region of a strong nonlinearity of any information transmission channel. The histogram grading algorithm works much faster than the filtering algorithms in the frequency domain and is free from many of the shortcomings inherent in the latter. FIG. 1 shows the structural scheme of the proposed device; in fig. 2 shows the sequence of inputting the elements of a two-dimensional digital signal when performing one-step sliding histogram alignment. The device consists of registering the reception of the number 1, the first delay element 2, a group of N registers 3, a multiplexer 4, a group of N blocks of comparison 5, a group of N elements OR 6, a group of (N + 1) elements AND 7, a group of { N + 1) counters 8, counter 9, information input 10 of the device, clock input AND, input calculating the function of the input device, setting the modes 12, 13 and 14 of the device, elements 15, 16 and 17 OR, triggers 18 and 19, elements OR 20 and 21, trigger 22, controllable delay element 23, AND elements 24, 25 and 26, divider 27, OR element 28, counter 29, decrypt oracle 30, multiplexer 31. The device operates as follows. The histogram formation operation is initiated by the arrival of the histogram formation signal at input 14, which, through the first element OR 15, transfers the first trigger 18 to the “O” state, and also through the third element OR 17, zeroes the counter 29 and the controlled delay element 23 and through the second the OR 16 element translates the second trigger 18 to the state “O at the direct output, and the third trigger 22 — to the state“ 1 at the direct output. The signal "O from the output of the fourth element OR 20 permits the passage of signals from the first outputs of the comparison blocks of group 5 through the group of elements OR 6 to the corresponding inputs of the group of elements AND 7. The signal" 1 from the inverse output of the second trigger 19 switches the outputs of the register of reception 1 through the first multiplexer 4 to the first inputs N of the comparison unit of group 5 and the output of the first element AND 24 through the second multiplexer 31 to the control inputs of the Zlemedt group AND 7, and also allows the signals to pass through the first element AND 24. The signal "1 on the forward" the output of the third trigger 22 allows the arrival of clock signals from input 11 through the second element AND 25 and the sixth element OR 28 to the input resolution of the counter 29. The signal "O at the inverse output of the third trigger 22 blocks the arrival of clock signals from input 11 through the first element And 24 on the counting the inputs of counter 9, as well as through the second multiplexer 31, to the control inputs of the group of elements And 7. Let the first information input 10 receive a monotonically increasing sequence of values of the boundaries of histogram intervals ai, a, z, ..., a, -, ... , an. The arrival (-th clock signal at the resolution enable input 29 (i 1, L) is determined by the appearance of a signal at (-th output of the decryptor 30, which allows to write the value of / -and the interval boundary a; in the i-th register 3 groups and set to state "About the gth counter of group 8. Counter 9 and (N + 1) -th counter of group 8, as well as the N-th counter of group 8, are zeroed by the signal at the N-OM output of the decryptor 30, when it appears the fifth element OR 21, the third trigger 22 is transferred to the state "O at the direct output and thereby blocks the passage of the clock signal from the input 11 through the second element AND 25 to the sixth element OR 28 and further to the enable input of the counter 29. The signal "1 from the inverse output of the third trigger 22 allows the passage of clock signals from the second information input 11 through the first element AND 24 to the counting input of the counter 9, as well as through the second multiplexer 31 to the control inputs of the group of elements And 7. Let the first information input 10 successively receive three numbers x, x2, xs, respectively belonging to the following intervals of the number axis: -oo, a, + oo. Upon receipt of the first number xi, which from the reception register of the number 1 through multiplexer 4 is fed to the first inputs of N blocks of group 5 comparison due to the condition - (xi OS) from the second output of the first block of group 5, the resolution potential is fed to the input of the first element of the group of elements And 7. The clock signal applied to the input 11, passes to the counting input of the counter 9 and through the open element of the group of elements And 7 - to the counting input of the first counter of the 8 group, increasing by one the contents of these counters. Upon receipt of the second number X2 due to the fulfillment of the conditions (a, l: 2 a, + 1, g 1, jV-1) from the output center of the i-ro comparison block of group 5, the resolving potential is supplied through the gth element of the open group of elements OR 6 to the second information input of the (i - {- 1) -th element of the group of elements 7, the second output of the (i + 1) -th comparison block of group 5, the resolving potential is fed to the first information input of the (j + 1) -th element of the group of elements 7 .

The clock signal applied to the input 11 passes to the counting input of the counter 9 and through the open element of the group of elements I 7 to the counting input of the (d-f 1) -th counter of the 8th group, increasing by one the contents of these counters. When the third number xs is received due to the condition (al xs) from the first input of the N-ro block of group 5, the resolving potential is fed through the Nth element of the open group of elements OR 6 to the information input of the (N-4-1) -th element of the group of elements And 7. The clock signal applied to the input 11, passes to the counting input of the counter 9 and through the open (N-f-1) -th element of the group of elements And 7 pa the counting input (N 4-1) -th counter of the 8 group, increasing per unit the contents of these counters.

Thus, upon arrival of any next random number, the content of the counter 9 and the contents of the counter 8 of the group corresponding to the interval are increased by one unit. This is how the histogram of random numbers is generated. When forming a histogram of random processes, the values of the measured value in a digital form are fed to the information input 10, and the input 11 is fed to the clock signals at the points required for retrieving information.

The operation of calculating the distribution functions of the frequency of occurrences of the digital signal is initiated by applying the distribution calculation signal to input 12, which translates the first trigger 18 into the state "1 at the output, as well as through the third element OR 17, zeroing the counter 29 and the controlled delay element 23 and through the second element OR 16 transfers the second trigger 19 to the state “O at the direct output and the third trigger 22 — to the state“ 1 at the direct output. The operation of the device in this case is similar to the operation of the device during the operation of forming a histogram, except that the signal 1 from the output of the first trigger 18 through the fourth element OR 20 blocks the passage of signals from the first outputs of the comparison blocks. 5 groups through the group of elements OR 6 to the corresponding information inputs of the group of elements AND 7.

Let the input 10 receive a monotonically increasing sequence of values of the upper bounds of the intervals of variation of the values of the digital signal x, x, ..., x, ..., x. As well as when loading the values of the boundaries of the histogram intervals ai, az, ..., (Zi, ..., aN B of operation, the formation of the histogram on the zth clock signal (g 1, N) from input 11 loads the value of B t th register of shaft boundaries 3, as well as zeroing the i-ro of group 8 counter. By the N-th clock signal (N-f -} - 1) -th group counter 8 and counter 9 are also zeroed.

Let, upon completion of loading the values of x (r 1, L), in registers of the 3rd group, two numbers Xi, X2, respectively, belong to the registers of the group 10, respectively, belonging to the intervals of change of the digital signal values: Xy, x ",: n. x where Upon receipt of the first number Xb from the reception register of the number 1 through the first multiplexer 4 is fed to the first inputs of N blocks of comparison of group 5, due to the fulfillment of conditions (xi x, t 1, N) from the second outputs of all blocks of comparison of group 5, the potential potential is applied to the corresponding the inputs of a group of elements And 7. The clock signal applied to input 11 passes to the counting inputs of group 8 counters and the counting input of counter 9, increasing by one the contents of these counters. When the second number xj is received due to the fulfillment of conditions (X2 x, i €, L /) from the second outputs i-x of the comparison units 5

Q group permitting potential is applied to the corresponding inputs of the x-elements of the group of elements And 7 and the clock signal applied to the input 11 increases by one the contents of the x-8 counters of the 8th group and the counter 9. This is done

5 parallel computation of N functions of the distribution of frequencies ug (- -1, N) by the formula (2). The histogram rolling alignment operation is initiated by applying a histogram alignment signal to the input 13, which translates the second trigger 19

0 to the state "1 at the direct output and through the first element OR 15 - the first trigger 18 to the state" O at the output, as well as through the third element OR 17 whips the counter 29 and the second delay element 23 and through the fifth element OR 21 translates

5, the third trigger 22 in the "On at the direct output" state. The signal "1 from the direct output of the second trigger 19 through the fourth element OR 20 blocks the flow of signals from the first outputs of comparison blocks 5 of the group through the group of elements OR 6 to the corresponding information inputs of the group of elements AND 7, and the signal" O from the inverse output of the second trigger 19 commutes the outputs of the first delay element 2 through the first multiplexer 4

5 to the first inputs of N blocks of comparison 5 groups and the output of the third element AND 26 through the second multiplexer 31 to the control inputs of the group of elements AND 7, and also blocks the passage of clock signals from input 11 through the first element AND 24 to the counting input of counter 9, and passing clock signal through the second element And 25 to the input of the simple element OR 26 is blocked by the signal "O at the direct output of the third trigger 22. The controllable element of the delay 23 delays the arrival of the enabling signal from the direct output of the second trigger 19 to the second input r Another element is AND 26 on -

cycles of the device until the information from the reception register of the number 1 through the first delay element 2 arrives at the inputs of the first multiplexer 4. When the enable signal arrives at the second input of the third element And 26, the clock signals from input 11 through the third element And 26 arrive at input divider 27, which divides the frequency of the clock signals by a factor M equal to the number of elements in the neighborhood line for a two-dimensional digital signal, and passes the clock signals without changing their tracking frequency for a one-dimensional digital signal. The pulses from the output of the divider 27 through the sixth element OR 28 are input to the resolution 29 input and cause a signal to appear at one of the outputs of the decoder 30, which allows writing the value of the central element of the next neighborhood into the corresponding register 3 of the group 3 The status is "About the corresponding counter of group 8". Let the input 10 receives the next value of the digital signal. From the output of the receive register number 1, the information is fed to the inputs of the first delay element 2 and is recorded in the presence of a write signal from the decoder 30 in one of the registers of the 3rd group. The delayed information from the output of the first delay element 2 through the first multiplexer 4 is fed to the first inputs of N blocks of comparison 5 groups, where pG2

k

ten

in parallel, they are compared with the central elements of the N neighborhoods, which are stored in 3 groups of registers. The results of the comparison from the second outputs of the comparison blocks of the 5th group are sent to the first information inputs of the group of elements And 7, and the second information inputs of the last N elements of the group of 7 And 7 are given the enabling signals from the outputs of the blocked group of elements OR 6. The clock signal applied to the input AND passes through the third element And 26, the second multiplexer 31 and the open elements of the group of elements And 7 on the counting inputs of the corresponding counters 8 groups, increasing their contents by one. As a result, when any next value of a digital signal arrives, the content of those counters of group 8 is increased by unit, the contents of the corresponding registers 3 groups of which are not less than the value of the number delayed by cycles, and also if there is a record from the decoder 30, the contents of the corresponding register 3 are modified and reset the corresponding counter of group 8. In this way, the histogram of one-dimensional and two-dimensional digital signals is slantingly aligned. The algorithm used in the device for moving histogram alignment in the case of a two-dimensional digital signal requires inputting elements in the order shown in FIG. 2

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Claims (1)

DEVICE FOR BUILDING HISTOGRAMS, containing a group of registers, a group of N comparison blocks, a group of (N + 1) AND elements, a group of (Α-pl) counters, a number reception register, a first counter, an input of the number reception register is an information input of the device , the output of the i-ro register of the group (i = 1, N) is connected to the first input of the i-ro unit of comparison of the group, the output of "Not more" of which is connected to the first input of the i-ro element of the group And, the output of which is connected to the counting input i- ro group counter, characterized in that, in order to expand the functional the remainder by calculating the distribution function and performing the operation of moving alignment of the histogram, it contains a group of N OR elements, AND elements, multiplexers, a decoder, OR elements, triggers, a second counter, a delay element, a controlled delay element, a divider, the output register of the number through the delay element is connected to the first information input of the first multiplexer, the second information input of which is combined with the information inputs of the group registers and connected to the output of the number reception register, second e inputs of the group comparison units are combined and connected to the output of the first multiplexer, the control input of which is combined with the first input of the first element And, the control input of the second multiplexer and connected to the inverse output of the first trigger, the output of the first element And is connected to the counting input of the first counter and to the information input of the second multiplexer, the clock input of which is connected to the output of the second AND element connected to the input of the divider, the first inputs of the elements OR groups are combined and connected to the output of the first OR element, the “More” output of the i-ro group comparison unit is connected to the second input of the i-ro of the OR element of the group, the output of which is connected to the second input of the (i -ph 1) th element of the AND group, the second input of the first AND element of the group is combined with the third inputs of the remaining elements of the And group and the first (W + 1) -th element of the And group and is connected to the output of the second multiplexer, the input of setting the i-ro of the group counter to zero is connected to the i-th output of the decoder, the Λ'th output of which is connected to the output of the zero (N + 1) -th counter of the group, the first counter and the first input of the second OR element, the output of which is connected to the zero input of the second trigger, the unit input of which is combined with the zero input of the first trigger and connected to the output of the third ILI element, whose first input is combined with the first inputs of the fourth and fifth OR elements and is the first the “Mode Setting” input of the device, the installation input to the unit of the first trigger is combined with the second inputs of the second, fourth and fifth elements OR and are the second input of the device mode setting, the installation input to unit t the third trigger is combined with the second input of the third OR element and the third input of the fourth OR element and is the third input of the device mode setting, the output of the fifth OR element is connected to the zero input of the third trigger, the direct output of which is connected to the first input of the first OR element, the second input of which -> horn is combined with the information input of the controlled delay element and is connected to the direct output of the first trigger, the output of the controlled delay element is connected to the first input of the second element And, the second input of which is combined with the first input of the third element And and the second input of the first element And is the clock input of the device, the output of the fourth OR element is connected to the reset input of the controlled delay element and the reset input of the second counter, the output of which is connected to the decoder input, the counting input of the second counter under is connected to the output of the sixth element And, the second input of which is connected to the direct output of the second trigger, the inverse input of which is connected to the third input of the first element And, the second input of the sixth element OR is connected to the output of the divider, the input of the ith register of the group is connected to the t-th output of the decoder , the outputs of the group counters and the first counter are the output of the device.