SU1188742A1 - Microprogram control device - Google Patents

Abstract

MICROPROGRAM CONTROL DEVICE containing a signaling transition code decoder, AND first and second elements, address counter, condition switch, microprogram memory block, microinstructions register, return register and microinstrumenter decoder, the output of the address counter being connected to the information input of the return register, address input of the microprogram memory unit, the output of which is connected to the information input of the microinstructions register, the control input of the condition switch, the decoder input of the conditional transfer flag The water, the first and second outputs of the micro-command decoder are connected respectively to the input of the return register entry and the device micro-operations output, the device condition-assignment input is connected to the information input of the conditions switch, the output of which is connected to the first input of the first element, And the decoder output of the conditional transition sign is connected to the second input The first element And, the inverse output of which is connected to the first input of the second element And, the output of the second element And connected to the counting input of the address counter, distinguishing This is because, in order to improve speed, a mode assignment switch, an annular shift register, a comparison block, a cycle counter, a debugging start trigger, a debugging end trigger, a counting trigger, a NOT element, four OR elements and eight AND elements are introduced into it , the outputs of the beginning and end of the microprogram program of the mode setting unit are connected respectively to the first information input of the address switch and the first input of the comparison unit, the outputs of the number of cycles, setting the debugging mode, initial setting, starting, The cyclic mode, cycle limits and clock output of the mode setting unit are connected respectively to the information input of the cycle counter by the first input of the third element AND, the first input of the first element OR, the recording input of the cycle counter, the first input of the fourth element AND, the first input of the fifth element AND and the first input of the sixth element, And, i, the outputs of setting the debug mode, initial setting, starting the cyclic mode, and so (The output of the block for setting the modes is connected respectively to the first input of the seventh element And, the first input of the second element OR, the first input of the third element OR, and the synchronization input of the ring shift register, the output of the seventh element AND is connected to the second input of the first OR element, the output of which is connected to the input of the initial installation of the ring shift register, the second input of the sixth OS element AND zero input of the 00 debugging end trigger, single trigger input of the start of debugging, input of the zero setting of account 4; ib address and through the element NOT with the zero setting input of the counting trigger, first, second, third and third the third outputs of the ring shift register are connected respectively to the first input of the eighth element And, the first input of the ninth element And, the first input of the tenth element And and the zero input of the start of debugging trigger, the unit output of which is connected to the second input of the third element And, the first and second outputs of the ring the pulse distributor is connected respectively to the input of the register of microinstructions and with the second input of the second element I, the output of the third

Description

element AND is connected to the control input of the address switch and the first input of the fourth OR element, the second input of which is connected to the forward output of the first AND element, the output of the fourth OR element is connected to the second input of the ninth AND element, the output of which is connected to the write input of the address counter, the second output of the microinstructor decoder, the outputs of the microprogram memory unit and the return register are connected respectively to the second control input, the second and third information inputs of the address switch, the information output of which It is connected to the information input of the address counter, the information output of the address counter is connected to the second input of the comparator unit, the output of which is connected to the second input of the tenth AND element, the output of which is connected to the single trigger input of the debug end, the direct output of the debug end trigger is connected to the second input the eighth And element, the output of which is connected to the second input of the second OR element, the output of which is connected to the single input of the flashing end of the debugger end, the direct output of which is connected to the second input of the seventh And element, the output of the sixth element And is connected to the clock input of the counting trigger, the direct output of which is connected to the second input of the fourth element And and the counting input of the cycle counter, the overflow output of which is connected to the second input of the fifth element And whose output is connected to the inverse input of the fourth element And the output of which is connected to the second input of the third OR element, the output of which is connected to the zero input of the trigger of the end of debugging.

one

The invention relates to automation and computing and can be used in specialized processors.

The purpose of the invention is to increase the speed by executing the firmware in parts with an arbitrary setting of the address of the beginning of the firmware part, the address of the end of the firmware part and the number of repetition cycles of this part.

The drawing shows a block diagram of the device.

The device contains a mode setting unit 1, made in the form of a set of toggle registers and clock and single pulse generators, a three-position multi-bit switch 2 addresses, an address counter 3, a microprogram memory block 4, a micro-command register 5, a decoder 6 micro-instructions whose output is output device, return register 7, conditional branch decoder 8, multi-position single-bit condition switch 9, whose input is the device input, ring shift register 10, comparison block 11, count IR 12 cycles, debug start trigger 13, debug end trigger 14, debug stop trigger 15, counting trigger 16, AND 17-24 elements with two inputs each, AND 25 element with direct and inverse output, AND 26 element with two direct and one inverse input, the elements OR 27-30 and the element NOT 31.

The principle of operation of the device is as follows.

In the operating mode, a zero signal is generated at the output of the debugging mode of the mode setting unit 1. In this mode, upon receipt of a pulsed positive signal from the output of the initial installation of block 1, this signal through element 28 OR enters the inputs of the initial installation of the counter 3 of the address and the ring shift register 10, sets one of its bits to one.

in the rest - in zero. The effect of this signal on other elements of the device in this mode is not significant. After the end of the initial setup signal, the single signal is moved in the ring shift register 10 under the influence of pulses from the clock output of the mode setting unit 1. At the same time, at four outputs of register 10, a comb of pulses is formed, shifted relative to each other and forming respectively four working phases within one repetition interval, which is a micro tactom of operation of the device.

During this micro-tact, the next micro-command is formed at the output of the decoder of 6 micro-commands, which is the output of the device as a whole, as follows.

The contents of the 3 address counter are fed to the input of the 4 microprogram memory, from the output of which the code

The 0 microcommands are recorded into the register of 5 microcommands by the signal of the first phase of the ring register 10. The signal of the register 5 microcommands is sent to the decoder of 6 microcommands, and from its output the control signals are output to the device. The signal of the third phase of the ring register 10 passing through one of the elements 17 or 18 changes the contents of the counter 3 of the address and at the output of the microprogram memory block 4 a micro-command code is generated for the next micro-work of the device. The formation of the address in the counter 3 for the next micro-tact depends on the type of micro-command formed in the current micro-tact. Two types of micro-commands can be formed in the device: a simple micro-command and a conditional transition, distinguished by a sign of a conditional transition in the micro-command code. If a simple microinstruction is selected from the microprogram memory block 4 in the current microcode, then a zero signal is generated at the output of the decoder 8 of the conditional transition sign, which causes the appearance of a single signal at the output output of the And 25 element, which permits the ring register to pass through the And 17 element of the third signal 10 to the counting input of the address counter 3, with the result that one is added to the contents of the counter. In the next micro-tact, the device forms a micro-command whose address differs by one from the address of the current simple micro-command. If a conditional branch command is selected from the microprogram memory block 4 in the current microcode, then a single signal is output to the output of the decider 8 of the conditional branch sign for the element 25. At the same time, the control input of the switch 9 is received from the microprogram memory block 4 . In this case, the switch 9 transmits to the second input of the element I 25 a signal of one of the conditions from its own input, the number of which is encoded in the micro-command. If this condition is fulfilled, a single condition signal arrives at the AND 25 element, and a single signal is generated at its output that passes through the OR element 27 at the AND 18 element, ensuring the third phase signal of the ring register 10 passes to the input of the counter 3 address. At the same time, the address is recorded in the address 3, which arrives at its information input from the microprogram memory block 4 via the switch 2, which ensures the device to go to the microprogram address specified in the current microcommand of the conditional transition. In case the condition checked in the current microcommand is unfulfilled, then one is added to the contents of counter 3 in the same way as described above with a simple command. During the transition from the main firmware to the standard micro subprogram, an address latching command is formed, using which the control signal of the third output of the decoder 6 records the current address value from the counter 3 to the return register 7. In the next micro tact, a conditional branch command is generated; at the end of which a transition is made to the return micro-command. When executing a return micro-command, the decoder 6 micro-commands generate a signal at its second output, which arrives at the control input of switch 2 and places it in the mode of passing the signal from the return register 7. An unconditional jump to the address stored in return register 7 is then performed. After returning to the specified address, follow-up micro-instructions are formed until the end of the microprogram. In the debugging mode, a single signal is set at the debug output of the mode setting unit 1. In this mode, upon receipt of a pulsed positive signal from the output of the initial installation of block 1, this signal goes through the OR element 29 to the input of the trigger 15 and sets it to one state. The trigger signal 15 through the element And 21 and the element OR 28 is fed to the input of the initial installation of the ring shift register 10 and holds it in the initial state for any time as desired by the operator. At the same time, the device does not work and is in standby mode until a single pulse signal is generated at the start output of unit 1. At the same time, the initial setup signal sets the microprogram start trigger 13 to one, the microprogram end trigger 14 to the zero state. At the same time, the output signal of the trigger 13 through the open element 19 And enters the switch 2 and switches it to the mode of passing the code from the output of the beginning of the firmware of the mode setting unit 1. In addition, the output signal of the trigger 13 through the elements AND 19 and OR 27 enters the element And 18, preparing it to pass the signal to the input of the record of the counter 3. When forming a single pulse signal at the output of the start of the unit 1 signal, it enters the input of the record of the counter 12 cycles , writes into it the number of cycles coming from the corresponding output of block 1. At the same time, the start signal through the element OR 30 sets the trigger 16 to the zero state, which activates the ring shift register 10, which is affected by the clock Nala unit 1 begins to operate similarly to the above. In the first micro-cycle, the signal of the first phase of the ring register 10 registers in the micro-command register 5 an empty micro-command from the zero cell of the microprogram memory block 4 corresponding to the zero state of the address counter 3. The third phase signal of register 10 through the element And 18 is recorded in the counter 3 addresses through the switch 2 of the address of the beginning of the firmware from the corresponding output of the mode setting unit 1. The fourth phase signal of the ring register 10c resets the microprogram start trigger 13 to the zero state and switches the switch 2 and OR element 27 to the operating mode, ensuring the circuit is closed to perform conditional transitions by the device as described above. In the second and subsequent micro-tacts, the device forms micro-commands similar to the operating mode described above, however, starting with the micro-command set at the output of the microprogram beginning of unit 1. The address of the executable micro-command from counter 3 goes to the comparison unit 11, the second input of which is the end address microprograms installed at the corresponding output of the mode setting unit 1. When the firmware generated by the device reaches an address equal to the end address, a single signal is output at the output of the comparator unit 11, arriving at the AND 20 element. At the same time, the signal of the second phase of the ring register 10, in which the last microcommand is executed, through the AND 20 element enters the trigger 14 of the end of the firmware and sets it to one. The output signal of the trigger 14 opens the element AND 22. After the final microcommand has been executed in the next micro-tact, the signal of the first phase of the ring register 10 passes through the elements AND 22 and OR 29 and sets the trigger 15 to the one state. The output signal of the trigger 15, the passage through the elements AND 21 and OR 28 sets the device to the initial state similarly to the initial installation signal of block 1. If a single signal is not set at the output of the cyclic mode of block 1, the microcommands at the output of the device end at this point, after which operation of the device can be repeated as described above, however, with other values of the beginning and end of the microprogram set in block 1. If the output of the cyclic mode of block 1 is set to a single signal, then after the first cycle of the firmware execution from the initial to the final address, as outlined above, the signal from the output of the element OR 28 opens the element AND 24, through which the clock signal of unit 1 enters the counting input of the trigger 16 and puts it into the unit state. The output signal of the trigger 16 through the element AND 16 and the element OR 30 resets the trigger 15 to the zero state. After that, the operation of the device is repeated from the start address to the end address in a manner similar to that described above. The zero signal from the output of the element OR 28 through the inverter 31 sets the counting trigger 16 to the zero state. Thus, at the output of the trigger 16, a positive impulse is generated at the end of each microprogram operation cycle, which, besides the AND 16 element, also enters the counting input of the 12 cycle counter, which operates in the countdown mode and after each cycle decreases its content by one. The repetition of the formation cycles of the debugged part of the firmware from the starting address to the final address occurs until the contents of the counter 12 reaches zero. In this case, the signal from its output goes to the AND 23 element and, in the presence of a single signal at the output of the restriction of cycles of block 1, passes through the AND 23 element and prohibits the passage of signals through the AND 23 element and prohibits the passage of signals through the AND 26 element, resulting in a new cycle not starts and the device ends. Further, the operation of the device can be repeated with other values of the microprogram addresses and the number of cycles installed at the outputs of block 1, similarly to the above. If the output of the limiting cycles of block 1 is set to zero, the signal from the output of the counter 12 cycles will never pass through the element 23, as a result of which the repetition cycles of the debugged part of the microprogram are executed infinitely.

Claims (1)

A microprogram control device comprising a conditional transition decoder, first and second AND elements, an address counter, a condition switch, a microprogram memory block, a micro-register, a micro-register, a micro-register and a micro-instruction decoder, the output of the address counter being connected to the information of the return register, the address input of the block firmware memory, the output of which is connected to the information input of the micro-command register, the control input of the condition switch, the input of the decoder of the conditional transition sign, the second and second outputs of the micro command decoder are connected respectively to the input of the return register record and the output of the device microoperations, the input of the device conditions setting is connected to the information input of the condition switch, the output of which is connected to the first input of the first element AND, the output of the conditional sign decoder is connected to the second input of the first element And, whose inverse output is connected to the first input of the second element And, the output of the second element And is connected to the counting input of the address counter, characterized in that, with In order to improve performance, it introduced the mode setting block address switch, ring shift register, comparison block, cycle counter, debug start trigger, end debug trigger, counted trigger, element NOT, four OR elements and eight AND elements, and the outputs of the beginning and end of the firmware of the mode setting unit are connected respectively to the first information input of the address switch and the first input of the comparison unit, the outputs of the number of cycles, setting the debug mode, initial setting, start-up, setting the cyclic mode , cycle limits and clock output of the mode setting block are connected respectively to the information input of the cycle counter by the first input of the third AND element, the first input of the first OR element, the recording input cycle counter, the first input of the fourth element And, the first input of the fifth element And and the first input of the sixth element And, the outputs of the job mode debugging, initial installation, start-up cyclic mode and the clock output of the unit mode settings are connected respectively to the first input of the seventh element And, the first input of the second OR element, the first input of the third OR element and the synchronization input of the circular shift register, the output of the seventh element And is connected to the second input of the first OR element, the output of which is connected to the input of the initial settings of the ring shift register, the second input of the sixth element And the zero input of the trigger for debugging end, the single input of the trigger for debugging start, the input for setting the address counter zero and through the element NOT with the input for setting the counting trigger zero, the first, second, third and fourth outputs of the ring shift register are connected respectively, with the first input of the eighth AND element, the first input of the ninth AND element, the first input of the tenth AND element and the zero input of the start debug trigger, the single output of which is connected to the second input of the third element And, the first and second outputs of the ring pulse distributor are connected respectively to the input of the micro-register register entry and to the second input of the second element And, the output of the third element And is connected to the control input of the address switch and the first input of the fourth OR element, the second input of which is connected to the direct output of the first AND element, the output of the fourth OR element is connected to the second input of the ninth AND element, the output of which is connected to the recording counter input address, the second output of the micro command decoder, output The microprogramme memory block and the return register are connected respectively to the second control input, the second and third information inputs of the address switch, the information output of which is connected to the information input of the address counter, the information output of the address counter is connected to the second input of the comparison unit, the output of which is connected to the second input of the tenth element And, the output of which is connected to a single input of the trigger of the end of debugging, the direct output of the trigger of the end of debugging is connected to the second input of the eighth element of And, exit which is connected to the second input of the second OR element, the output of which is connected to a single input of the end debug trigger, the direct output of which is connected to the second input of the seventh AND element, the output of the sixth element And is connected to the clock input of the counting trigger, whose direct output is connected to the second input of the fourth element And and the counting input of the loop counter, the overflow output of which is connected to the second input of the fifth element And, the output of which is connected to the inverse input of the fourth element And, the output of which is connected to the second input ohm of the third OR element, the output of which is connected to the zero input of the trigger for the end of debugging.