SU645453A1 - Multiprogramme control device - Google Patents

Description

The invention relates to computer technology and can be used in computer control devices.

A microprogram control device is known in which the microcommand comprises an operational part consisting of N fields of microoperations. Microoperations are performed one after another sequentially (1, 2, 3, ..., N), and there may be two options for performing ¹⁰ microoperations. In the first case, a fixed time interval is allotted for each microoperation and its value is chosen equal to the duration of the longest microoperation. 15 In the second case, the signal of the end of the previous microoperation triggers the next.

The disadvantage of this device is a rigid ² θ cue order for performing microoperations. ''

Closest to this invention, the technical solution is a microprogram control device comprising a micro-command memory block, a micro-command register, an address generation block, a first group of AND elements, a synchronization block, the control outputs of which are connected to the control inputs of the micro-memory block, register of 30 micro-commands, address generation unit, the input of which is an address input unit, and an output coupled to the address input of the microinstruction storage unit ⁵ first inputs of aND gates of the first group cos ineny yield microinstruction register input connected to the first output of the storage unit microinstructions * outputs of AND gates of the first group are the outputs of the device control signals.

The disadvantage of this device is the strict procedure for performing microoperations, determined by the location of microoperations in the micro-team. To implement a microprogram consisting of a set of microoperations, which is specified by the algorithm, a large number of microcommands is required, since the strict order of launching microoperations does not allow performing microoperations in a single microcommand cycle in a manner different from their actual location in the operational part of the microcommand. Correspondingly, the number of memory calls of 'microcommands, the duration of which' is comparable with the duration of the execution of microcommands, is increasing. The runtime of the firmware increases, and the performance of such a firmware control device cannot be sufficiently high.

-. 4

The purpose of the invention is to increase the speed of the firmware control device.

This goal is achieved by the fact that the device contains an order code register · · · ka, an order code decoder, a register. triggering signals, the second group of AND elements, the first inputs of which are connected to each other and with the output of the synchronization block, the second inputs are with the outputs of the de-encoder of the order code, and the outputs are with the inputs of the trigger signal register, the outputs of which are connected to the second inputs of the AND elements of the first group, the input of the decoder of the order code is connected to the output 15 of the register of the order code, the information input connected to the second output of the micro-memory block, and the control input to the output of the synchronization block. ²⁰

The drawing shows a block diagram of a device that contains a memory unit 1 microcommands, register 2 microcommands, block 3 synchronization, block 4 formation of addresses, the first group of elements And 25 5, register 6 order code, decoder 7 order code, register 8 trigger signals, . the second group of elements And 9.

The device operates as follows. thirty

Block 3 selects at the address issued by block 4 to block 1, the micro-command coming to register 2 and register 6. A code is received on register 6, indicating the order of microoperations of this micro-command. Block 3 generates a signal for the start of the microcommand input to the first groups of elements And 9. At the second input of one of the elements And 9 of the second group, a signal is received from the 40 output of the decoder 7, namely from the output corresponding to the code on the register 6. The open element And 9 is the second group includes the corresponding bit of register 8, the signal from which opens the element And 5 45 of the first group, passing control signals of the first microoperation to the device output. The signal for the end of the current microoperation enters block 3, which makes it possible for the decoder ^{50 to} excite the element And 9 the second

The troupe corresponding to the following microoperation. This continues until all micro-operations indicated in the micro-command are completed. Next, block 3 selects from block 1 to registers 2 and 6 the next micro-command and starts it.

The device allows you to implement algorithms in which the order of microoperations is not rigid and can be changed if necessary, and this change does not increase the number of micro-commands, the runtime of the microprogram and reduce the speed of the microprogram control device.

Claims (1)

--..... ......... ... ,, -....: -: -....; .... The purpose of the invention is to increase the speed of the microprogrammed control device. The goal is achieved by the fact that the device contains the order code register, the order code decoder, the trigger register, the second group of elements AND whose first inputs are connected to each other and to the output of the synchronization unit, the second inputs to the code decoder's outputs, and outputs - with start-up signal register дамиhbdami, outputs of which are connected to the second inputs of the AND elements of the first group, the order code decoder input is connected to the output of the order code register, the information input connected to the second output memory block These are the commands of these commands, and the control input is with the output of the synchronization unit. The drawing shows a block diagram of a device that contains a block of 1 memory of micro-instructions, a register of 2 micro-instructions, a block 3 of synchronization, a block 4 of the formation of addresses, a first group of PI 5 elements, a register 6 of order code, a decoder 7 of order code, register 8 of signals run, the second group of elements And 9. The device operates as follows. Unit 3 selects, at the address issued by unit 4 to unit 1, a microcommand arriving at register 2 and register 6. On register 6, a code is received indicating the order in which the microoperations of this microcommand are executed. Block 3 generates a start signal of the microcommand that arrives at the first groups of elements AND 9. The second input of one of the elements 9 of the second group receives a signal from the output of the decoder 7, namely from the output corresponding to the code on the register 6. The open element 9 of the second The group includes the corresponding register bit 8, the signal from which opens the element And 5 of the first group, the control signals of the first micro-operation being passed to the device output. The signal of the end of the current micro-operation enters the block 3, which allows the decoder 7 to excite the element AND 9 of the second. . Troupe corresponding to the following micro-operation. This continues until all the microoperations specified in the microcommand are executed. Further, block 3 selects from block 1 for registers 2 and 6 the next micro-command and starts it. The device allows the implementation of algorithms in which the order of micro-operations is not hard and can be changed if necessary, and this change does not lead to an increase in the number of micro-instructions, the execution time of the microprogram, and a decrease in the performance of the microprogrammed control device. Microprogram control device containing microinstructions memory block, microinstructions register, address generation unit, first group of elements AND, synchronization unit, control outputs of which are connected to microinstructions memory control module inputs, microaddress register, addresses-forcing unit, input which is the address input of the device, and the output is connected to the address input of the microinstructions memory block, the first inputs of the AND elements of the first group are connected to the output of the microinstructions register, the input The first unit of the microcomputer memory, the outputs of the elements And the first group are the outputs of the control signals of the device, characterized in that, in order to improve speed, it contains the order code register, the order code decoder, the trigger signal register, the second group of elements And, the first inputs of which are interconnected and with the output: the synchronization unit, the second inputs - with the decoder code outputs of the order code, and the outputs - with the inputs of the trigger register, the outputs of which are connected to the second inputs of the AND elements The first group, the input of the order code decoder is connected to the output of the order code register, the information input connected to the second output of the microcommand memory block, and the control input to the output of the synchronization block.