SU1186057A1 - Flip-flop device (design versions) - Google Patents

Abstract

FIELD: pulse engineering. SUBSTANCE: flip-flop device available in three design versions has in first version flip-flop, first and second NAND gates, OR gate, first and second series RC circuits whose resistor leads are connected to common and their common points, to first and second inputs of OR gate, respectively; first inputs of first and second NAND gates are connected to device input and second inputs, to direct and inverted outputs of flip-flop, respectively; novelty is that it is provided, in addition, with first and second resistors as well as third series RC circuit whose capacitor lead is connected to common bus, resistor lead, to OR gate output, and point, to clock input of flip-flop; first and second inputs of OR gate are connected to common leads of first and second RC circuits through first and second resistors, respectively; OR gate is built around CMOS structure. In second version, newly introduced are first and second resistors and third RC circuit whose capacitor lead is connected to common bus, resistor lead, to OR gate output, and common point, to second input of NAND gate whose output is connected to clock input of flip-flop whose direct and inverted output are connected, respectively, to capacitor leads of first and second RC circuits; common points of the latter are connected, respectively, to first and second inputs of OR gate through first and second resistors; OR gate is built around CMOS structure. In third version, newly introduced are EXCLUSIVE OR gate, whose first and second inputs are connected to common points of first and second RC circuits whose capacitor leads are connected to common bus and resistor leads, to direct and inverted outputs of flip-flop, respectively; NAND gate output is connected to flip-flop clock input and second input of NAND gate, to EXCLUSIVE OR gate output; time constant of first RC circuit in not equal to that of second RC circuit. EFFECT: reduced size and power requirement.