SU1149253A1 - Versions of device for multiplying frequency by code - Google Patents

Abstract

1. A device for multiplying a frequency with a code containing a clock, a frequency divider, a counter, a register, a controlled divider and a pulse shaper, which is connected to the information input of the device, and the first output is connected to the reset inputs of the frequency divider and counter, the outputs of which connected to the information inputs of the register, the outputs of which are connected to the information inputs of the control divider, the output of which is connected to the output of the device, the clock input of the controlled divider is connected to the clock input the house of the frequency divider and the output of the generator of clock pulses, characterized in that, in order to increase the reliability of the function-. Nor by eliminating the possibility of large errors of multiplication, the element I is entered into it, the first input and output of which are connected respectively to the output of the frequency divider and the clock input of the counter, and the pulse shaper contains the first, second and third single-vibrators, and the first single-vibrator input connected to the input of the pulse generator, the inverse output of the first one-shot one-shot is connected / not to the input of the second one-shot, the direct output of which, being the BTopfciM output of the pulse shaper, is connected to the clock m input of the register, and the inverse output with the input of the third one-oscillator, the output of which is connected to the first output of the pulse former and connected to the reset input of the controlled split (L l, the inverse output of the first one-oscillator, the third output C of the pulse former, is connected to the second input Element I. 2, Device for multiplying frequency by a code containing a clock, frequency divider, counter, register controlled by 4; the divider and pulse shaper, with to to the first input of which is connected to the information input of the device, and the joint venture the first output to the reset inputs of the frequency and counter body, the outputs of which are connected to the information inputs of the register, the outputs of which are connected to the information inputs of the controlled divider, the output of which connected to the output of the device, the clock input of the controlled divider is connected to the clock input of the frequency divider and the output of the clock pulse generator, characterized in that, in order to increase reliably ti functioning by

Description

prevent the occurrence of large errors of multiplication, the element I is entered into it, the first input and output of which are connected respectively to the output of the frequency divider and the clock input of the counter, and the pulse generator contains the first and second triggers and the first and second elements AND, and the installation input of the first the trigger is connected to the first input of the pulse former, the inverse output of the first trigger is connected to the first input of the first element AND the pulse former, the second input of which is connected to the second input of the primary pulse pulses, a clock pulse output with a clock input of the second trigger 53 ra and with a first input of the second element And a pulse driver, the second input of which is connected to the direct output of the first trigger and D is the input of the second trigger, the output of which is connected to the third inputs of the first and second elements and pulse generator, the output of the second element and pulse generator is the second code of the pulse generator and is connected to the reset input of the first trigger and to the clock input of the register, the output of the first element and a pulse shaper is the first output of the pulse shaper and is connected to the reset input of controllable divider.

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The invention relates to devices that provide an execution of the multiplication operation, and can be used in specialized computational devices to multiply the numbers given by the frequency of the pulses by the numbers given in the form of codes.

A device is known which makes it possible to multiply the frequencies with a variable pulse repetition period.

The disadvantage of this device is the relatively low reliability of operation.

Closest to the invention is a device comprising a pulse generator, a controlled divider, a counter, a register and a code-controlled counter, the output and control inputs of which are connected respectively to the output of the device and the output of the register information and control inputs are connected respectively to the output of the counter and the input of the controlled divider, the output and the reset input of which are connected respectively to the counting input of the counter and the output of the clock generator, which is connected to the input auxiliary ADDITIONAL counter, and the counter reset input connected to the clock input of the register

and the output of the input shaper reference signal 2

A disadvantage of the known device is also relatively low reliability of operation, due to the fact that the input signal of the frequency type is not synchronized with the clock frequency pulses, therefore, it can come at an arbitrary time, which will cause a record from the counter to the instantaneous code value register, found right now. In addition, at some values of the input signal frequency (close to the clock frequency), the input pulses arrive at the moment of switching the counter, and at the time of the transition process in the counter, the code at its output may be more than twice different from the code in the previous and next times that Gives a significant increase in multiplication error.

The aim of the invention is to increase the reliability of operation by eliminating the possibility of the occurrence of large multiplication errors.

The solution of the problem is possible by ensuring the separation in time of the transient moment in the counter and writing the code to the register when an output pulse appears. The goal is achieved in that the device for multiplying the frequency by a code containing a clock, a frequency divider, a counter, a register, a controlled divider and a pulse shaper, whose input is connected to the information input of the device, and the first output to the frequency divider reset inputs and a counter, the outputs of which are connected by the synformational inputs of the register, the outputs of which are connected to the information inputs of the control divider, the output of which is connected to the output of the device, the clock input of the control The divider is connected to the clock input of the frequency divider and the output of the clock pulse generator, an element I is inputted, the first input and output of which are connected respectively to the output of the frequency divider and the clock input of the counter, and the driver of the pulses contains the first, second and third single vibrators, and the first input the one-shot is connected to the input of the pulse former, the inverse code of the first one-shot is connected to the input of the second one-shot, the direct output of which is the second output of the pulse former, soy Inen with the register clock input, and the inverse output with the input of the third oscillator, the output of which is connected to the first output of the pulse former and connected to the reset input of the controlled divider, the inverse output of the first single vibrator, which is connected to the third output of the pulse former, is connected with the second input of the element I. According to the second embodiment 8, the device of the day multiplying the frequency with the code is entered the element I, the first input and output of which connected respectively to the output of the frequency divider and the clock input of the counter, and The pulse generator contains the first and second triggers and the first and second elements I, and the installation input of the first trigger is connected to the first input of the pulse former: the inverse output of the first trigger

dinene with the first input of the first element And the pulse former, the second input of which is connected to the second

contains the first 14 and second 15 triggers, the first 16 and second 17 elements I, the input of the pulse former, with the output of the clock pulse generator, the clock input of the second trigger and the first input of the second element And the pulse former, the second input of which is connected to direct output of the first trigger and with the D input of the second trigger, the output of which is connected to the third inputs of the first and second elements And the pulse generator, the output of the second element And the pulse driver, is the second output of the pulse former and with of the connections with the reset input of the first flip-flop and taktov№1 input register, an output of first AND pulse shaper is pervm output of the pulse shaper and the reset input is connected to the controllable divider. The clock generator, the counter, the register, the frequency divider and the controlled divider according to the second embodiment of the device are completely identical to those of the first embodiment. FIG. 1 is a block diagram of a device for multiplying a frequency with a code according to the first embodiment, FIG. 2 - the same, according to the second embodiment. The device for multiplying the frequency by the code in the first embodiment contains a generator (n 1 clock pulses, divider 2 frequencies, counter 3, register 4, control & 1 divider 5, element I6, driver 7 pulses, information input 8 of the device, output 9 of the device , inputs W of the control code of the frequency divider. The pulse shaper contains the first 1, second 12 and third one-shot 13. Device dn multiply the frequency by the code according to the second variant contains the generator 1 clock pulses, divider 2 frequencies, counter 3, register 4, controlled Divider 5, element 6 and pulse generator 7, device information input 8, device output 9, frequency divider control code inputs 10. Pulse driver 7 s The device for frequency multiplication by code works in the following manner. The code for which the input frequency should be multiplied The signal supplied to input 8 is specified as a division factor of the 2 frequency divider or the internal structure of the latter, if this code is constant or controlled by code on the inputs 10. Thus, the frequency divider 2 divides the frequency of the pulses by the output of the clock pulseN generator, where N is the division factor. At the output of the divider 2 frequency will be a signal with a frequency of f / N. At the moment of arrival at the input 8, the shaper 7 is started. At the shaper output, a zero signal appears, blocking element AND 6, as a result of which the last code calculation cycle starts in the counter 3, which ends during the pulse time generated by the second single vibrator 12, the output the signal of which launches the third one-shot 13, the output signal of which ensures the reset of the counters and dividers, after which the device is ready for a new operation cycle in which the code equal to I is recorded in register 4 and controls the coefficient The dividing unit of the controlled splitter 5, at the output of which a signal is formed with a frequency equal to By Thus.

% y / 3 .6 provides frequency multiplication by code. with the exception of large errors due to the fact that the record in the register is related in time from the moment of arrival of the last counting pulse to the input of counter 3. The device according to the second embodiment works in a similar way with the difference that the input signal from the input 8 starts the shaper 7, in which the trigger 14 is switched, the signal from the inverse output of which blocks the element 6, and upon receipt of a clock pulse, the unit code is rewritten into the trigger 15, the output signal of which allows the passage The clock pulse to clock A register 4 through the element And 17, which also sets the trigger 14 to the zero state on the falling edge, as a result of which the counter and dividers are reset by a clock pulse. to the initial cool state, and the trigger 5 returns to its initial state on its falling edge, and the device is ready for a new cycle of operation. In this way, a significant reduction in the maximum possible multiplication errors is achieved, which makes it possible to increase the reliability of the multiplication devices.

Fyg.1

Claims (2)

1. A device for multiplying the frequency by a code containing a clock generator, a frequency divider, a counter, a register, a controlled divider and a pulse shaper, the input of which is connected to the information input of the device, and the first output is connected to the reset inputs of the frequency divider and counter, the outputs of which are connected with information inputs of the register, the outputs of which are connected to the information inputs of the control divider, the output of which is connected to the output of the device, the clock input of the controlled divider is connected to the clock input of the cases and the output frequency of Tell clock pulse generator, characterized in that, in order to increase the reliability func- ··. By eliminating the possibility of the appearance of large multiplication errors, an AND element is introduced into it, the first input and output of which are connected respectively to the output of the frequency divider and to the clock input of the counter, and the pulse shaper contains the first, second, and third one-shots, and the input of the first one-shot is connected to pulse shaper input, the inverse output of the first one-shot vibrator is connected to the input of the second one-shot, whose direct output, which is the second output of the pulse shaper, is connected to the clock input home register and the inverse output - to an input of the third monostable multivibrator, whose output is connected to the first output of the pulse and is connected to g being the third output of the pulse shaper reset input managed divider inverse output of the first monostable multivibrator, coupled to the second input element I. 2. A device for multiplying the frequency by a code containing a clock generator, a frequency divider, a counter, a register, a controlled divider and a pulse shaper, the first input of which is connected to the information input of the device, and the first output is connected to the reset inputs of the frequency divider and counter, the outputs of which connected to the information inputs of the register, the outputs of which are connected to the information inputs of a controlled divider, the output of which is connected to the output of the device, the clock input of the controlled divider is connected to the clock input ohm of the frequency divider and the output of the clock generator, which is different in that, in order to increase the reliability of operation by eliminating the possibility of the appearance of large multiplication errors, an element And, the first input and output of which are connected respectively to the output of the frequency divider and the clock input counter, and the pulse shaper contains the first and second triggers and the first and second elements And, and the installation input of the first trigger is connected to the first input of the pulse shaper, the inverse output the first trigger is connected to the first input of the first element And the pulse shaper, the second input of which is connected to the second input of the pulse shaper, the output of the clock generator with the clock input of the second trigger and the first input of the second element And the pulse shaper, the second input of which is connected to the direct output of the first the trigger and with the G input of the second trigger, the output of which is connected to the third inputs of the first and second elements And the pulse shaper, the output of the second element And the pulse shaper I the second output of the pulse generator and is connected to the reset input of the first flip-flop and to the clock input of the register, the output of first AND pulse shaper is the first output of the pulse generator and is connected to the reset input of divider managed.