SU1140130A1 - Function generator - Google Patents

Abstract

FUNCTIONAL TRANSFORMER, containing the first group of p

Description

The invention relates to automation and computing and is intended for the mechanization of manual methods for the synthesis of logic circuits in automated design systems.

Known functional Converter containing a counter, switch, encoder, elements, and counting triggers 1.

Despite significant hardware costs, this device allows you to find its Zhegalkin polynomial for a given Boolean function, if in the latter all variables are not inverted.

The closest to the technical essence of the invention is a spectrum analyzer consisting of a counter and serially connected channels, each of which contains a delay unit and an arithmetic unit that contains a serially connected And element and a modulo two 2.

This device is implemented with less hardware costs, but it also allows you to find for a given Boolean function only its Zhegalkin polynomial in which all variables are not inverted.

The closest in technical essence to the invention is a spectrum analyzer consisting of a counter and serially connected channels, each of which contains a delay block and an arithmetic unit. which contains a series-connected element And and a modulo two 2.

This device is implemented with less hardware overhead, but also allows it to be found for a given boolean function. only its Zhegalkina polynomial in which all variables are not inverted.

The purpose of the invention is to extend the functionality by implementing the full Zhegalkin of a given type, in which each variable is included either directly or with inversion.

The goal is achieved by the fact that a functional converter containing the first group of n (2-conversion size) charge elements, n arithmetic 15 blocks, the 1st (1, n) arithmetic unit containing the first And element and the modulo two, the first input of which connected to the output of the element I, the first input of which is connected to the output of the i-ro delay element of the first group, the control unit containing the counter, the direct output of the i-ro (, n) of the discharge of which is connected to the second input of the first element And the i-ro arithmetic block entered second a group of n delay elements, in the i-th arithmetic unit - the second and third elements AND, and in the control unit - n elements AND, n AND-NOT elements and n triggers, and in the i-th arithmetic unit the second and third passes of the adder module two are connected to the outputs of the second and third elements AND, the first inputs of which are connected to the outputs of the i-ro element AND, NOT and the i-ro element of the control unit, the first inputs of which are connected to the output of the i-ro trigger of the control unit, respectively my and inverse outputs of the i-ro discharge counter of the control unit n Connected to the second inputs, respectively, the i-ro element of the NAND and the i-ro element of the AND control block, the output of the modulo two j-ro (j 1, n-1) of the arithmetic unit is connected to the second input of the third And element (j + l ) -ro arithmetic unit and the input (j + 1) -th delay element of the second group, the output of which is connected to the second input of the second element AND (j + 1) th arithmetic unit and the input (j + 1) -th delay element of the first group , the output of the modulo two nth arithmetic block is the information output of the converter, the second input of the second el The first AND element of the first arithmetic unit is connected to the input of the first delay element of the first group and connected to the output of the first delay element of the second group, the input of which is connected to the second input of the third element AND of the first arithmetic unit and is the information input of the converter.

FIG. 1 shows the structure of the functional converter; in fig. 2 and 3 are block diagrams of the arithmetic unit and the control unit, respectively.

The functional converter consists of the block 5, 1, the delay elements 2; |,, .. 2п and 3,), ... 3, the arithmetic blocks 4, (, ... 4f |, each of which contains the elements AND 5, 6 and 7 and the adder 8 modulo two, the control unit 1 consists of a n-bit counter 9, triggers lOj ,, ... 10., elements AND-NOT 1C, ... 1Ci elements And 12, ... 12 " The outputs 13, ... 13 ", ... 14, ... 14 (,, 15;, ... 15. control unit 1 are connected correspondingly to the inputs of elements 5, 6 and 7 of the arithmetic units 4, ... four.

The delay elements 2 and 3 of the first channel delay the input binary sequence by one cycle each. The delay elements in each subsequent channel delay twice as much as in the previous channel.

Consider the aglo-rhythm of calculating the coefficients of the Zhegalkin polynomial implemented by the device. Let a Boolean function be given by its truth vector t (f, ..., fgi.,), Where fj can be either zero or one (} 0,). An arbitrary Boolean function is representable by the Zhegalkin polynomial of the following form iUn,.,., ... ipi.ch (0 where 2 is the sum of two moduli, x i This is either x; or x (, ... n), and 1 if K; j: 0. The values of F (k, ..., k) can be either zero or one. Since each variable x is in (1) either directly or with inversion, there are a total of 2 different a polynomial of the form (1), and if all the variables are not inverted, then we have the traditional Zhegalkin polyp, the coefficients of which can be calculated using a prototype device. For example, with n 2 and x "x", x - have polynomial f (Xj, x,) F (0,0) ffiF {0, l) .. F (l, 0) x, © F (l, l) Xj To get the vector J of the coefficients F (k, .. k), it is necessary to multiply the vector f by the n-fold direct (Kronecker) product of the matrix as i 1, ... n. If the variable is not inverted, then hi в, otherwise, in the case of hi 1 In order to find the n-fold direct product of H matrices (2), we can use the following recursive relation n-, b, n ".Л,., Ь" н „ .And where H |. - matrix of 2 x 2 size, which is a (n-1) -fold Kronecker product of matrices (2), considered with i 1, ... n-1. For n 2, multiplying the vector of values of the function f (x, ..., x) by the matrix H is written as follows. This relation can be represented as a system of the following four equalities written in the bracket form F (0,0) (fo ®0 © h, f,) ®0 © h, (fj®0®h, p, F (0, l) - (h, f © fo®0) ®0®h2 (h, f, ®f2 © 0), (3 ) F (l, 0) h2 (, f) ® (f (90 ® h,) @ 0, F (, 1) h (hf, @ fj Ф 0) € t (R, f, Ф 0 0) ® 0 For n 2, the operation algorithm of this device is determined by the system of equalities (3). This device allows calculating the coefficients of the Boolean functions polynomial even when their originality of length 2 is input directly to another g after another. The sequence of 2 zeros and; units - coefficients of the Zhegalkin polynomial is generated with a delay of 2 -1 cycles in relation to the Truth Teacher, i.e., the coefficient is formed in the same cycle in which the last value of the Boolean function is input. The Zhegalkin polynomial is given by the values h, ..., h, stored respectively in the triggers 10, ... 10 and equal to one if the corresponding non-temporary x, ..., Xj are inverted, and identical to zero otherwise. Consider the operation of this device for p 2, which is described by the equation system (3). In the first cycle, the counter 9 of the control unit 1 is in the zero state (00), the device input contains the last value fl of the boolean function of two variables, the delay elements 2 and 3 are stored respectively. correspondingly, f and f ,, and the delay element 2 contains fg 0 h, f, in its first discharge and fg ® h, f in the second. In the first and second. The bits of delay element 32 are the results of processing the truth vector of the previous Boolean function f ® iS, respectively. The zero potential from the output 13t of the control unit I is fed through the input of the element AND 5 to the input of the adder 8 modulo the arithmetic unit 4. Zero in the lowest row of counter 9 provides the potential for potential at output 14 of control unit 1 and, therefore, at the input of element H 6 of arithmetic unit 4 (. Thank you for this, the value f through input of element 6 comes to input of adder 8 modulo two The signal from the inverse output of the first bit of the counter 9 provides the passage of the value 1 ′ from the output of the trigger 10 through the input of the element 12; the output 15 of the control unit 1 to the input of the element 7 of the arithmetic unit 4 |, so that f from the input of the function converter is multiplied by h. doing em modulo two arithmetic block 4. Therefore, at the output of the arithmetic block 4, we have fj® h fj. This quantity is multiplied by the And 7 element of the rhymetrical block 4y by h and fed and the input of the modulo two 8, hg posS1 to the input of the element 7 from the trigger output through the input of the TL 12 element 15l output of the control unit 1 due to the presence of one potential at the nimepc output of the second discharge of the counter 9. The logical zero from the output 13 of the control unit 1 is fed through the input of the element 5 to the input of the adder 8 modulo two ifmeticheskogo unit 4h ,. Due to the potential of the logical zero at the direct output of the second discharge of the counter 9, we have a unit at the output 14, the control unit 1, which ensures that modulo two passes to the input of the adder 8 modulo II through the input of the And 6 element of the arithmetic unit 4 delay element 2. At the output of the device, we have (f & n- (f. i) hf). At the end of the cycle, the delay elements and 3f are stored fj and fn, respectively. In the first and second bits of the delay element 2 we have f h hj f and. fo & li, as well as f @ h. 2 h 2. ® t the first and second bits of the delay element 3 In the second cycle, the first value f of the new Boolean function receives the ira input of the function-optical converter. Due to the presence of a unit in the lower category of counter 9 at the output of the AND-NOT AND element, we have the value of h. which output 14 (control unit 1 enters the input of the element 6, where it is multiplied by the value fj from the output of the delay element 2f. The result is fed to the input of the hcgklätlgcha pn R nnvmn pp I pngll tmirg. 4. To the other input of the adder 8 modulo two through the input of the element And 5 from the output of the delay element 3. The value of f. At the corresponding input of the accumulator 8 modulo two arithmetic unit 4, we have a zero coming from the inverse output of the first discharge of the counter 9 through the input elem nta I 12 /. exit 15, control unit 1 and input element And 7. As a result, the output of the arithmetic unit 4, floor, / tea value Since in the second cycle, as well as in the first, the second discharge of counter 9 contains 1gul, the modulo inputs to the inputs of the adder 8. two arithmetic unit 4 receive the corresponding zero, the signal from the output of the delay element 2 2. - fg, ® h, f, and the output from the first channel - fj ® h. which is supplied from the output of the trigger 102 through the input of the electronic 12 and the output of the 15 h block up. 1. At the output of the device in the second cycle, we have (fgiSh, f,) ® ® 30. At the end of the second cycle, the values of and f are filled into the delay elements 2, and 3 |. respectively. The delay element 2 contains f @ h, fj in its first category and fn® h. f / in the second. In the first and in the third discharge of the delay element 3 we have fQ (, and fg®h f., Respectively. In the third cycle, the contents of the counter 9 are (10). Therefore, at the outputs 13, 14 ", 15 15 and 132. 1, and pyl, 14-, J of control device 1 are 0.1 h and 1, h 0, respectively. The adder 8 modulo two arithmetic unit 4 adds the value of f from the output of delay 2 to the value of f ,, input pa functional converter, which is pre-multiplied by h by the element And 7. As a result, at the output of the arithmetic unit 4, we have foSh f. modulo two 8, the arithmetic unit 4 performs the summation of the values fQ®h f., and f from the outputs of the delay elements 3 and 22, respectively, and the value is pre-multiplied by h2 using the element And 6 of the arithmetic unit 4. Consequently, in the third cycle at the output of the functional converter, we have (f © h d) C / ir / x / g, and .J: (eb2 (f, ®h, fp. When going to the fourth cycle, delay elements 2, | and 3 are sent the values of f and f J, respectively. In the first bit of the delay element 22 we have, f ,, and in the second bit we are in the first and second bits of the delay 3 element and contain the values of f®h uch ... ... - l and J, respectively. In the fourth clock cycle, at the input of the function converter, the value f of the new Boolean function is present, and counter 9 contains (11). The unit potentials from the direct outputs of the counter 9 are fed through the outputs 131 and 13 of the device 1 to the inputs of the arithmetic units 4 and 4. Due to this modulo two arithmetic units 4 and 4 are fed to the inputs of the adders 8 and 4 . of the outputs of the elements of the top 3 and 22, respectively. At the outputs 14 and 14 of the control unit 1, we have the values of h and h, respectively, which are fed to the inputs of the elements And 6 of the arithmetic blocks 4 and 4 As a result, f and f from the outputs of the elements of Delay 2 and 2 are multiplied by h and b, respectively. elements And 6 and fed to the inputs of adders 8 modulo two arithmetic units 4 4 and 4 2- The signals of the logical zero from the inverse outputs of the counter 9 through the inputs

elements 2 and 12 are fed to the inputs 15 / and 15d of the control unit 1, and then through the inputs of the elements I 7 to the input of the adder 8 modulo two arithmetic blocks 4x and 4. Thus, in the fourth clock cycle at the outputs of the arithmetic blocks 4 and 4 we have the values R, f, and (fg® h) @ ®hp (f®li fj), respectively.

The technical and economic effect of using a functional converter is the ability to automate the process of finding for a given Boolean function and variables not only a single Zhegalkin polynomial in which all variables are not inverted, but also any of the 2 possible polynomials that differ from each other by inverting perimeters.

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Claims (1)

FUNCTIONAL CONVERTER containing the first group of η (2 is the conversion size) delay elements, η arithmetic blocks, and the ith (i = Tn) arithmetic block contains the first element And and the adder modulo two, the first input of which is connected to the output of the first element And, the first input of which is connected to the i-ro output of the delay element of the first group, the control unit containing a counter, the direct i-ro output (i = 1, n) of the discharge of which is connected to the second input of the first element And the i-ro arithmetic block, о which, in order to expand functionalities due to the implementation of the Zhegalkin polynomial of a given type, into which each variable enters directly or with inversion, the second group of η delay elements is introduced into the converter, the second and third elements And are introduced into the i-th arithmetic block, and η elements are entered into the control block And, η elements AND — NOT and η flip-flops, and in the i-th arithmetic block the second and third inputs of the adder modulo two are connected to the outputs of the second and third elements And, the first inputs of which are connected to the outputs, respectively about the i-ro element AND — NOT and the i-ro element AND of the control unit, the first inputs of which are connected to the output of the i-ro trigger of the control unit, the direct and inverse outputs of the i-ro discharge of the counter of the control unit are connected to the second inputs, respectively, of the i-ro element AND — NOT and i-ro of the AND element of the control unit, the adder output modulo · two j-ro (j = 1, n— 1) arithmetic units are connected to the second input of the third AND element (j + l) -ro of the arithmetic unit and the input (j + l) -ro delay element of the second group, the output of which is connected to the second input of the second element And (j + l) -ro arithmetic of the first block and the input (j + l) -ro of the delay element of the first group, the output of the adder modulo two of the ηth arithmetic block is the information output of the converter, the second input of the second element And the first arithmetic block is connected to the input of the first delay element of the first group and connected to the output of the first delay element of the second group, the input of which is connected to the second input of the third element And the first arithmetic block and is an information input of the Converter. 1 1140130 2