SU1126968A1 - Function generator - Google Patents

Abstract

The FUNCTIONAL TRANSMITTER containing the register of the highest bits of the argument, the register of the lower bits of the argument, four memory blocks, the first adder, the multiplication block, the division block and the result register, whose information input is connected to the output of the first adder, the output of the register of the highest bits of the argument is connected to The address inputs of the first and second memory blocks, BbtxoA, of the second memory block are connected to the input of a divisible division block, characterized in that, in order to increase speed, three intermediate ones are entered into it the register, the second and third adders and the synchronization unit, the first output of which is connected to the synchronization inputs of the first and second intermediate registers and the result register, the second output of the synchronization unit is connected to the synchronization inputs of the high and low bits of the argument and the third intermediate register, the output of the lower bits The argument argument is connected to the first input of the second adder and the information input of the second intermediate register, the output of which is connected to the first {input of the multiplication unit, in The second input and output of which are connected respectively to the output of the third and left input of the first adders, the output of the first memory block is connected to the second input of the second adder, the Outlet of which is connected to the input of the divider of the division unit whose output is connected to the information input of the third intermediate register, output which is connected to the first input of the third adder, the output of the register of the higher bits of the argument is connected to the information input of the first intermediate register, the output of which is connected to the address input 1m third and fourth storage units whose outputs are connected to kotork second inputs, respectively, of the first and third adders, registers information inputs MSB and lower bits of the argument rows respectively connected to inputs of senior and junior bits device argument.

Description

Jl3o6peTeHHe relates to computing technology and can, be used for instrumental realization of functions in specialized and universal speed (of first digital computers about

A device for logarithmization is known which contains the registers of the lower and higher bits. argument ,. three memory blocks, switch, oivfMaTor, result register 1j,

A disadvantage of the known device is the narrow class of peraaei ibK tasks.

The closest to the present is a functional converter containing a register mp: the 11 bits of the argument, the register of the higher bits of the argument connected to the address inputs of the first and second memory blocks, the output of which is connected to the input of the dividend division block, the multiplication block, the third and fourth a memory block, an adder, the output of which is connected to the input of the result register 2J.

The disadvantage of this device is the need for sequential use of division and multiply operations, which significantly reduces their performance.

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that the functional converter containing the register of the old bits of the argument, the register of the maximum bits of the argument, the four memory blocks, the first adder, the multiply HHHj block of the division and the result register, whose information input is connected to the output of the first adder, the output of the register the higher arrays of the argument are connected to the address inputs of the first and second memory blocks, the output of the second memory block is connected to the input of the divisible division block} three intermediate registers are added, and the second and third adders and the synchronization unit, the first output of which is connected to the synchronization inputs of the first and second intermediate registers and the result register, the second synchronization block code is connected to the inputs of the upper and lower bits of the argument and the third intermediate register, register register

The younger bits of the argument are connected to the first input of the second adder and the information input of the second intermediate register, the output of which is connected to the first input of the multiply block, the second input and output of which are connected respectively to the output of the third and first input of the first adders, the output of the first memory block is connected with the second input of the second adder, the output of which is connected to the input of the divider of the dividing unit, the output of which is connected to the information input of the third intermediate register, the output of which is connected to the first At the third cyNiMaTOpa input, the output of the high-order argument register is connected with the information input of the first intermediate register, the output of which is connected to the address inputs of the third and fourth memory blocks, the outputs of which are connected to the second inputs of the third and first adders, respectively; the low order bits of the argument are connected to the inputs of the high and low bits of the device argument, respectively

In the drawing, the same block diagram is shown, on the converter.

The functional converter contains a register of 1 higher bits of the argument, intermediate register 2, block 3 of memory, adder 4, register of 5 m-fallen bits of argument, intermediate register 6, block 7 of division, intermediate register 8, block 9 of memory, block 10 memory, adder 1 15, block 2 multiplying, adder 13, block 14 of memory, register 15 of the result, block 16 synchronization.

The calculation of the function values in the device is based on the following relationships.

Let the function F (K), be given, satisfy the condition F (x) 1 1, the values of the argument X be Y -disable binary code, and the values of the function Y-F (X) need to be entered with correct binary digits after the yyyy. We fix the value of the parameter K and divide the argument in the following way:

HgO, X ,,. Xj-O ... About V 6X-0,0 ..

About x

X „; yh

K-1-1

The calculations show that the value of the given function F (X) can be approximated by the expression: and (X) rF (Xj,) + 4X. (A (X (j) tB (Xo) / / (C (Xo) 44X)), (1) where the coefficients F (Xp), A (Xd), B (X (C (XQ)) depend only on the intermediate argument X, but do not depend on ik X and are defined as follows:) f / Xd) -F; (Ho) / F, (Xd), A (XO) B (X,) - f | (X) / FiHo), C (Ho) -F2 (Ho) / Fz (Ho) F (g) pChg) 11,, A. The value of the parameter K to get all the binary bits of the result P true is necessary to be taken from the expression: (pi +) / 41 tP, t))) Ch 2 (2) - F, and Oi, 2 2. The values of the coefficients T (Xd) A (X (), B (XQ), SCCD) is preliminarily calculated by the above formulas and stored at the corresponding addresses of the memory blocks of the device in question. The device works as follows. In the first cycle, the synchronization unit 16 forms, at the second run, the synchronization code C1, which supplies the control inputs of the register of the highest bits of the argument and the register of the five lower digits of the argument to which the code of the first argument is entered. The code of the high-order bits of the argument from the output of the register 1 of the high-order bits of the argument goes to the address inputs of the first 3 and second 9 memory blocks. At the output of the first memory block, the value C (X) is formed, which is fed to the input of the second adder 4. At the output of the second sum jpa 4, the value C (X) t lX is formed, which is fed to the input of the divider of the division block 7. The VSHO code) from the output of the memory block 9 is fed to the input of the dividend dividing block 7, at the output of which the value of the intermediate result F, (x) (. Xo) / C (Ho 6X) is formed. In the second cycle of operation, the synchronization unit 16 generates at the first 684 output a synchronization signal C2, which is fed to the control inputs, register 2 and register 6, while the first argument code rewrites from the output of register 1 the higher bits of the argument to the intermediate register 2 and from the register output 5 lower bits of the argument to intermediate register 6. The code X of the high bits of the argument from the output of intermediate register 2 is fed to the address inputs of the third 10 and fourth 14 blocks. At the same time, the value of A (AO) is formed at the output of the third memory block 10, and the value of F (XQ) is output at the output of the fourth memory block 14. In the third cycle of operation of the device, the synchronization unit 16 generates the next signal of the C1 series, under control of which the second argument code is entered into register 1 of the higher order bits of the argument and register of the 5 lower order bits of the argument. At the same time, the intermediate result code F | (X) is entered into the intermediate register 8, which then enters the input of the third adder 11, at the other input of which the code A () (o) is already located. From the output of the third adder 11, the sum (A (XO) A - P (() 1) goes to the first input of multiplication unit 12, on the second input of which is code iX. The product HX (A (Xo) 4 F (X)) is summed the value of F (Xo) on the first adder .13, the output of which forms the result value F (X) F (Xo) 4AX- (A ((o) t F (X)). In the fourth cycle, the synchronization unit 16 generates a signal C2, under whose control the code of the second argument is entered into intermediate registers 2 and 6. At the same time, the result code F (X) is transmitted from the output of the first adder 13 to the result register 15. Subsequently, Playback function with spinning cycle is repeated as described for the previous cycles of operation. Thus, the performance of the device is approximately 1.5 times vsh1e performance of the prototype device.

Claims (1)

FUNCTIONAL CONVERTER containing the register of the highest bits of the argument, the register of the least significant bits of the argument, four memory blocks, the first adder, the multiplication block, the division block and the register of the result, the information input of which is connected to the output of the first adder, the output of the register of the highest bits of the argument is connected to the address inputs of the first and of the second memory blocks, the output of the second memory block is connected to the input of the divisible division block, characterized in that, in order to increase performance, three intermediate registers are introduced into it tra, second and third adders and a synchronization block, the first output of which is connected to the synchronization inputs of the first and second intermediate registers and the result register, the second output of the synchronization block is connected to the synchronization inputs of the registers of the upper and lower bits of the argument and the third intermediate register, the output of the register of the least significant bits argument is connected to the first input of the second adder and the information input of the second intermediate register, the output of which is connected to the first input of the multiplication unit, the second input and Exit of which are connected respectively with the output of the third and the first input of the first adder, the output of the first memory block. th is connected to the second input of the second <g adder, the output of which is connected to the input of the divider of the division unit, the output of which is connected to the information input of the third intermediate register, the output of which is connected to the first input of the third adder, the output of the register of the upper bits of the argument is connected to the information input of the first intermediate register the output of which is connected to the address inputs of the third and fourth memory blocks, the outputs of which are connected to the second inputs of the third and first adders, respectively, information nye input registers MSBs and LSBs of the argument respectively connected to the inputs of senior and junior device discharges argument.