SU1132341A1 - Polyfunctional flip-flop - Google Patents

Abstract

1. MULTIFUNCTIONAL TRIGGER, containing the first clock bus and six NAND elements, the outputs of the first, second, third, and fourth. In addition, the fifth and sixth elements of the NAND are connected respectively to the first inputs of the second, first, fourth, third, sixth and fifth elements of the NAND, the outputs of the second, fourth and sixth elements of the NAND are respectively connected to the second inputs of the sixth, n of the first and third elements of the NAND, the first clock bus is connected to the second input of the fourth and to the third input of the fifth elements of the NAND, characterized in that, in order to expand the functionality, the seventh, eighth, ninth, tenth eleventh The thirteenth, and thirteenth IS-NE elements, three delay elements, eleven control buses, and a second clock bus, which are connected to the first inputs of the eleventh and twelfth AND-NOT elements, whose outputs are connected to the second inputs of the first and second AND-NOT elements, respectively. respectively, with the first and second inputs of the tenth AND-NB element and connected respectively with the first and second inputs of the eighth AND-NOT element, the output of which is connected to the first input of the seventh AND-NOT element and to the input of the first delay element, output One of which is connected to the first input of the ninth NAND element, the output of which is connected to the third input. the tenth element of AND-NOT and from the second (the input of the seventh element of the IS-NOT, the output of which is connected to the third input of the eighth element of the AND-NO the thirteenth element AND-NOT, whose output is connected to the fourth input of the fifth element. AND-NOT and to the third input of the third element AND-NOT, the first output of which is connected to the second input of the eleventh AND-NOT element, the output of the fourth element AND-NOT connected with the third entrance of the ninth and the second entrance of the twelfth element AND NOT, the outputs of the second and first ND 9 liik cops AND-NOT are connected respectively to the inputs of the second and third delay elements, the outputs of which are connected respectively to the third inputs of the eleventh and twelfth elements AND-NOT, the fourth input of the last of which is connected to the output of the sixth element AND- NOT, first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh control buses are connected respectively to the third input of the seventh, to the fourth input of the eighth, to the third input of the first, to the third the entrance of the second, with the fourth input of the ninth, with p of the

Description

the input of the twelfth, with the second input of the thirteenth, with the fourth input of the third, with the third input of the fourth, with the third input of the sixth and with the fourth input of the second element, the eleventh control bus is connected to the fourth input of the sixth element I-YE.

2. The trigger of claim 1, of which there is also the fact that each delay element contains, in series, 2 n I-NOT elements (where n 0, 2 ,, ...), the input, the first and the output of the last of which is connected respectively to the input and output of the delay element.

The invention relates to a pulse technique and can be used in devices for various purposes as a counting trigger, a pulse frequency doubler, a static register, a synchronization device, an input, a single pulse is subtracted from a series, and the pulses are generated by the single and zero differences of the input signal. A device for isolating (shaping) a single pulse from a pulse sequence is known, comprising six AND-NOT elements, two input and output buses lj. The specified device implements one function, which limits its scope. A device is known that contains a clock bus and six AND-NES outputs of the first, second, third, fourth, fifth, and sixth elements AND-NOT are connected to the first inputs of the second, first, fourth, third, sixth, and fifth elements, respectively. NOT, the outputs of the second, fourth and sixth elements AND-NOT are connected respectively to the second inputs of the sixth, fifth and third elements AND-NOT, the clock bus is connected to the second input of the fourth and to the third input of the fifth elements AND-NOT. This device implements the functions of memory, counting, frequency division and pulse distribution into two 2J channels. However, despite its functional capabilities, it does not implement the function of frequency doubling, pulse synchronization, single pulse (including the first) selection from the sequence , subtracting a pulse from it, forming pulses on a single and zero difference of the selected (subtracted) pulse, shift, autonomous operation of the memory elements and the pulse distribution node into two channels, which reduces the functional POSSIBILITY known device. . The purpose of the invention is to expand the functionality of the trigger. This goal is achieved by the fact that in a multifunctional trigger containing the first clock bus and six AND-NOT elements, the outputs of the first, second, third, fourth, fifth and sixth AND-NOT elements are connected respectively to the first inputs of the second, first, fourth, third , the sixth and fifth elements of the NAND, the outputs of the second, fourth and sixth elements of the NAND are connected respectively to the second inputs of the sixth, fifth and third elements of the NAND, the first clock bus is connected to the second input of the fourth and the third input of the fifthof the elements AND-NOT, the seventh, eighth, ninth, ten, eleventh, twelfth, thirteenth AND-NOT elements, three delay elements, eleven control buses and the second clock bus are introduced, which are connected to the first inputs of the eleventh and twelfth AND elements NOT, the outputs of which are connected respectively to the second inputs of the first and second elements AND-NOT, are connected respectively to the first and second inputs of the tenth element AND-NOT and are connected respectively to the first and second inputs of the eighth element AND-NOT, the output of which is connected to ervm input of the seventh AND-NO element and to the input of the first delay element, the output of which

connected to the first input of the ninth element NAND, the output of which is connected to the third input of the tenth element of the NAND and to the second input of the seventh element of the NAND, the output of which is connected to the third input of the eighth element of the NAND, output of the fifth element The NAND is connected to the second input of the ninth element NAND and to the first input of the thirteenth element NAND, the output of which is connected to the fourth input of the 5th element NAND, and to the third input of the third element I N the output of which is connected to the second input of the eleventh element is NOT the output of the fourth element AND-NOT connected to the third input of the ninth and second input of the twelfth elements AND-NOT, the outputs of the second and first elements AND-NOT connected respectively to the inputs of the second and third delay elements, the outputs of which are connected respectively to the third inputs of the eleventh and twelfth elements AND-NOT , the fourth input of the last of which is connected to the output of the sixth element NAND, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh control bus are connected respectively to the third input m seventh, with the fourth entrance of the eighth, with the third exit of the first, with the third entrance of the second, with the fourth entrance of the ninth, with the fifth entrance of the twelfth, with the third entrance of the thirteenth, with the fourth entrance of the third, with the third input of the fourth, with the third entrance of the sixth and The eleventh control bus is connected to the fourth input of the second NAND element and the fourth input of the sixth NAND element.

In the multifunctional trigger, each of the delay elements contains 2 n I-NOT elements serially connected (where n 0, 1, 2), the input of the first and the output of the last of which are connected respectively to the input and output of the delay element.

FIG. 1 is a diagram of a multifunctional trigger; FIG. 2 timing diagrams of voltages at the inputs and outputs.

The multifunction trigger in FIG. 1 contains thirteen elements 1-13 AND-NOT, three elements 14, 15 and 16 delays, eleven tires 17-27

office, eleven weekend

tires 28-38 and two clock tires 39 and 40.

The outputs of elements 1-6 AND-NOT are connected respectively with the first inputs of elements 2,1,4,3,6 and 5 AND-NOT, the outputs of elements 2,4,6 AND-NOT are connected respectively with the second inputs of elements 6.5 and 3 AND -NO, the clock bus 39 is connected to the second input of the element 4I-NOT and to the third input of the element 5I-NOT, the clock bus 40 is connected to the first inputs of the elements 11.12 I-NN, the outputs of which are connected respectively to the second inputs of the elements 1.2 And -NO, are connected respectively with the first and second inputs of the element 10 AND-NOT and are connected respectively with the first and second inputs element 8 AND-NOT, the output of which is connected to the first input of the element; 7 AND-NOT and to the input of the delay element 14, the output of which is connected to the first input of the 9 AND-NOT element, the output of which is connected to the third input of the 10 AND-NOT element and the second input element 7 AND-NOT, the output of which is connected to the third input of the element 8 AND-NOT, the output of the element 5I-NOT connected to the second input of the element 8 AND-NOT and the first input of the element 13 AND-NOT, the output of which is connected to the fourth input element 5I-NOT and with the third input element 3 AND-NOT, the output of which is connected to the second input element 11 AND-NOT, the output of element 4 is AND-NOT connected to the third input of element 9 I.-NOT and to the second input of element 12 I-NOT, the outputs of elements 2.1 and IS-NOT are connected respectively to the inputs of elements 15, 16 of the delay whose outputs are connected respectively to the third the inputs of the elements 11, 12 AND-NOT, the fourth input of the element 13INE is connected to the output of the element 6 AND-NOT, tires 17-27 of the gravity are connected respectively to the third input of the element 7 AND-NOT, to the fourth input of the element 8 AND-NOT, to the third the input element 1 AND-NOT, with the third input element 2 AND-NOT, with the fourth input element 9 AND-NOT, with tm input member 12 AND-NB with vtorm input elements; This 13 AND-NOT, with the fourth input of the element 3 AND-NOT, with the third input of the element 4 AND-NOT, with the third input of the element 6I-NOT, and with the fourth input of the element 2I-NOT, the control bus 27 is connected to the fourth input of the element. 5s 11 and 6 AND-NOT, the output buses 28-38 are connected respectively to the outputs of the elements 1, 2,3,4,5,7,8,1,1,1 1, 10,9 AND-NOT Fig. 2 shows diagrams of 4145 signals respectively on: ah 39 (40), at the outputs of elements 11, 9, 12, 10 AND-NOT. -Trigger works in the following modes. The binary counting trigger mode includes elements 1-6, 11, 12 INE, delay elements 15, 16 at ta О, their respective communications and Rizhgo tires are set by combining clock tires 39 40, level O on tires 21, 23 and starting 1 on tires 19 20, 22, 24, 25, 26, 27. Depending on the initial state of the trigger, the clock pulse switches elements 5, 12 or 4.11, then elements 2, or 1, the level O at the output of one of which through delay element 16 (15) switches elements 12 or 11 again. As a result, on tires 35, 36 and 37 pulses form on the leading edge (one Nome drop) clock pulse, the busbar 31, 32 - the inverted clock pulse, and on the tires 28, 29 - output of signals of equal duration period. The mode of the pulse frequency doubler includes all the elements corresponding to them and the bus, which is set by the counting trigger mode, initial installation of elements 7.8 (1, O) and level 1 on tires 17 18 and 21. Formation of pulses on a single differential of clock pulses is similar. At the same time, O at the inputs of elements 11, 12 switches elements 10, 8 and 7. After the clock pulse is applied, one of elements 4.5, elements 9,7,8 and 10, and after tj introduced by element 14, elements 9 and 10 As a result, the formation of pulses by zero differential clock pulses occurs, as well as a doubling of the pulse frequency (Fig. 2). The mode of the pulse synchronization device, including elements 1-6, 11, 12 and delay elements 15, 16 at t 5. O, their respective connections and tires. The mode is set in the same way as the counting trigger mode, O being fed to bus 22, and clock pulses to clock buses, and asynchronous pulses to bus 27, Before an asynchronous pulse, O from bus 27 provides the periodic response of element 5. The effect of an asynchronous pulse ( 1) provides switching element 6 after the impact of the sync pulse and switching the following sync pulse elements 4, 11, 1, 2, 6, 10, after t, introduced by element 15 - elements 11, 10, after the influence of the sync pulse 4,3, and after asi synchronous elements 2.1. In this case, a synchronized pulse is formed on the bus 31, and a pulse on the bus 36 is triggered by a single clock pulse. The mode of the device for extracting a single pulse (including the first one) and subtracting it from the pulse sequence, including elements 1-6, 11, 12, delay elements 15, 16 at t-: 5- O, their respective connections and buses. This mode differs from the synchronization mode by bus 27 control. P | vim fo1 1 Pulse impulse on single and zero differences of impulse (synchronized) pulse, including all elements connected to the bus, are implemented similarly to the frequency doubling mode with the only difference that 27 carry the control signal, and bus 22. The mode of three-digit static register on -triggers performed respectively on elements 1 and 2, Zi4, 7 and 8, including all elements, connections and buses. The mode is set by the O Nashin level 21, 23, 26, 40, level 1 on the tires 27, 39 and thus divides the indicated triggers. The pins 17-20, 24, 25 (39) serve as ff, 5 inputs. The mode of the pulse distributor on two channels, including elements 3-6, 13, and the mode of a two-bit static register on RS triggers, including other elements, their corresponding connections and buses. The mode is set by level O on tires 21, 26, 40, level 1 on tires 24, 25, 27 and thus separates the indicated groups of elements. Input

pulses are fed to bus 39, the distribution control signal is sent to loop 23. Depending on the control signal, input pulses pass to bus 31 or 32, buses 17–20 serve as R, 5 inputs of the register.

The cell mode (bit) of the shift register, including the elements 1-6, 11, 12, 13, 15, 16 at t 5-O and the Yb-flip-flop mode, including the remaining elements at t J 0.

The mode set by the connection of tires 19, 31 and 20, 32, level O on tires 21, 26, 40, level 1 on tires 24, 25,

27 and the very same divide the indicated groups of elements. The bus 23 is the input information bus, the bus 28 is the output information bus, and the clock pulses are supplied to the bus 39.

In the case of t O, the formation of short pulses of duration 3.

Thus, this trigger, unlike the prototype, has broader functionality and can replace a whole range of specialized devices.

and

and

and

Tj and

2.2

Claims (2)

1. MULTIFUNCTIONAL TRIGGER containing the first clock bus and six AND-NOT elements, outputs of the first, second, third, fourth, fifth and sixth AND-NOT elements connected to the first inputs of the second, first, fourth, third, sixth and fifth elements, respectively AND NOT, the outputs of the second, fourth and sixth AND-NOT elements are connected respectively to the second inputs of the sixth, fifth and third AND-NOT elements, the first clock bus is connected to the second input of the fourth and third input of the fifth AND-NOT elements, characterized in what, In order to expand the functionality, it introduced the seventh, eighth, ninth, tenth, eleventh, twelfth,> thirteenth AND elements, three delay elements, eleven control buses and a second clock bus, which is connected to the first inputs of the eleventh and twelfth elements AND NOT, the outputs of which are connected respectively to the second inputs of the first and second AND-NOT elements, are connected respectively to the first and second inputs of the tenth AND-NOT element A and are connected respectively with the first and second inputs of the eighth AND-NOT element, the output of which is connected with the first input of the seventh AND-element and with the input of the first delay element, the output of which is connected to the first input of the ninth AND-NOT element, the output of which is connected to third entrance. of the tenth AND-NOT element and with the second input of the seventh AND-NOT element, the output of which is connected to the third input of the eighth AND-NOT element, the output of the fifth AND-NOT element is connected to the second input of the ninth AND-NOT element and with the first input of the thirteenth AND element NOT, § whose output is connected to the fourth input of the fifth AND-NOT element and see the third input of the third AND-NOT element ₍ whose output is connected to the second input of the eleventh AND-NOT element, the output of the fourth AND — NOT element is connected to the third input of the ninth and the second input of the twelfth elements of INE, out the odes of the second and first AND-NOT elements are connected respectively to the inputs of the second and third delay elements, the outputs of which are connected respectively to the third inputs of the eleventh and twelfth AND-NOT elements, the fourth input of the last of which is connected to the output of the sixth AND-NOT element, the first, second third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh control buses are connected respectively to the third input of the seventh, with the fourth input of the eighth, with the third input of the first, with the third input of the second, the fourth input of the ninth, with the five input of the twelfth, with the second input of the thirteenth, with the fourth input of the third, with the third input of the fourth, with the third input of the sixth and with the fourth input of the second element AND NOT, the eleventh control bus is connected to the fourth input of the sixth element AND -NOT. 2. The trigger on π. 1, with the fact that each delay element contains 2 η AND-NOT elements connected in series (where n = 0,1,2 ,,.), The input of the first and the output of the last which are connected respectively to the input and output of the delay element.