SU1120503A1 - Device for making diagnostics of multichannel redundant systems - Google Patents

Abstract

1. A DEVICE FOR DIAGNOSTING MULTI-CHANNEL RESERVED SYSTEMS, which contains, by the number of channels, P1-discharge buses, which are the first inputs of the device, and by the number of bits of kh-discharge coincidence blocks, connected to the output of the device, the first input to the output of the first element OR, the second inputs of the analysis unit. are connected to the outputs of the counter, the input of which is connected to the second input of the device, the first inputs of each matching unit are connected to the buses of the same name of all channels the outputs of the matching blocks are connected to the inputs of the first OR element, which is so that, in order to increase reliability and simplify the device, it contains a switching unit and an inverter, and the second device input is directly and through an inverter connected to the second single inputs of the coincident block and the control inputs of the switching unit, the information inputs of which are connected to the counter outputs of the counter, and the transducers with the third inputs of each coincidence block. 2. The device according to Claim 1, which is based on the fact that the switching unit contains (n-1) switching node, each of which contains four elements AND and the second and third elements OR, the first inputs of the First and second elements AND are connected to the right information inputs, and the first inputs of the third and fourth I elements - with inverse information inputs of the corresponding bit of the switching unit, the second turns of the first and fourth AND elements are connected to the first, and the second inputs of the second and third elements TOB AND - with the second control inputs i mi block ommutation, the inputs of the second element OR are connected to the outputs 1C: the first and third elements AND, and the inputs of the third element OR - from the output. O1 of the second and fourth elements of AND, the outputs of the second and third elements OR are the outputs of the corresponding bit of the switching unit. 3. The device according to Claim 1, stating that the analysis block contains a decoder and a group of valves, the direct inputs of which are connected to the corresponding outputs of the decoder, the second input - with the second input of the unit, and the output - with the output of the block, the decoder input i connected to the first input of the analysis block.

Description

The invention relates to digital computing and can be used in multichannel redundant systems for diagnosing their condition and identifying the source of error. A device is known that contains the majority elements and allows to allocate a reliable result according to the majority principle in the multichannel redundant system et1l. The disadvantage of this device is the inability to determine the source of unreliable information. It is also known a device comprising buses A, B, C, which are the inputs of the device, which are directly and through the elements NOT connected to the inputs of the AND elements, the outputs of the AND elements connected to the inputs of the OR elements, the outputs of the OR elements are the outputs of the device. The elements NOT, AND, OR, together with their connections, form an analysis block that implements the logical FLZ functions ABC V ABC, ABC V V ABC, ABCV ABC. This device allows you to localize the source of error in a three-channel redundant P2 system. The disadvantage of this device is the low reliability associated with the complexity of the device. This is due to the fact that with an increase in the number of bits, the number of analysis blocks, which are relatively complex nodes, increases by the same amount. The closest in technical essence to the present invention is a device containing, by the number of channels, nk -drash buses, which are the first inputs of the device, an analysis unit, the output of which is the output of the device, Kg -discmatching units, the OR element and p - a bit counter, the input of which is connected to the second input of the device, and the outputs are connected to the first inputs of the matching blocks and the first inputs of the analysis block, the second inputs of each - matching block are connected to the outputs of the same name of all channels, the outputs of the matching blocks connected to the inputs of the OR element, the output of which is connected to the second input of the analysis unit. This device allows you to determine the source of unreliable information in the n-channel redundant system. 03J A disadvantage of the prior art is the low reliability associated with the complexity of the device. The purpose of the invention is to increase the reliability and simplification of the device. To achieve this goal, a device containing, by the number of channels, hV -disable busses, which are the first inputs of the device, and according to the number of bits, kn -disk matches, (n-lj-bit counter, the analysis unit, the output of which is connected to the device output, the first input - with the output of the first element OR, the second inputs of the analysis unit are connected to the outputs of the counter, whose input is connected to the second input of the device, the first inputs of each block of the match are connected to the busses. ina with inputs of the first element OR, a switching unit and inverters), the second input of the device directly and through the inverter connections to the second inputs of each block and the control inputs of the switching unit, whose information fields are connected to the outputs of the counter, and the outputs with the third blocks of each block of coincidence. The switching unit contains (and-1) switching node, each of which contains four elements And the second and third, elements OR, the first inputs ;: the first and second elements And are connected to the direct information inputs, and the first inputs of the third and fourth elements And - with inverse information inputs of the corresponding discharge of the switching unit, the second inputs of the first and fourth elements I are connected to the first, and the second inputs of the second and third elements I - with the second control inputs of the switching locus, the inputs of the second element OR are connected to the outputs of the first and third elements are AND, and the inputs of the third element OR are with the outputs of the second and fourth elements AND, the outputs of the second and third elements OR are the outputs of the corresponding bit of the switching unit. The analysis block contains a decoder and a group of valves, the direct inputs of which are connected to the corresponding. the outputs of the decoder, the second input with the second input of the block, and the output with the output of the block, the input of the decoder.

The rator is connected to the first input of the analysis unit.

The principle underlying the invention will be considered on the example of diagnosing five-channel

Combination A B C D E

1120503, 4

(p 5) of one-bit systems A, B, C, D, E. It is easy to notice that two mutually inverse 5 code combinations correspond to the same faults each (see table).

situations

Obviously, to diagnose the state of the system, it is sufficient to decipher the combinations 1,3,5, ..., 31, and the common feature in these combi | Inactions are the presence of zero in the discharge corresponding to channel A.

Thus, all possible 32 code combinations will be supplied to the input of the matching blocks, as is the case in the prototype, and only odd ones to the input of the analysis block. This makes it possible to reduce the counter size by one unit and significantly simplify the decoder the composition of the analysis unit, since the number of diagnosed situations has decreased from 2 to 22.

Figure 1 shows the structural diagram of the device; figure 2 - switching unit; in FIG. 3, a match block.

The device contains (h-1) -diameter, switch 1, coincidence unit 2, element OR 3, decoder 4, valve group 5, analysis unit 6, inverter 7, switching unit 8, outputs 9

blocks of coincidence, the resolution signal 10 for a group of gates 5, input k-discharge buses 11 from channels, input 12 of the device from a pulse generator, switching unit 13.

Switching unit 8 contains a single-switching unit 13, an AND 14 element, an OR 15 element, direct and inverse inputs 16 from counter 1, direct and inverse outputs 17 of the switching unit, control inputs 18 of the switching unit.

Block 2 matches the element And 19, the element OR 20, the element And 21, the element NOT 22 and the circuit 23 of the match one bit.

Counter 1 is intended for the sequential enumeration of all possible situations in one bit of the {l-1 | -L channel redundant system. The counter has direct and inverse outputs; its state changes when the input signal transitions from 1 to O.

Block 2 of the match is designed to compare the n-bit code from the same-named bits of all channels with the second and third inputs, and the task. signal 9 if they match. Element Ш1И 3 ensures the output of signal 10 in the presence of at least one signal. The decoder 4 is designed to form an error signal corresponding to the current code on the counter Dp to simplify the decoder to its input are fed direct and inverse codes. The outputs of the decoder are assigned values in accordance with the accepted ideology of assessment, situations. For example, for the LBSSE system (see table), the code 0000 is assigned the value of All channels are OK, the ORH code is defective. Channels A and B are faulty, and code 1111 is faulty. Channel A. is used to transmit the error signal from the decoder 4 to the input of the device 10 resolutions. Inverter .7 is designed to invert the input signal of 12. block 8 commutating and is designed to feed to the input of block 2 a direct or inverse code from counter 1, depending on the control signal. When a single signal arrives at the first (second) control input 18, the code from the direct outputs of counter 1 goes to the forward (inverse outputs of switching unit 8), and from the inverse outputs of counter 1 to the inverse (direct) outputs of block 8 The device works as follows: Let counter 1 be reset in the initial state. Codes from n channels to be diagnosed are fed to n input k-bit buses 11. At the same time, the values of the same-named bits of all channels and these values do not change for gender The first cycle of the counter account 1. The zero signal from the generator, pulses, pass through the inverter 7, is fed to the control input of the switching unit 8 and ensures that the direct code from the counter 1 is transmitted to its output. with one, nominal sizes of all n channels, to the third input - direct and inverse (l-1 | -discharge code from switching unit 8, and to the second input of block 2 coincidence, direct and inverse signals from input 12 , performs the function of the n-th compared bit. Thus, from the switching unit 8 and the input 12 to the input of the unit 2,000. “- o. match the code and its inversion. If in any discharge of the diagnosed system there are zeroes in all channels, then at the output of the corresponding block 2, the signal 9, which passed through the element OR 3, opens valves 5. At the same time, the code j30.o ,, -., .. i: .i. and its inversion from counter 1 is fed to the input of the decoder 4. As a result, at its output there is a single signal indicating the proper operation of all channels. This signal will go to the output of the analysis unit 6, as the group of valves 5 is open. The signal will then go into one state. The state of counter 1 will not change, and therefore the same output of the decoder 4 will be in the excited state. The signal will go to the second control input of the switching unit 8, resulting in its direct outputs code . .00 ... oh,. and -1 on inverse - -j. A code will be given to the direct inputs of blocks 2 of the match, and a code will be given to the inverse ones. in case of coincidence, code drops, signal 10 will open a group of gates and a signal on the proper operation of all channels will go to the output of the device. The transition of the signal from one state to zero will result in the addition of one to the contents of counter 1 — it will go to the state 00 ... 01. At the same time, the zero signal will open the transfer of direct codes from counter 1 to the direct inputs of the coincidence unit 2, inverse - on inverse. The direct inputs will be OS. o CODE, which in the ABCDE five-channel system corresponds to the failure of the E channel. If such a code combination occurs in any bit, then signals 9 and 10 will provide the output of the device with the corresponding signal from the decoder 4. After the signal from input 12 is switched to one state, the direct inputs of the previous one will be sent to the direct inputs of the blocks, Namely, 11 ... 10, which also contributes to the failure of the channel B. In the future, all code combinations that may occur in the same bits of the redundant systems will be sequentially transferred, with codes corresponding to faults of one the same channel (s) will appear one after the other at the inputs of blocks 2, coinciding with zero and one states of the signal from input 12. Note that the last two combinations will be 01 ... -f and; to ... 0, which corresponds to the failure of the channel f. Let us estimate the depth of troubleshooting. The number of the faulty channel is determined by the output from analysis block 6, the bit in which 38 an error occurred can be determined by the number of the match block 2, which currently had an output signal 9; and the nature of the error is determined by the value of the unmatched bit in the faulty channel. Thus, the introduced elements and their connections provide for the detection of an irregular canal, and the device is clogged by reducing the hardware costs for the analysis unit. This is due to the fact that in a known device an n-rand counter was used, and in the proposed one, a (n-1) -disable counter and, accordingly, a decoder 2 code combination, and not 2 as in a known device.

FIG. 2 9

Claims (3)

1. DEVICE FOR DIAGNOSIS OF MULTI-CHANNEL RESERVED SYSTEMS, containing, by the number of channels η to -bit buses, which are the first inputs of the device, and by the number of bits of kh -bit matching blocks, (p-1) -bit counter, the analysis unit, the output of which is connected to the output of the device, the first input - with the output of the first OR element, the second inputs of the analysis unit. connected to the outputs of the counter, the input of which is connected to the second input of the device, the first inputs of each matching unit are connected to the buses of the same category of all channels, the outputs of the coincidence blocks are connected to the inputs of the first OR element, and this means that, in order to improve reliability and simplify the device, it contains a switching unit and an inverter, and the second: second input of the device directly and through the inverter connected to the second inputs of each matching block and to the control inputs of the switching block, the information inputs of which are connected to the outputs of the counter, and the outputs are connected to the third inputs of each matching block. 2. The device according to claim 1, wherein the switching unit comprises (n-1) a switching unit, each of which contains four AND elements and a second and third OR element, the first inputs of the first and second elements AND are connected by straight lines information inputs, and the first inputs of the third and fourth elements And with inverse information inputs of the corresponding discharge of the switching unit, the second (inputs of the first and fourth elements And connected to the first, and the second inputs of the second and third elements And - with the second control inputs- ( block com mutations, the inputs of the second OR element are connected to the outputs of the first and third AND elements, and the inputs of the third OR element are with the outputs of the second and fourth AND elements, the outputs of the second and third OR elements are outputs of the corresponding discharge of the switching unit. 3. The device according to claim 1, wherein the analysis unit contains a decoder and a group of valves, the direct inputs of which are connected to the corresponding outputs of the decoder, the second input to the second input of the unit, and the output to the output of the unit, the decoder input is connected ίwith the first input of the analysis unit. SU „..1120503