SU1120396A1 - Device for coding digital information by modified frequency modulation method - Google Patents

Abstract

CODING DEVICE FOR DIGITAL INFORMATION BY MODIFIED FREQUENCY MODULES, containing a block of clock pulses, the first code of which is connected to a synchronous input of the first register, information input connected to the input bus; This is due to the fact that, for the purpose of noBbnueHiiq interference immunity, the block bc: of the pulses is complete in the form of a series connection: b of the generator of the sync of pulses and the second countable trigger, whose outputs are It is the second and the first outputs of the sync pulses block, and the second register and the EXCLUSIVE Ifflli element are inserted into the device, connected between the output of the first register and the information input of the second register of the synchronization input of the connected S with the second output of the sync pulse block, the first output of which is connected to another input of the SCP element; PEER 1, the second register code is connected to the input of the first counting trigger,

Description

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. Invention relate; Our devices (memories) are used in magnetic; : j: -; - ii;: - from ki ZOR for koloto5a 1p z anvrch n ::, -, -i digital format: The device of digital information is known method :: ;; frequency mod. h) containing connected opra; way with nhrogsnsog) imp; register, switch, and disadvantage; this one is his case of use with the closest technical essence to the invention of the digital coding method using the method number-M, sodede ;; synchro-generator; -I: pz dzos,: 7th output of which is connected; en r tg;: o1 histra and the first input of the second input of which is connected with an output output of sync. c-rato) .-; u n: i-: y of the second tritger pkkd oczn; i register, and the counting input with: oadine: with the first output sync mode: imEulsus, intrusion code; trigger connect with the third input ;; ; KONMYTaTopa fourth input -.o :: r: ir is connected to the register output. The disadvantage of the known ...: ..., .. .. is its complexity from 3 to 3-ul-1. with the need to have a sss-sgl: who is the commutator. and np-tg .-:., - - in the output signal of the signal of the r-o-.k-xi, arising from the delays of the sc, lv in logical el-mental--r -t -: - - - -. -, .. -. the operation of the device and) inode; g; to the necessity is complicated;: cx; :: h: .1 - of the device and unnecessary annap; v;:; b: ii.,: The purpose of the invention is 5; gc: ;; roiiir interference suppression and device - Set a goal .. ih: ;; because of the fact that the device has the code ;; - gp digital information method i: - {0;:, I1: c the frequency module ;; a block of sync pulses, the output of which is connected to the C: :: clock input of the first (information input to; input to the input bus, the first account is connected to the output) c; ::; series-connected generator Cynxy pgyJTI, owl and the second counting trigger or i pwei i CHPUi, | gJII, gf 1 g 1 g f i i i, I. ,, og - ij 14 and -yyc, i,, pi ii - ji ii nn su ,, ijj Moreover, the proposed circuit design of the digital information encoding device using the f4M method makes it possible to use a simpler than the known sync pulses divide the frequency by two, for example, by a trigger, as in the proposed scheme, is much simpler than forming two mutually

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Thus, the invention allows to significantly simplify the design and increase the reliability of the operation of the device for encoding digital information in multi-speed magnetic recording devices without its alterations and modifications.

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Claims (1)

DIGITAL INFORMATION CODING DEVICE BY METHOD OF MODIFIED FREQUENCY MODULATION, containing a block of clock pulses. the first output of which is connected to the synchronizing input of the first register, the information input connected to the input bus, the first counting trigger, the output connected to the output bus, due to the fact that, in order to increase the noise immunity, the clock block is made in the form of a series-connected clock generator and a second counting trigger, the outputs of which are the second and first outputs of the clock block, respectively, and the second register and the element EXCLUSIVE ID are entered into the device, including connected between the output of the first register and the information input of the second register, the synchronizing input of the clock unit connected to the second output, the first output of which is connected to the other input of the EXCLUSIVE OR element, the output of the second register is connected to the input of the first counting trigger.