SU1118996A1 - Device for compressing data when executing dataexchange between computers - Google Patents

Abstract

A DEVICE FOR COMPRESSING DATA DURING EXCHANGE BETWEEN ELECTRONIC COMPUTING MACHINES, containing number registers, address registers, switches, characterized in that, in order to improve performance, an adder, a comparison circuit switch, a control unit, including a clock pulse generator and a pulse generator, are inserted into it, and a control accumulator is inserted into it, and a control circuit switch is turned on. a storage unit, the first information input and output of which are connected respectively to the information input and output of the device, the control input of the mode setting is connected to the first output the decoder allowing the inputs of the first, second and third switches are connected to the first output of the decoder, the second information output of the associative storage unit is connected to the information inputs of the first address register and the adder, the output of which is connected to the information first register number, the third information output of the associative storage unit is connected to information the inputs of the second address register and the second number register, the bits of the first address register are connected to the first groups pami information inputs of the first comparison circuit, the first and second switches, the outputs of the bits of the second register of the address connected to the second group of information inputs of the first comparison circuit and the first group of information inputs of the third switch, the outputs of the bits of the first register number connected to the first group of information inputs of . the key switch and with the second groups of information inputs of the first and third switches; the outputs of the bits of the second register of the number are connected to the second group of inputs (the Formation inputs of the switch and the second group of information inputs of the second switch; the outputs of the first, second and third switches are connected to the second information the input of the associative storage unit, the first and second groups of outputs of the switch are connected respectively to the first and second groups of inputs of the second comparison circuit, the outputs of the first and second Comparison circuits are connected respectively to the information inputs of the decoder, the clock input of which is connected to the output of the clock generator, whose input is connected to the information input of the device, the second output of the decoder is connected to the switch enable input.

Description

The invention relates to computing. A device for information exchange is known, containing two memory blocks, an ardres register, a regeneration register, a group of elements AND, input and output switches, an object matching node, a synchronization node, an amplifier node, AND, OR, decoder nodes, a request address generation node exchange 1. The known device does not allow the data to be encoded selectively, in order to reduce the amount of data involved in the exchange with the highest frequency. A device is known that contains a control unit, which includes decoders for the signs of the starting address, command information, numeric information and a trigger, an address generation unit, command and numeric information conversion units 2. This device has the same drawback as the previous one. Closest to the present invention is a device comprising buffer registers, two control registers, an address register, a marker register, switches, and a byte counter. The device provides word editing bytes, forming words of different formats, highlighting fields inside a word, reduces computer time costs during information exchange 3. However, the device does not automatically transcode data depending on the intensity of their participation in machine-to-machine exchange, which reduces the efficiency of the exchange and causes situations in which the time of data exchange in the channels exceeds the allowable, which delays the solution of the problem. The purpose of the invention is to increase the speed of the device. The goal is achieved by adding an adder, a switch, comparison circuits, a control unit that includes a clock generator and a decoder, an associative storage unit, the first information input and output of which are connected to information devices in the device containing number registers, address registers, switches. the device input and output, the mode setting control input connected to the first output of the decoder, the enabling inputs of the first, second, and third switches are connected to the first output m decoder, the second information output of the associative storage unit is connected to the information inputs of the first address register and the adder, the output of which is connected to the information input of the first number register, the information output of the self-associative storage unit connected to the information inputs of the second address register and the second number register, the outputs of the first the address register is connected to the first groups of information inputs of the first comparison circuit, the first and second switches, the outputs of bits in the first address register is connected to the second group of information inputs of the first comparison circuit and the first group of information inputs of the third switch; the bits of the first register of the number are connected to the first group of information inputs of the 1st switch and the second groups of information inputs of the first and third switches; the number register is connected with the second group of information inputs of the switch and with the second group of information inputs of the second switch, the outputs of the first, second and third The switches are connected to the second information input of the associative storage unit, the first and second groups of switch outputs are connected respectively to the first and second groups of inputs of the second comparison circuit, the outputs of the first and second comparison circuits are connected respectively to the information inputs of the decoder, the synchronization input of which is connected to the clock generator output pulses, the input of which is connected to the information input of the device, the second output of the decoder is connected to the enable input of the switch. Fig. 1 is a block diagram of a computing system in which the proposed device is used; in fig. 2 - device diagram; in FIG. 3 is a control block diagram; in fig. 4 and 5 - time diagrams of work. The following symbols are used in the diagrams: devices 1 and 2; electronic computing machines (computers) 3 and 4; hardware 5. and b data transmission; link 7; information link, associative storage unit 9; control unit 10; adder And; register number 12; address register 13; register number 14; address register 15; comparison circuit 16; switch 17; comparison circuit 18; switches 19 - 21, the generator 22 clock pulses; the decoder 23. The device in the composition of the computing system works as follows. Between the computer 3 and the computer 4 through the equipment 5 and 6 of data transmission over the communication channels 7 there is an exchange of alphanumeric data representing a sequence of words, phrases. Understandings in the form of dictionaries or arrays are stored in a computer memory. The number of the concept in the dictionary (or its derivative) is the code of the concept and replaces it when data is exchanged between computers.

The code of understanding is one-to-one corresponds to the address at which the frequency of the frequency of the understanding in the exchange between computers is stored in the memory of the device. When transmitting from a computer to a communication channel or receiving from a communication channel of a particular concept, the code of the concept is transmitted from computer 3 to device 1, from computer 4 to device 2.

Based on this, in devices 1 and 2, the frequency of this understanding in exchange is accumulated. After increasing the frequency of device 1 and 2, a frequency is searched simultaneously, the value of which is less than the value of the changed frequency. - In this case, the search is performed only from the set of frequencies that correspond to the concepts with a code of lower magnitude than the code of the concept, whose frequency has changed. If such a frequency is found in the device, it changes places with a changed frequency, and devices 1 and 2 issue codes of descriptions whose frequencies are changed in computer 3 and computer 4. Upon receipt of these codes in the computer 3 and computer 4, the codes are changed for the corresponding concepts.

The computing system operates in accordance with the timing diagram (Fig. 4), which depicts the system operation cycle when the code of the concept is transmitted from the computer 3 and the computer 4. A similar diagram corresponds to the transmission of the code of the computer 4 and computer 3.

Shorter. the device code encodes those concepts that are more often involved in the exchange between computers. The automatic transcoding of concepts when changing frequencies provides synchronously in both computers, and only those concepts whose frequency ratio has changed and the codes differ in the number of bits are subject to transcoding. Thus, by reducing the length of the codes of the concepts most actively involved in the exchange, the efficiency of data exchange is increased.

In the associative memory unit 9, numbers are stored which represent the frequencies of participation in the exchange between computers. The code of understanding and the address of the frequency of the code in exchange are in one-to-one correspondence with each other. The address contains the section number in which the frequency is stored. In this section, the frequencies of those concepts whose codes contain the same number of bits are stored are one less than the number of bits in the codes whose exchange frequencies are stored in the next section.

The signal from the computer about the arrival of the number of the un (participating in the exchange) is fed to the input of the control unit 10 and starts the generator 22 of clock pulses, which through the decoder 23 begins to generate the control signals of the operation cycle of the device.

The device operates in accordance with the timing diagram (Fig. 5).

The first control signal is transmitted from the output of control unit 10 to the control input of unit 9. By this signal, in block 9, the code of the concept received via the information link 8 to the input of block 9, an address is generated and the output of block 9 receives a number representing the frequency of participation in the exchange, which is transmitted to the input of the adder 11, in the adder increases by one and from its output enters the input of the register on the 12th. In addition, from the same output of block 9 to the input of the register 13 address receives the address of the number. From another output of block 9 to

The inputs of the register are 14 numbers and the register 15 addresses are received next number and address, starting from the first day of the first section. From the output of the address registers 13 and 15 are fed to the first comparison circuit 16, which supplies a signal to the input of the control unit 10 if the section number of the second address is less than the section number of the first address. If the circuit 16 does not supply a signal, the control unit 10 generates a signal for the end of the operation cycle and supplies it from the output to the control input of the block 9. On receipt of the signal from the comparison circuit 16 to the input of the control block 10 in the block 10, a second control signal is generated, which is received to the second output of the control unit 10.

g

The second control signal from the second

the output of the control unit 10 is fed to the input of the switch 17 and passes the numbers from the outputs of the registers 12 and 14 to the inputs of the comparison circuit 18. The comparison circuit 18 generates a signal if the number in register 12 is greater than the number in register 14, i.e., if the frequency of participation in the exchange is understood, then the section with the larger number is greater than the frequency of the concept with the section with the higher number. If the comparison circuit 18 does not signal,

then the control unit 10 generates a third control signal, which is output from the control unit 10 to the input of block 9 and delivers the next order and number to the output of block 9 and repeats the actions caused by the first control signal; comparing the addresses in the comparison circuit 16 and supplying (as a result of the comparison) the signal of the end of the operation cycle or the second control signal. From the output of the comparison circuit 18, the signal is fed to the input of the control unit 10, and in the control unit 10 a fourth control signal is generated. By. The fourth control signal, which enters from the output of the control unit 10 to the control inputs of the unit 9 and the switches 20 and 21, is shifted

frequencies in places: the switch 20 passes to the input of block 9 the second address from the output of register 15 and the first number from the output of register 12, and the switch 21 to the first address from the output of register 13 and the second number from the output of register 14. On the fourth signal of block 9, first, the numbers entered at the input are recorded; secondly, two concepts codes are output to the information output of the device in order to change the codes of the corresponding concepts in the computer memory. This cycle of operation of the device ends. When generating in the control unit 10 a signal about the end of the operation cycle (in the absence of a signal from the output of the comparison circuit 16, indicating that the section number of the next number is less than the section number of the first number, the switch 19 opens and passes the first address from the output of the register 13 to the input of block 9 and the number from the output of the register 14. The signal on the end of the cycle of operation of the device also enters the control input of block 9 and causes the recording of the number entered at the input. At this, the operation of the device ends before the next input at its input numbers understand

As a result of the operation of the device, the concept of alphanumeric information is encoded in accordance with the intensity of participation in the exchange of data between computers: the more often the concept participates, the shorter the code. The replacement of codes is done only for certain concepts, which significantly reduces the time for recoding.

The exchange efficiency is increased by reducing the length of the transmitted messages. Let a message be transmitted consisting of N concepts. When coding U concepts by a uniform uniform code, the length of the message LO UN When coding the concepts of the proposed device, non-uniform codes are used, and U - code size increases with decreasing frequency. The length of the message with uneven coding, taking into account the frequency

L. U Niil / if + N,

with Ni. - the number of codes It-size, Nji - the number of codes, frequency

the share in the exchange of which is equal to V / tj, the term N is the number of delimiters required when coding a message of N concepts with non-uniform codes. Winning is defined as

L. -L. .L

Example. Let N 100. Then, when encoding in binary sequence code, 7 binary bits (n 7) are needed, i.e. 1о 7, ... 7, LO 700. Let the exchange frequencies be distributed as follows:

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Ij 5,,

U 6,

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"P l /" 1) 22, 25 l / 5i -T Vs, 2.5 L. Vl "2.5 Oa ... Os5 1.2" 61 ... "69 0.7 | / H ... Vf, zs 0.3 KK .. (" 1.2

1/58 I / 5, M 0.8

..., ja 0.4 1) g, 2G- .3T 0.2,

then L 409, 0.45, e. e. for

In this example, the gain was 45%. Device. especially effective for

large arrays of concepts, the intensity of participation in the exchange of which varies, for example, the nomenclature dictionary. The recoding time is usually the sum of the revision time of the whole list of concepts and its sorting in decreasing order of time. In the proposed device, the recoding time is reduced due to the fact that the recoding consists of four operations: the choice of two concepts and their interchange;

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Claims (1)

DEVICE FOR COMPRESSING DATA WHEN EXCHANGE BETWEEN ELECTRONIC COMPUTER MACHINES, containing number registers, address registers, switches, characterized in that, in order to improve performance, an adder, a comparison circuit switch, a control unit including a clock generator and a decoder, an associative are introduced into it a storage unit, the first information input and output of which are connected respectively to the information input and output of the device, the control input of the mode setting is connected to the first output of the decryption a radiator, allowing inputs of the first, second and third switches are connected to the first output of the decoder, the second information output of the associative storage unit is connected to the information inputs of the first address register and adder, the output of which is connected to the information input of the first number register, the third information output of the associative storage unit is connected to information inputs of the second register of the address and the second register of the number, the outputs of the bits of the first register of the address are connected to the first groups in ormatsionnyh inputs of the first comparison circuit, the first and second switches, the outputs of the second register address bits are connected to the second group of information inputs of the first comparator circuit and the first group of information inputs of the third switch outputs the first bits of the register are connected with the first group of information inputs transferred. switch and with the second groups of information inputs of the first and third switches, the outputs of the bits of the second register of the number are connected to the second group of information inputs of the switch and the second group of information inputs of the second switch, the outputs of the first, second and third switches are connected to the second information input of the associative storage unit, the first and the second group of switch outputs are connected respectively to the first and second groups of inputs of the second comparison circuit, the outputs of the first and second comparison circuits The connections are connected respectively to the information inputs of the decoder, the synchronization input of which is connected to the output of the clock generator, the input of which is connected to the information input of the device, the second output of the decoder is connected to the enable input of the switch. fig Ϊ