GB1560834A

GB1560834A - Apparatus for generating at an output terminal thereof a succession of output bits representative of information contained in an arbitrary sequence of information bits applied to an input terminal thereof

Info

Publication number: GB1560834A
Application number: GB2806476A
Authority: GB
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1975-07-08
Filing date: 1976-07-06
Publication date: 1980-02-13
Also published as: FR2317828B1; DE2629799A1; FR2317828A1; NL7508096A; JPS529408A

Description

(54) APPARATUS FOR GENERATING AT AN OUTPUT TERMINAL THEREOF A SUCCESSION OF OUTPUT BITS REPRESENTATIVE OF INFORMATION CONTAINED IN AN ARBITRARY SEQUENCE OF INFORMATION BITS APPLIED TO AN INPUT TERMINAL THEREOF (71) We, PHILIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LIMITED of Abacus House, 33 Gutter Lane, London, EC2V 8AH a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The invention relates to apparatus for generating at an output terminal thereof a succession of output bits representative of information contained in an arbitrary sequence of information bits applied to an input terminal thereof, successive said information bits of said sequence occurring in successive information bit cells and successive said output bits occurring in successive output bit cells, said apparatus comprising a coding device the input of which is constituted by said input terminal, said coding device being constructed to effectively divide the information bits received in succession on its input into groups in such manner that a first number of said information bits will constitute a said group if the bit or succession of bits making up said first number has a first predetermined characteristic and a second number of said information bits will constitute a said group if the succession of bits making up said second number has a second predetermined characteristic, and to generate at its output a code word representative of the information word constituted by each group thus formed, each said code word having more bits than has the information word to which it corresponds, the various said code words being generated in succession, the bits of each code word occurring in successive code bit cells, and the various code words being such that code bits of one value cannot occur in directly successive code bit cells.

Apparatus of this kind is often used when it is desired to transfer information to a medium which can have two states. bits of the one value giving rise to a transition between one state and the other and bits of the other value not giving rise to such a transition. The medium may be, for example, a magnetizable tape which can be driven along a read and/or write head. As an alternative it may be a data transmission channel. Each information bit appears in its own bit cell, i.e. in a time interval of a fixed length. Information bits of one value may be represented by an "empty" bit cell. The form in which the information bits appear may be arbitrary. It may be, for example, a signal level, the presence or absence of a transition, a waveform having a given direction etc., in accordance with known techniques. Similarly, the code bits occur in a succession of code bit cells.

It is desirable to also incorporate clock pulse information in the medium, preferably without employing a separate track or channel for this purpose. Moreover, the bandwidth required in the channel is preferably as small as possible. The biphase and double-frequency codes used in known such apparatuses result in at the most two and at the least one transition between the two states of the medium per information bit cell. Thus, a comparatively large amount of clock pulse information is provided in the medium when such codes are used, so that the capacity of the medium is limited. Codes are also known which give rise to less transitions. for example one transition per information bit cell at the most. For example, U.S. Patent Specification 3108261 discloses the so-called "delay code". Two successive information bit cells then give rise to at least one and at most two transitions of the said state. When this code is used, an information bit cell containing the information "0" followed by an information bit cell containing the information "1" does not give rise to a transition. Two successive information bits "O" give rise to a transition at an instant between the two. An information bit "1" gives rise to a transition at an instant occurring at the middle of the relevant information bit cell. Successive transitions are thus spaced at least one and at the most two information bit cells apart.

The above coding can be considered as the formation of groups of code bits (code words) from corresponding groups of information bits (information words). As regards the state of the medium it is assumed hereinafter that a code bit " I " gives rise to change in the state of the medium (for example, at the beginning of the said code bit) and a code bit "0" does not give rise to such a change. It will be appreciated however that employing the reverse convention will give corresponding results.

A known form of coding is realized by using the following code alphabet, which indicates which code words represent which groups of information bits (information words): information words code words 01 01 0001 00 0010 It will be seen that one or more code bits "0" are always present between successive code bits "1". Because there are only three code words, the implementation of such a system is very simple. On the other hand, the efficiency of this system is rather small.

(The efficiency is defined as the mean number of information bits per code bit.) In this case the efficiency is only 50V0.

Furthermore, the state transitions can occur comparatively closely together. (If the input information is 1111, one transition will occur for each information bit).

It is an object of the invention to provide apparatus which can give a high efficiency and a high transmission rate, so that the channel capacity can be efficiently utilized, which can employ a short code alphabet, and in which information transferred therefrom to a medium can be adequately self-synchronizing.

The invention provides apparatus for generating at an output terminal thereof a succession of output bits representative of information contained in an arbitrary sequence of information bits applied to an input terminal thereof, successive said information bits of said sequence occurring in successive information bit cells and successive said output bits occurring in successive output bit cells, said apparatus comprising a coding device the input of which is constituted by said input terminal and a processing circuit coupling the output of said coding device to said output terminal, said coding device being constructed to effectively divide the information bits received in succession on its input into groups in such manner that a first number of said information bits will constitute a said group if the bit or succession of bits making up said first number has a first predetermined characteristic and a second number of said information bits will constitute a said group if the succession of bits making up said second number has a second predetermined characteristic, and to generate at its output a code word representative of the information word constituted bv each group thus formed, each said code word having more bits than has the information word to which it corresponds, the various said code words being generated in succession, the bits of each code word occurring in successive code bit cells, and the various code words being such that code bits of one value cannot occur in directly successive code bit cells whereas a specific sequence of said information bit, which sequence is of arbitrary length, will result in the generation of a corresponding sequence of code bits of the other value in successive code bit cells, said processing circuit being constructed to respond to the application of the successive code bits to its input by generating a succession of output bits representative thereof at said output terminal in such manner that output bits of said one value will never occur in directly successive bit cells whereas output bits of said one value will occur at intervals whatever sequence of information bits is applied to the input of the coding device.

The basic structural components of the device thus consist of a coding device which forms the code words in such manner that it is possible that a long series of code bits of said other value may occur, and a processing circuit which removes the risk of long series of bits of said other value occurring at the output terminal (which bits may not give rise to a transition in a medium to which the output terminal may be coupled).

The processing circuit may be constructed, for example, to change the values of certain code bits or to add further bits to the code bit stream.

The processing circuit may comprise a scrambler, said scrambler comprising a scrambling member, a shift register coupling the output of the coding device to an information signal input of said scrambling member, and a clock pulse source constructed to generate clock pulses which are isochronous with the code bits applied to the shift register, an output of said clock pulse source being coupled to a shift signal input of said shift register and an output of said clock pulse source being coupled to a control signal input of said scrambling member via a controllable pulse suppression circuit, outputs of specific stages of said shift register being coupled to a control input of said pulse suppression circuit in such manner that said pulse suppression circuit will suppress certain clock pulses which would otherwise be applied to the control signal input of the scrambling member, the clock pulses so suppressed depending on the collective content of said specific stages.

"Isochronism" is to be understood to mean a property of two recurrent phenomena that the interval between two significant instants in-each is equal to a specific value or to an integral multiple of the said specific value.

Referring to the present state of the art, U.S. Patent Specification 3647964 discloses a coding device employing a code alphabet which can give rise to an unlimited series of code bits "0", successive code bits "1" in each code word always being separated by at least one code bit "0". However, code bits "1" belonging to successive code words are not necessarily separated by at least one code bit "0". Moreover, all code words have the same length, so that a large code alphabet (many words) is required.

Obviously, this results in a complex coding device.

U.S. Patent Specification 3685033 discloses a code conversion method permitting shorter code alphabets to be employed. However, two code bits "1" can again directly succeed each other, so that if these code bits are applied to a medium the information density possible therein is limited by this fact. Moreover, the code words are chosen so that an upper limit is imposed on the number of code elements "0" which can occur in succession, resulting in the code words being rather long.

Scramblers are known per se from U.S.

Patent Specification 3421146, and a more recent article by D. J. Leeper; "A universal digital data scrambler", Bell System Technical Journal, Vol. 52, No. 10, December 1973, pages 1851-1865.

Embodiments of the invention will be described in detail hereinafter, by way of example, with reference to the accompanying diagrammatic drawings in which: Figure 1 shows a block diagram of a first embodiment, Figure 2 shows a block diagram of a second embodiment, Figure 3 shows a possible construction for part of the apparatus of Figure 1 or Figure 2, Figure 4 is a clock pulse diagram relating to Figure 3, Figure 5 shows a possible construction for another part of the apparatus of Figure 1, Figure 6 shows a time diagram relating to Figure 5, Figure 7 shows a possible construction for another part of the apparatus of Figure 1 or Figure 2 when said apparatus includes the construction of Figure 3, Figure 8 shows an alternative construction to Figure 5, Figure 9 shows a time diagram relating to Figure 8, Figure 10 shows a possible construction for part of the apparatus of Figure 2, and Figure 11 shows an information diagram relating to the construction of Figure 5.

First of all, a code will be described which allows successive transitions of the state of a transmission medium to occur at intervals T, 3/2T, 4/2T, 5/2T,... from each other, the unit T/2 being the length of a code element.

It can be proved that when such a code is used in which the maximum length of the code words is infinite (implying the use of a corresponding complex coding device), an efficiency improvement of 38% can be achieved with respect to the commonly used NRZ- I code. In fact a very short code alohabet will he given, bv wav of example, which is realizable with an inherently simple coding device, and which can give an efficiency improvement of approximately 33% although the representation efficiency is in fact 2/3 (two information elements are represented by three code elements), in the most favourable case, depending on the transmission channel properties, its use can enable the transmission rate therethrough to be doubled, because two code elements containing a transition can never occur in direct succession. The code alphabet is given in the following table (various capital letters being used to denote the various bits of the information and code words as shown in the final line of the table, in order that these bits can be conveniently referred to hereinafter): Information words: Code words: Il 000 10 010 01 100 0011 001000 0010 001010 0001 101000 0000 101010 DCBA PONMLK The information bits are received in a sequence progressing from left to right in this example. If one of the first two bits is a logic "I", the first three lines of the table are applicable. If no logic "1" is present, a further two information bits must be received before a complete code word can be composed. Each code word of three or six code elements terminates with a code element "0" (which element does not give rise to a transition in the transmission medium), so that one or more code elements "0" always occur between successive code elements "1". Because the code word 000 also occurs, there is no upper limit on the number of code elements "0" which can occur in uninterrupted succession.

It will be obvious that the above alphabet is only one of many which are possible. For example those code words which have the same length can be interchanged, and/or all code words can commence with a code element "0" instead of terminating therewith. Moreover, one of the two columns can be read from right to left. It will be evident that all possibilities are covered by the group of seven information words.

Two embodiments of the invention will now be described, one including a scrambler which changes elements of the various code words formed, and one including a device which adds additional code elements containing a transition to the various code words formed.

Figure 1 shows a block diagram of a first embodiment of the invention in the form of a data storage system utilizing a magnetic tape. Information bits are input on input terminal 70, for example from a central data processor. The information bits are applied to a coding device 71 which forms information words therefrom and converts these information words into code words in accordance with the coding alphabet quoted above. The output of the coding device is in the form of a pulse train, a code element "1" being represented by a pulse, and a code element "0" by the absence of a pulse. These code elements are applied serially to a divide-by-two member 72 (for example a flipflop), output signals from which are applied to a scrambler 73. As will be described, in this scrambler every two, or possibly three, channel symbol time intervals in which there is no change in the state of the divide-by-two member are combined to produce a clock pulse train which controls a scrambling member which scrambles the code information. The output signals of the scrambling member are applied to a change-of-state coder which comprises a delay line 74 constructed to provide a delay which corresponds to the length of a channel symbol (,T). The output signals of the element 73 and of the delay line are applied to an exclusive-ORgate (modulo-2 adder) 75, with the result that the gate 75 produces an output only if a change of stage occurs in the output of the scrambler. The output signal of the gate 75 is applied to and stored in a magnetic tape 77 via a write amplifier 76.

The code elements stored in the magnetic tape can be read by a read head/amplifier 78 which may be constructed to differentiate the signals passing through it to produce output pulses which are applied to a divide-by-two member 79. The output signals of the divide-by-two member 79 are applied to an unscrambler 80 which operates in the inverse way to the scrambler 73, so that the modifications to the code words introduced by scrambler 73 are removed. The output signals of the unscrambler are applied to members 81, 82, whose construction and function correspond to that of the members 74 and 75 respectively and which thus form a change-of-state coder. The output signals of the gate 82 are applied to a decoding device 83 which operates in the inverse way to the coding device 71, so that the original information bits appear on the output terminal 84, for example for use in the central data processor or in another user device. If desired the magnetic tape 77 can be replaced by a line connection between transmission and receiver amplifiers 76, 78.

Moreover, it will sometimes be that the amplifier 78 will not have a differentiating action; in such a case the divide-by-two member 79 can be dispensed with.

Figure 2 shows a block diagram of a second embodiment of the invention. In this embodiment additional code elements are added to the various code words formed.

Information bits are applied to the coding device 71 via the terminal 70. The output signals of the coding device are applied to a buffer register 85. When the buffer register becomes filled with a given number of code elements, for example 12 code elements, this fact is detected and these 12 code elements are transferred in parallel to an output register 87 which is then also supplied with a code element 1 and a code element 0 from a code generator 86, in such manner that the ultimate result can never contain two code elements 1 in direct succession. Thus if the example of a code alphabet quoted above is used, and the code elements (bits) are written into register 85 in the order KLM ., the code element I from generator 86 will be written into the penultimate stage of register 87, whereas if the code elements are written into register 85 in the order... MLK the code element I will be written into the last stage of register 87. The output signals of the output register 87are applied to the medium 77 (the devices 76, 78 shown in Figure I having been omitted for the sake of simplicity), and the signals read therefrom are applied to a register 88. When 14 code elements have been serially received therein, this fact is detected and the code elements are applied in parallel to a register 90 and to a terminating device 89 which operates, for example, as a register, the non-significant code elements added by element 86 being applied to this terminating device and being excluded from further use. The signals from the register 90 are applied to an output terminal 84 via a decoding device 83. Due to the addition of the two additional code elements, the efficiency is decreased by a factor 12/14, but the fact that it may be possible to transmit the channel symbols at twice the rate that it is possible to transmit the original information bits can give a net overall improvement in efficiency.

Moreover, not more than 13 successive code elements 0 can ever occur in direct succession. This number will normally not be too high to enable proper synchronisation to be maintained if it occurs. If desired the registers may be given other capacities for example 9 or 15 bits.

Figure 3 is a diagram of a coding device for producing code words in accordance with the alphabet quoted previously. The device comprises an information input terminal 1, a shift register 2 having stages 3, 4, 5, 6, a clock 7, two divided-by-two members 8, 9 (which operate as two-counters) two logic AND-gates 10, 11, two logic OR-gates 12, 13 a shift register 14 comprising stages 15, 16, 17, 18, 19, 20, and information output terminal 21, and a further gate 251. Figure 4 shows clock pulse series 22, 23, 24 which appear on the three outputs of the clock 7 in the circuit shown in Figure 3.

Input information bits are applied to terminal 1. The shift register 2 is controlled by the clock pulses shown at 22 in Figure 4, and the divide-bv-two member 8 is supplied with the clock pulses shown at 23 in Figure 4.

After the first clock pulse 22 the state 3 contains the first information bit. After the first clock pulse on the line 23, the divideby-two member or counter 8 assumes its "l"-position. After the second clock pulse 22, the stages 3, 4 contain the first two information bits. If at least one of these two bits is a logic "1", the corresponding "1"output of the stage is activated and the ORgate 12 produces a logic "l"-signal to indicate that the first code word to be formed comprises only three channel symbols. In such a case the state 3 contains the information bit A, and the stage 4 contains the information bit B (see the coding alphabet table). The next clock pulse 23 resets the divide-by-two member or counter 8 to its zero position, so that it applies a carry output signal (a momentary "I") both to the divide-by-two member 9.

which assumes its one-position in response thereto and also (slightly later) to the logic AND-gate 10, with the result that the gates 11 and 13 both receive a logic "1". The output signal of the gate 10 also resets the divide-by-two member or counter 9 to its zero position in such a manner that "1" is effectively subtracted from the contents thereof. i.e. in such a manner that a "carry" is not produced at its output. The " I " appearing at the outupt of the OR-gate 13 activates the shift register stages 15, 16, 17 so that they take in input information. the following functions then being implemented: K (state 15):=0 (due to the input terminal thereof being at a fixed potential) L (stage 16):=at (from stage 3) M (stage 17):=B (from stage 4).

The symbol ":=" indicates in known manner the effectuation of an information modification.

If neither of the stages 3, 4 contains an information bit "1" after the second shift pulse, nothing happens (as required, because in that case the code word to be formed requires the presence of an information word having a length of four bits). The divide-by-two member or counter 9 then remains in the "1" position. When the next (third) clock pulse occurs on the line 23, the divide-by-two member or counter 8 assumes its "1" position again. When the next (fourth) clock pulse has occurred on the line 22, the stages 3, 4, 5, 6 will contain the information bits A, B, C, D, respectively. When the next (fourth) clock pulse occurs on the line 23, the divide-bytwo member or counter 8. and hence also the divide-by-two member or counter 9, counts on to its zero position and produces a carry output signal, with the result that the shift register stages 18, 19, 20 are activated directly from the output of 9 and the shift register stages 15, 16, 17 are activated via the OR-gate 13 to take in input information.

The "carry" pulse from 9 is also applied to the input of the gate 251 via the delay member 25. Although shown as a simple OR gate, gate 251 is in fact constructed so that a "1" appearing at its output will be cancelled by a "1" applied to its lower input. Thus the information in stage 17 is reset to a "0" if it should have been previously set to a "1" because the stage 3 happens to contain an information bit "1" and the stage 4 happens to contain an information bit "0". The output signal of the member 25 may, of course, as an alternative be applied directly to a reset input of stage 17, in which case gate 251 may be replaced by a direct connection from gate 11 to stage 17. It will be seen that the following functions are implemented: K (stage I5):=Q L (stage 16):=A (from stage 3) M (stage 17):=0 N (stage 18):=1 O (stage 19):=0 P (stage 20):-B (from stage 4) The required inversions are achieved by way of a connection to the inverted output of the corresponding stage 3, 4. The signal input terminals for the stages 15, 18, 19 can be connected to steady signal sources (not shown). The shift register 14 is supplied with the clock pulses 24 at a repetition frequency which is 50% higher than that of pulses 22.

Thus, three stages of the shift register 14 are always emptied in order that they can be supplied with code elements for every two information bits fed into the shift register 2. The delay produced by the member 25 can correspond to 1/3 of the period of the clock pulses 23. The stages 5, 6 may be dispensed with if desired.

The coding device of Figure 3 is only one of many possible constructions for the element 71 of Figure 1, 2; the element 71 may, as an alternative consist of a combinatory circuit only (made up from gates etc. to operate without employing sequential logic). As a further alternative the coding can be effected by means of a table which is permanently stored, for example in a read-only memory.

Figure 5 shows a block diagram of a scrambler which can be used in the apparatus shown in Figure 1. The scrambler comprises a clock 7, a source 210 for code elements, a shift register 26 comprising stages 27, 28, 29, 30, an exclusive-OR-gate 31, an inverter 32, four logic AND-gates 33, 34, 39, 40 a logic OR-gate 41, two delay members 35, 36, a scrambling member 42, and an output terminal 43. Figure 6 is a time diagram for explaining the operation thereof, 63 denoting a series of signal elements originating from the coding device 71 of Figure 1 (in which series it is, as has already been stated, impossible for two elements having the value "1" to occur together within an elementary time unit T).

In Figure 6 signal elements at 63 having the value "1" are represented at 63A by pulses, signal elements having the value "0" being represented by the absence thereof. 64 shows the numerical values of the corresponding output signal of the divideby-two member 72 (Figure 1) the output signal itself being shown on line 44. (A "I" bit corresponds to a high signal and a "0" bit corresponds to a low signal.) The clock 7 corresponds to the clock 7 of Figure 3, and controls the production of code elements from source 210 by means of a series of clock pulses the frequency of which is the same as that of the pulses 24 in Figure 4. The member 210 is therefore merely a symbolic representation of the divide-by-two member 72. The shift register 26 is supplied with these clock pulses, which are shown at 49 in Figure 6. If it is assumed that one of the gates 39, 40 passes a clock pulse to the output of the OR-gate 41 at a given time (the circuit having been started by, for example momentarily applying a pulse to a further input (not shown) provided on gate 41) then, if the stages 27 and 28 contain the same information, the exclusive-OR-gate 31 will produce a logic "0"-signal and the inverter 32 will produce a logic "I"-signal, so that the AND-gate 34 is open and the delay member 36 is started. Signals applied to the input of this member appear on its output true to shape but after a delay which corresponds to two periods of the clock pulses 49, so that the next clock pulse is blocked by gate 40 and the subsequent (second) clock pulse is transmitted thereby.

However, if the stages 27 and 28 contain different information, the exclusive-ORgate 31 produces a logic "1" signal, so that the AND-gate 33 is opened and the delay member 35 is started. Signals received on the input of this member appear true to shape on its output, but after a delay which corresponds to three periods of the clock pulses 49, so that the next two clock pulses are blocked by gate 39, and the subsequent (third) clock pulse is transmitted thereby.

The output pulses of the gates 39 and 40 actuate the scrambling member 42 via the OR-gate 41. This scrambling member substantially corresponds to that described in the quoted article by Leeper. It comprises two modulo-2 gates 421, 422 and, in this simple case, five shifting members 423 to 427, the information in which is shifted one position further each time the gate 41 produces an output. The modulo-2 gates provide feedback. When the input information is transmitted by the modulo-2 gate 421, it appears on the output 43.

Figure 6 shows time diagrams of various signals relating to the foregoing. 47 shows the code elements stored in the stage 27: 46.

45 and 44 show the same for the stages 28, 29 30, respectively. As already mentioned, 49 shows the pulses, the phenomena 4448 being isochronous therewith: a signal cha pulse is passed by 39 or 40: whether or not this is so depends, of course on the previous history. When this first clock pulse appears the signal 48 is low, because the signals 46 and 47 are then both high. As a result, the gate 34 is opened and only one clock pulse is blocked. On the other hand the pulse train 51 appears at the output of 41 if it is assumed that the first clock pulse is blocked. When the next clock pulse appears, the stages 27 and 28 contain different information, so that two clock pulses are blocked by way of the member 35. After this has occurred the pulse trains 50 and 51 are identical and the further passing or blocking of clock pulses will be exclusively determined by the information then received, i.e. no longer by the previous history.

Figure 11 shows an information diagram relating to the scrambling member 42 or Figure 5, the columns 30, 423, 424, 425, 426 427 showing the output information of the correspondingly numbered members of the circuit shown in Figure 5 for successive output pulses from gate 41. The first line of "0"s and "l"s contains an arbitrary starting position. The input information is that shown at 64 in Figure 6 (and at 44), the dots denoting when the successive pulses 50 (Figure 6) appear on the output 43 thus, each time two or three identical bits of the signal 64 are combined. The exclusive-OR (modulo-2) gates 421, 422 determine the output information (which corresponds to that shown in the column 423) directly. In the second line of Figure 11 (the second line of "0"s and "l"s) this output information is therefore: (0+0+0) mod 2=0, in the third line : (1+1+1) mod 2=1, and so on, the information in each column 423--427 being shifted over one column position for each pulse 50.

The output information is shown at 65 in Figure 6. The members 74 and 75 (changeof-state coder) of Figure 1 from a code element 1 shown at 66 in Figure 6 in reaction to each change in the signal 65, the write amplifier 76 being fed with each said code element " I " and reversing the magnetization direction in the tape 77 in response thereto. (If the output signal were to be transmitted instead in the form of first and second signal levels, the members 74, 75 could be dispensed with).

It will be seen that two successive code elements I never occur on the line 66.

Moreover the probability of a long series of successive code elements 0 occurring has been substantially reduced: it will be noted that the last portion of the signal 63 which consists of a continuous series of "0"s still gives rise to transitions in the signal 66. The risk of a long series of transitionless code elements occurring can be reduced to any required value by including a sufficiently long series of fed back elements 423--427 in the scrambling member.

The member 79 (Figure I) is analogous to the member 72, so that the signal 66 (Figure 6) read from the tape 77 by read head/amplifier 78 is formed thereby into a signal similar to signal 65. The unscrambler 80 is designed to operate in conjunction with the scrambler 73. As will be seen from the article by Leeper it can comprise similar components to the scrambler of Figure 5 but in a slightly modified configuration, the member 210 now corresponding to the divide-by-two member 79. Thus the unscrambler 80 may also include a series of five shifting members, the outputs of the third and the fifth member being fed to the input of a modulo-2 gate whose output is coupled to an input of a further modulo-2 gate the other input of which is fed with the input signal and the output of which supplies the output signal (there being now no connection from the output of this further gate to the input of the first shifting member). However the input signal is now itself also applied directly to the first shifting member. The clock pulses are treated therein a similar manner to that described with reference to Figure 5. The members 81/82 of Figure 1 are similar to the members 74/75. The information shown at 63 in Figure 6 is thus recovered at the output thereof.

Figure 7 shows a possible construction for the decoding device 83, designed to operate in conjunction with the coder of Figure 3.

Decoder 83 comprises an input terminal 91, a shift register 92 having stages 93-98, a ring counter 99 having stages 100--106, a delay member 107, a clock 109, a logic ORgates 108, 111, and 113, logic AND-gates 110, 112, 114, 115, a shift register 116 having stages 117-120, and an output terminal 121.

The code elements produced by the members 81/82 and which are as shown at 63 in Figure 6 arrive on the input terminal 91 in a sequence which corresponds to 63 in Figure 6 when read in a direction from left to right. They are advanced in the shift register 92 under the control of the clock 109 by clock pulses which also advance the ring counter 99 via OR-gate 108. This ring counter is arranged so that only one stage thereof produces a logic "l"-signal at any time. In the starting position this stage is the stage 100. Under the control of the first clock pulse, the first code element is stored in the stage 93 and the stage 101 is set to produce a logic "1". After the third clock pulse has occurred the ring counter stage 103 has become set to produce a logic "1" and the first three code elements occupy the stages 95, 94, 93, respectively. If the stage 93 should then contain a code element "0", the AND-gate 110 will be supplied with two logic "I" signals to signify that one of the first three lines of the coding alphabet table is concerned; element K=0. The following logic functions are then implemented: A (fed into stage 117): t (from stage 94) B (fed into stage 118):= g (from stage 95) the gate 112 being opened via the gate 111 to fill the stage 117 with the inverted information (output 0) from the stage 94 and the gate 114 being opened to fill the stage 118, via the gate 113, with the inverted information from the stage 95. Moreover, the output signal of the gate 110 returns the ring counter 99 to its starting position via the line 122, possibly after a small delay, so that the process can be restarted. However, if the gate 110 should not be supplied with two logic "I"-signals after the third clock pulse one of the last four lines of the coding alphabet table is concerned, and the relevant code word comprises six bits. In this case nothing happens for the time being, but the next three clock pulses ultimately cause the stage 106 to produce a logic "1", the code elements having by then successively occupied the stages 98 . . 93.

At that - instant the following logic functions are performed: A (fed into stage 117):=5(from stage 94) B (fed into stage 118):=7(from stage 98) C (fed into stage 1 l9):=O D (fed into stage 120):=O These are achieved because the gate 112 is then opened via the gate 111, to supply stage 117 from the inverted output of stage 94, and the gate 115 is opened in order to fill the stage 118, via the gate 113, with the inverted information from the stage 98. The stages 119, 120 are not fed with information directly and it may be possible to omit them.

The register 116 is controlled by clock pulses from the clock 109 which have a frequency which is 2/3 that of the pulses applied to the shift register 92, and such a phase that the two clock pulse trains do not interfere with each other, i.e. in a manner similar to that described with reference to Figures 3 and 4. The stage 117 is in fact filled with the information 0 each time a clock pulse is applied to register 116, which information is subsequently replaced if required, by the information 1 from the gates 112, 113 when it is in the stage 117 and/or 118. The information bits appear on the output 121, this output corresponding directly, for example, to the output 84 of Figure 1. The output signal of the stage 106 is applied to the ring counter 99 after a small delay, via the member 107 and the gate 108, with the result that the counter is reset to its starting position.

A code will now be described in which successive transitions of the state of the transmission medium (corresponding to a code element "1") can occur at intervals T, 4/3T, 5/3T, 6/3T . . . from each other, 1/3T being the length of a code element. The code alphabet is as follows, and can give substantial efficiency improvement.

Code Information bits; elements: (words) (words) 0 00 10 0100 11 1000 UT YXWV Each group of two or four code elements terminates with two code elements "00" (no transitions), so that two or more code elements "0" always appear between successive code elements "1". Because the code word "00" also occurs, there is no upper limit on the number of code elements "0" which can appear in uninterrupted succession. (Of course, this is only another one of the many possible alphabets which may be used). The coding device 71 (Figure 1) for such a code may have a structure analogous to that shown in Figure 3, but can be simpler, because two information bits at the most have to be translated together into a code word. Because now two or more code elements 0 always occur between successive code elements 1 it is now possible to increase their transmission rate by, depending on the circumstances, up to a factor 3 (again only the code elements "1" give rise to a stage transition in the transmission medium), increasing the transport rate of the information bits by up to a factor 1+ and utilizing the channel capacity more fully accordingly.

If the coding device for forming the code words is constructed in a manner analogous to that shown in Figure 3 the logic functions to be implemented will be: a) if the first information bit received is zero: V:=O W:=O b) if the first information bit is not zero; wait until second information bit is available: V:=O W:=O X:=T Y:=T Corresponding logic functions will of course be required to be implemented for decoding.

Figure 8 shows a scrambler 73 (Figure 1) which may be used for this code, its construction being substantially analogous to that of the scrambler shown in Figure 5.

The scrambler comprises a clock 7 and a source 211 of code elements formed according to the said code alphabet, a shift register 52 having stages 53, 54, 55, 56, 57, 58, two exclusive-OR-gates 61, 62, a NORgate 59, six logic AND-gates 122, 123, 124, 128, 129, 130 a scrambling member 42 having an output 43 and constructed in a similar manner to the scrambling member 42 of Figure 5, three delay members 125, 126, 127, and a logic OR-gate 60. The clock output frequency is equal to the repetition frequency of the code elements. When a clock pulse has been passed to the scrambling member 42 (the circuit having been started by, for example, momentarily applying a pulse to a further input (not shown) provided on gate 61) then, if the shift register elements 53, 54, 55 all contain the same information, neither of the Exclusive-OR-gates 61, 62 will produce a logic "1", so that the logic NOR-gate 59 will produce a logic "1" and open the gate 122.

The member 125 applies any clock pulse received to the AND-gate 128 true to shape but after a delay time of three clock pulse periods, with the result that the next two clock pulses are blocked und the third one is passed by gate 128. However, if the information in the stage 55 had been different from that in 53 and 54 (a "zero" versus two "ones" or a "one" versus two "zeroes"), the logic Exclusive-OR-gate 62 would have produced a logic "1", opening the gate 124 to pass one clock pulse. The member 127 introduces a delay of four clock pulse periods, so that the next three clock pulses would then have been blocked and the fourth one passed by the AND-gate 130. Furthermore, if the information in the stage 53 had been different from that in 54 and 55 the Exclusive-OR gate 61 would have produced a logic "1" opening the gate 123 to pass one clock pulse, this appearing at the output of the member 126 after a delay of five clock pulse periods. In that case the next four clock pulses would have been blocked and only the fifth passed by gate 129. It is not possible for more than one of the gates 59, 61, 62 to produce a logic "1" signal simultaneously.

Figure 9 shows time diagrams of various signals relating to the foregoing. 131 is the output signal of the coding device, a "1" code element corresponding to an output pulse therefrom. 132 is the corresponding output signal of the divide-by-two member 72 of Figure I transitions occurring between successive series of zeroes and ones. 133.

134 . . . 138 are the information contents of the members 58, 57, 56, 55, 54, 53.

respectively. and 139 is the output signal of the gate 59. 140 is the output signal of the gate 61 and 141 is the output signal of the gate 62. 142 are the clock pulses from the clock 7 (with which the phenomena 133141 are isochronous. Code elements "1" in the signal 131 succeed each other at intervals of at least three clock pulse periods. 143, 144, 145 are examples of how the clock pulses may appear on the output of 60 depending on the previous history, 143 being on the assumption that the first pulse is transmitted, 144 on the assumption that the second pulse is transmitted and 145 on the assumption that the third pulse is transmitted. Thus, for signal 143, when the first clock pulse is passed all stages 53-55 contain the information "0" so that two clock pulses are suppressed. The same happens when the third clock pulse is passed, so a further two clock pulses are suppressed. As far as signal 144 is concerned, when the second clock pulse is passed the gate 61 produces a logic "1", so that four clock pulses are then blocked. The situation is subsequently identical to that described previously. As far as signal 145 is concerned, when the third clock pulse is passed the gate 62 produces a logic "1", so that three clock pulses are then blocked.

The situation is subsequently identical to that of the other two cases described. Thus the single output line from 60 offers a clock pulse control which, after a brief starting phenomenon, for the remainder is independent of the previous history. 146 is the output signal of the scrambling member 42 of Figure 8 when it has been constructed in the manner shown in Figure 5 and started with the same information .contents as is shown in Figure 11. 147 is the corresponding output signal of the changeof-state coder comprising the members 74, 75 of Figure 1.

Figure 10 shows a possible construction for the components 85-87 of Figure 2. This construction is in fact suitable for use with both code alphabets described, but will be described as operating on the output of the coding device shown in Figure 3. Thus an input terminal 131 of shift register 132 in Figure 10 is supplied with the code elements which appear on the terminal 21 of Figure 3.

Clock pulses corresponding thereto are supplied to the terminal 135, these pulses being counted in a counter 134. When counter 134 has counted up to 12, forwarding devices 140, 139 are activated and the information in the shift register 132 and a code generator 133 in stored in a shift register 137. If the final stage 1321 of the shift register 132 contains a logic "1", the device 139 is controlled in such a way that it forwards the contents of 133 unchanged, so that the last stages of the shift register 137 will contain the elements 101. However, if it contains an "0" the device 139 is controlled in such a way that it forwards the contents of 133 in an inverted manner. so that the final stages of the shift register 137 will contain the elements 010. This is done because the bit last received may have been a "1" (bit "N" of the coding alphabet table) in which case the bit in the stage 1321 will be a "0" or a "0" (a bit "K" of the table) in which case the bit in the stage 1321 may be a "0" or a "I". In this way it is ensured that two elements "I" cannot appear on the output terminal 138 in succession, and furthermore that not more than 13 elements "0" can be generated in succession. The additional bits can be added either at the beginning or at the end of the series of twelve information bits. 136 is a clock pulse converter which is supplied with the pulses from the clock (terminal 135) and multiplies their frequency by 14/12. Such converters are known per se.

WHAT WE CLAIM IS: 1. Apparatus for generating at an output terminal thereof a succession of output bits representative of information contained in an arbitrary sequence of information bits applied to an input terminal thereof, successive said information bits of said sequence occurring in successive information bit cells and successive said output bits occurring in successive output bit cells, said apparatus comprising a coding device the input of which is constituted by said input terminal and a processing circuit coupling the output of said coding device to said output terminal, said coding device being constructed to effectively divide the information bits received in succession on its input into groups in such manner that a first number of said information bits will constitute a said group if the bit or succession of bits making up said first number has a first predetermined characteristic and a second number of said information bits will constitute a said group if the succession of bits making up said second number has a second predetermined characteristic, and to generate at its output a code word representative of the information word constituted by each group thus formed, each said code word having more bits than has the information word to which it corresponds, the various said code words being generated in succession, the bits of each code word occurring in successive code bit cells, and the various code words being such that code bits of one value cannot occur in directly successive code bit cells whereas a specific sequence of said information bits, which sequence is of arbitrary length, will result in the generation of a corresponding sequence of code bits of the other value in successive code bit cells, said processing circuit being constructed to respond to the application of the successive code bits to its input by generating a succession of output bits representative thereof at said output terminal in such manner that output bits of said one value will never occur in directly successive bit cells whereas output bits of said one value will occur at intervals whatever sequence of information bits is applied to the input of the coding device.

2. Apparatus as claimed in Claim 1, wherein the processing circuit comprises a scrambler, said scrambler comprising a scrambling member, a shift register coupling the output of the coding device to an information signal input of said scrambling member, and a clock pulse source constructed to generate clock pulses which are isochronous with the code bits applied to the shift register, an output of said clock pulse source being coupled to a shift signal input of said shift register and an output of said clock pulse source being coupled to a control signal input of said scrambling member via a controllable pulse suppression circuit, outputs of specific stages of said shift register being coupled to a control input of said pulse suppression circuit in such manner that said pulse suppression circuit will suppress certain clock pulses which would otherwise be applied to the control signal input of the scrambling member, the clock pulses so suppressed depending on the collective content of said specific stages.

3. Apparatus as claimed in Claim 2, wherein code bits of said one value are represented by a pulse at the output of the coding device and code bits of said other value are represented by the absence of a pulse at the output of the coding device and wherein a frequency divider-by-two is included between the output of the coding device and the input of the shift register.

4. Apparatus as claimed in Claim 2 or Claim 3, wherein the output of the scrambler is coupled to said output terminal via a change-of-state coder.

5. Apparatus as claimed in Claim 2, 3 or 4 wherein said output terminal is coupled to a medium and wherein said medium is coupled to the input of a decoder via an unscrambler, said decoder being constructed to process signals applied to its input in an inverse manner to that in which said coding device processes signals applied to the input thereof, and said unscrambler being constructed to process signals applied to its input in an inverse manner to that in

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. such a way that it forwards the contents of 133 unchanged, so that the last stages of the shift register 137 will contain the elements 101. However, if it contains an "0" the device 139 is controlled in such a way that it forwards the contents of 133 in an inverted manner. so that the final stages of the shift register 137 will contain the elements 010. This is done because the bit last received may have been a "1" (bit "N" of the coding alphabet table) in which case the bit in the stage 1321 will be a "0" or a "0" (a bit "K" of the table) in which case the bit in the stage 1321 may be a "0" or a "I". In this way it is ensured that two elements "I" cannot appear on the output terminal 138 in succession, and furthermore that not more than 13 elements "0" can be generated in succession. The additional bits can be added either at the beginning or at the end of the series of twelve information bits. 136 is a clock pulse converter which is supplied with the pulses from the clock (terminal 135) and multiplies their frequency by 14/12. Such converters are known per se. WHAT WE CLAIM IS:

1. Apparatus for generating at an output terminal thereof a succession of output bits representative of information contained in an arbitrary sequence of information bits applied to an input terminal thereof, successive said information bits of said sequence occurring in successive information bit cells and successive said output bits occurring in successive output bit cells, said apparatus comprising a coding device the input of which is constituted by said input terminal and a processing circuit coupling the output of said coding device to said output terminal, said coding device being constructed to effectively divide the information bits received in succession on its input into groups in such manner that a first number of said information bits will constitute a said group if the bit or succession of bits making up said first number has a first predetermined characteristic and a second number of said information bits will constitute a said group if the succession of bits making up said second number has a second predetermined characteristic, and to generate at its output a code word representative of the information word constituted by each group thus formed, each said code word having more bits than has the information word to which it corresponds, the various said code words being generated in succession, the bits of each code word occurring in successive code bit cells, and the various code words being such that code bits of one value cannot occur in directly successive code bit cells whereas a specific sequence of said information bits, which sequence is of arbitrary length, will result in the generation of a corresponding sequence of code bits of the other value in successive code bit cells, said processing circuit being constructed to respond to the application of the successive code bits to its input by generating a succession of output bits representative thereof at said output terminal in such manner that output bits of said one value will never occur in directly successive bit cells whereas output bits of said one value will occur at intervals whatever sequence of information bits is applied to the input of the coding device.

which said scrambler processes signals applied to the input thereof.

6. Apparatus as claimed in Claim 5 when appended to Claim 3, including a change-ofstate coder in the coupling between the output of the unscrambler and the input of the decoder.

7. Apparatus as claimed in Claim 5 when appended to Claim 4, including a frequency divider-by-two in the coupling between the medium and the input of the unscrambler.

8. Apparatus as claimed in Claim 5 when appended to Claim 4, when appended to Claim 3, including a frequency divider-bytwo in the coupling between the medium and the input of the unscrambler and a change-of-state coder in the coupling between the output of the unscrambler and the input of the decoder.

9. Apparatus as claimed in any of Claims 2 to 8, wherein the ratio of the number of bits in each code word to the number of bits in the information word which it represents is 3:2, wherein the clock pulse source is constructed to apply clock pulses to said shift signal input with a frequency equal to the rate at which said code bits are generated by said coding device, wherein said specific stages of the shift register are two successive stages of the shift register, and wherein at least one said certain clock pulse occurs between each two clock pulses applied in succession to the control input of the scrambling member.

10. Apparatus as claimed in Claim 9, wherein the pulse suppression circuit and the coupling from said two successive stages to its control input are constructed so that the presence of bits of the same value in said two successive stages when a clock pulse is applied to the control signal input of the scrambler will result in the suppression of one subsequent clock pulse which would otherwise be fed to said control signal input, and so that the presence of bits of mutually different values in said two successive stages when a clock pulse is applied to said control signal input will result in the suppression of two subsequent clock pulses which would otherwise be fed to said control signal input.

II. Apparatus as claimed in any of Claims 2 to 8, wherein the various code words are such code bits of said one value will always be separated by at least two code bits of said other value, wherein the ratio of the number of bits in each code word to the number of bits in the information word which it represents is 2:1, wherein the clock pulse source is constructed to apply clock pulses to said shift signal input with a frequency equal to the rate at which said code bits are generated by said coding device, wherein said specific stages of the shift register are three successive stages of the shift register, and wherein at least two said certain clock pulses occur between each two clock pulses applied in succession to the control input of the scrambling member.

12. Apparatus as claimed in Claim 11, wherein the pulse suppression circuit and the coupling from said three successive stages to its control input are constructed so that, when a clock pulse is applied to the control signal input of the scrambler, the presence of a bit in the first of said successive stages which is of a different value to the its in the other two said successive stages will result in the suppression of four subsequent clock pulses which would otherwise be applied to said control signal input, the presence of a bit in the last of said successive stages which is of a different value to the bits in the other two said successive stages will result in the suppression of three subsequent clock pulses which would otherwise be applied to said control signal input, and the presence of bits of the same value in all three of said successive stages will result in the suppression of two subsequent clock pulses which would otherwise be applied to said control signal input.

13. Apparatus as claimed in Claim 1, wherein the processing circuit is constructed to respond to the application of a bit stream to the input thereof by generating at said output terminal a bit stream which corresponds thereto but to which has been added a bit of one value and a bit of the other value in succession after every N bits which corresponds to the input bits, where N is an integer having the numbers of bits in the various code words as factors.

14. Apparatus for generating at an output terminal thereof a succession of output bits representative of information contained in an arbitrary sequence of information bits applied to an input terminal thereof, substantially as described herein with reference to Figures 1, 3 and 5, Figures 1, 3, 5 and 7, Figures 1, 8 and 5 or Figures 2, 3 and 10 of the drawings.