DE2629799A1 - ARRANGEMENT FOR TRANSFERRING DIGITAL INFORMATION - Google Patents

Description

N.V. Philips'Gloeilampenfabrieken, Eindhoven / Netherlands

"Arrangement for the transmission of digital information"

The invention relates to an arrangement for transmitting binary data elements over a medium or for storing binary ones Data elements in a medium by means of a two-valued state variable of this medium, which data elements in a bit cell sequence can be freely received at an input of an existing coder, from which received data elements each group alternates at least two different numbers of data elements (data words) and therefrom from the coder groups each corresponding to a data word, but larger numbers of code elements Let (code words) be formed in a sequence of channel symbols, and where a code element is a possibly occurring The transition between the two values corresponds to the state variable. The medium can be a magnetizable tape that can be driven along a read and / or write head. It can also be a channel for data transmission. The data elements can have the value "0" or "1" without restriction, so that the data source of the coding does not have any further Restrictions imposed. The data elements only need to have the appropriate lengths and occur synchronously. The data elements occur in bit cells that are time intervals of fixed length in which a data element (data bit) may occur. If it does not occur, the Bit cell empty. Furthermore, there are no restrictions in the appearance of the data element so that it is a signal

PHN 8061 '- 2 -

^1X1 609884/1040

level, a possible occurrence of a transition, a pulse shape of a certain direction, and this according to known Techniques can be.

The code elements occur in a channel symbol sequence, where a channel symbol is a time interval of fixed length in which a state transition can possibly occur. With respect to the medium, it is desirable to incorporate clock pulse information: in such a case, no separate track or no separate channel is required for this. Preferably is the one needed Bandwidth small. The known two-phase and double frequency codes contain at most two and at least a transition between the two values of the state variable per bit cell. Such codes require a relatively large number Clock pulse information, which limits the capacity of the medium. There are codes with fewer transitions, for example with at most one transition per bit cell, known. For example, US Pat. No. 3,108,261 gives the so-called "delay" code at. In this code, two successive bit cells contain at most two and at least one transition of the mentioned state variable. According to this code, one bit cell results with the information "0" followed by a bit cell with the information "1", no transition. Two consecutive Information "0" is separated by a transition. The information "1" creates a transition in the Middle of the bit cell concerned. So are consecutive Transitions by at least one bit cell and by a maximum of two bit cells apart.

The above coding can be considered the formation of groups of code elements (Code words) from groups of data elements (data words) corresponding to them are considered. The data elements can have any physical appearance. The following is a description of the state of the

PHN 8061 - 3 -

609 b 84/1040

Medium assumes that a code element "1" contains a signal change or a transition (for example on Beginning of this code element); a code element "0" does not contain a transition. The reverse convention provides corresponding Results. As long as the code elements are not yet attached to the medium, and also after the code elements have been read from the medium, they can in turn have different physical manifestations. According to the well-known Technology, the coding can be implemented by the following "code alphabet" consisting of code words into which the Groups of data elements or data words are implemented:

Data words Code words 1 01

01 0001

00 0010

Thus, between successive channel symbols or code elements 1 one or more code elements 0 are inserted. This reduces the symbol interference in the channel. There is further only three code words, which greatly simplifies the implementation. On the other hand, the efficiency is limited. It is defined as the mean number of data bits per channel symbol and is therefore only 50? Ί in this case. Furthermore, the changes in state can occur relatively densely packed, namely in the case of input information 1111, with one transition per data bit then always occurring.

In contrast, the invention seeks a system with a high degree of efficiency along with a high transmission speed on, whereby the channel capacity is better used and the state changes are sufficiently separated from each other. The invention is based on the object of a simple approach

PHN 8061 - 4 -

6 0 9 B _8/4/1 (HQ

- * -? ■ -

To create order with a short code alphabet with a fixed length ratio between data words and code words for a uniform data transmission speed, which maintains the self-synchronizing properties of the code elements to be transmitted over the medium or to be attached in the medium and in which at deia Coder there is no upper limit between has two successive code elements which, without further measures, would result in a transition of the mentioned condition variable. In order to achieve the objects, the invention is characterized in that the coder includes successive code elements of a first ¥ sz * teS; the a 'transition in the state mentioned size "would cause by at least one code element separated from the other value without dai3 the sequentially closed occurrence of a code sequence of elements of this other ¥ ertes an upper limit has ₃ that further the output of the coder is connected to an input of an encryption device is , which then increases the number of C ^ de elements provided with a transition in order to avoid sequences of successive seamless code elements without both of the directly successive code elements having a transition in the erii-äl ^ itsii state variable ^

The arrangement thus contains as basic building blocks a coder which forms the code words "_s" and an encryption device, which greatly reduces the possibility of long, seamless code element sequences in the medium This results in an optimally functioning and yet uncomplicated arrangement. In principle, the object of the invention is thus achieved on the one hand by changing code elements and on the other hand by adding code elements.

PHN 8061 - 5 -

BO3884 / 1040

2629798

It is advantageous if the encryption device contains a scrambler that receives code elements serially and to avoid sequences of successive seamless code elements changing the value of the code elements without directly consecutive code elements both signify a transition from which scrambler an input shift register is controlled by a clock pulse train of a clock generator with which code elements received therein are isochronous, wherein an output of the shift register is connected to an input of a scrambling element. and taking the information of the input shift register a blocking circuit activated to allow only part of the mentioned clock pulses to pass to the scrambler, with an output of the scrambling element is connected to the medium. So only code elements are changed, which increases the efficiency maintains.

It is advantageous that the coder delivers pulse-shaped signals and between the coder and an input of the scrambler a two-parter is connected, and that the scrambling element emits static signals and via a Change-of-state coder with the Medium is connected. By adding these further parts and coordinating them with one another, a very advantageous one results System in which code elements with a status change are always replaced by one or more code elements without Change of state can be separated from each other, with the possibility of seamless sequences of many code elements is very low. The aforementioned separation enables the transmission speed in the channel to be increased unchanged frequency response (or the write density in a "magnetizable medium). This offers in the field of physical Properties of the medium a possibility for better utilization of the capacity.

PHN 8061 - 6 -

BO9-B4 / 1Q40

With regard to the state of the art, US Pat. No. 3,647,964 describes a coder in whose code alphabet an unlimited sequence of code elements "Ο" is permitted and in which successive elements ^B 1 ^{n are} always separated from one another by at least one code element "0 ™ The latter, however, does not apply between successive code words, so that the combination of a simple, short alphabet, a high degree of efficiency and the avoidance of directly successive code elements with transition, with the possibility of long sequences of seamless code elements being low, is not achieved also, all of the code words have the same length, so that a large code alphabet (many words) is required, which of course leads to a complicated coder.

US Pat. No. 3,685,033 also gives a code conversion on, which allows for shorter code alphabets; however, two code elements "1;" can also follow one another directly, so that the information density cannot be increased. In addition, the number of consecutive code elements is "0 ™ set an upper limit; this makes the code words relatively long.

In themselves scrambler from relating to a priority date of February 8, 1964 US Patent No. 3,421,146 and from a recent article by DJ Leeper, ¹¹ A universal digital data scrambler, "Bell System Technical Journal, Vol 52, No. 10, December 1973, pages 1851 ..... 1865. But the measures according to the invention provide the advantageous combination of the following useful properties:

a. There are at least two different code word lengths;

b. At the output of the encoder there is an unlimited number of

FHN 8061 Br. S 0 9 8 8 4/1 0 4 Q

consecutive code elements ⁶¹ O "permitted?

c. According to a first exemplary embodiment, two successive code elements ⁵¹ I "are separated from one another by at least one code element" 0 "and, according to a second exemplary embodiment, by at least two code elements ^{81 O"?}

d. A dicing device is used to re-synchronize applied.

Under "isochronous" is that property of a repetitive one Appearance understood in which the time interval between two significant moments theoretically equals one as such a defined unit interval or an integer multiple of this unit interval.

It is advantageous that an output element of the medium has a two-parter with an input of the scrambler mentioned associated designer, one of which The output is connected to an input of a decoder belonging to the mentioned coder, at the output the one at the input of the Coders recovers received data items and the descrambler emits static signals and connected to an input of the decoder via a status change indicator is. In this way, the original information can be largely symmetrical with the input arrangement with the aid of a Reclaim facility.

It is advantageous that the lengths of the groups of data elements and their in each case corresponding groups of code elements only as 2: behave that the mentioned clock frequency of the repetition frequency in the mentioned input shift register of received code elements corresponds and that under the control of the data content of two successive stages of the input shift

FHN 8061 809884/1040 - ⁸ "

26237 ^ 95

registers a locking unit each at least one clock pulse sua mentioned "/ cubing element locks. So can a simple code alphabet can be realized, whereby the scrambler is also simply 'and the efficiency is greater than according to the known state of the art.

2s it is advantageous that under the control of the data content Ier mentioned two successive shift register stages the blocking unit two each in the event of a state difference Blocked clock pulses and otherwise one clock pulse each blocked. In this way, the scrambling element can be controlled in a simple manner.

It is advantageous that the coder separates successive code elements of a first value that would cause a transition by at least two code elements of the other value without an upper limit being set for the successive occurrence of a sequence of code elements of this other value the amounts expressed in Elementan-2shlen lengths of the groups of data elements and ier them .jeweils corresponding groups of code elements only ■; Fi® "i ι 2 behave ₉ that said clock frequency of the re-Iiolungsfrequenz in said input shift register corresponds to received code elements, and that under the control of of the data content of three consecutive stages of the input shift register, a blocking unit blocks at least two consecutive clock pulses to the scrambling element mentioned in a hurry if, under the control of the data content of the three consecutive shift register stages mentioned, the locking unit in a different state of the first shift register stage with respect to the other two of the three consecutive shift register stages mentioned four, in a different state of the third shift register

609 * 84/1040

2623799 Λ

stage three, and otherwise two clock pulses are blocked. The scrambling element is controlled so only a little more complicated than previously described.

It is also advantageous if the encryption device contains an output device that receives code elements and for avoiding sequences of successive seamless code elements of a predetermined number of code elements adds a code element with a transition and a code element without a transition in series, one after the other, without that directly successive code elements would both mean a transition. In this way sequences of seamless code elements that are too long are avoided. The efficiency drops a little, but it will show that it can still be elected high enough «,

Embodiments of the invention are explained in more detail below with reference to the drawing. Show it

1 shows a first exemplary embodiment according to the invention in a block circuit,

Fig. 2 shows a second embodiment according to the invention in a block circuit,

3 shows a diagram of a coder,

FIG. 4 is a clock pulse diagram for FIG. 5,

FIG. 5 is a diagram of a scrambler for FIG. 3,

FIG. 6 shows a time diagram for FIG.

Fig. 7 shows a decoder to Fig. 3 $

8 shows a second scrambler,

Fige, 9 ®i & ZeiMiagE ^ asiäi zn Figo S _P

WEM SOSI 6 U 8 H> U / 1 0 I D

10 shows an output device,

11 shows a data scheme for the scrambling element according to FIG Fig. 5.

A coding is first described in which successive transitions of the mentioned state variable of the medium can occur at distances T, 3 / 2T, 4 / 2T, 5 / 2T ... from one another, so that the unit T / 2 is the length of a code element. It can be proven that with an infinite maximum length of the code words (and thus with a correspondingly complicated coder) an efficiency improvement of 38 % can be achieved with respect to the usual NRZ-1 coding. The following is an exemplary embodiment of a very short code alphabet with an associated simple coder _9, which already results in an approximately 33 % greater efficiency: the efficiency of the illustration is 2/3 (two data elements are mapped onto three code elements), but in the best case can Depending on the channel properties, the transmission speed can be doubled in that two code elements with a transition can never be in direct succession.

Data words code words

11,000

10 010

01 100

0011 001000

0010 001010

QOGI 101000

0000 101010

DCBA PQMMLK

The data elements are in this example in one from the left

'Ss2t 8061 109 ^ 4/1040

right-going order received. If one of the first two is a logical "1 ^M ", the first three lines are valid. If there is no logical "1", another two data elements must be received before a complete code word can be composed. Each code word with three or six code elements ends with a code element ⁸¹ O "(no transition), so that one or more code elements ⁸¹ O" ^{always occur between successive code elements 61 I ".} Since the code word 000 also occurs, there is no upper limit to the number of code elements "0" occurring in a closed sequence. Of course, this is only one of the possible code alphabets within the scope of the invention. Code words of the same length can be interchanged and they can all start with a code element "0" instead of ending with it. One of the two columns can also be read from right to left. However, the group of seven data words includes all possibilities.

Two embodiments of the invention will now be described, one with a scrambler in which the information of code elements are changed, and one with a facility in which additional code elements are assigned with a transition will.

Fig. 1 shows a first embodiment of the invention in block diagram form for use in a data storage system with a magnetic tape. The data elements arrive via the input terminal 70, for example from a central processing arrangement for data from, to the coder 71, which forms data words therefrom and converts them into code words according to the coding scheme specified above. For the time being, a code element "1" through a pulse and a code element "0" the lack of momentum can be represented. This does not affect the later transmission through the channel. These code elements reach the two-parter 72 serially. The

PHTi 8061 609884/1 (UO- -12-

Output signals of this two-divider (e.g. a flip-flop) reach the scrambler 73. As will be described in more detail later, it takes two or, if necessary, three channel symbol time intervals together without changing the position of the two-divider and generates a clock pulse for a scrambler in the scrambler, which the Code information scrambled. The output signals of the scrambling element reach a state change indicator which contains a delay line 74 with a delay time which corresponds to the length of a channel symbol (WS) . The output signals of the element 73 and the delay line are fed to the exclusive OR gate (modulo-2 adder) 75 whereby the elements 74 and 75 together only emit a signal when a change of state occurs in their input signal. The output signal of the gate 75 reaches the magnetic tape 77 via a write amplifier 76 and is stored in the magnetic tape 77. The code elements stored in the magnetic tape can be read by the read head and the amplifier 78 connected to it, which generally has a differentiating effect, so that pulse-shaped output signals which are fed to the two-divider 79 occur. The output signals of the divider reach the descrambler 80, which is implemented with regard to the scrambler 73, so that the changes introduced by the scrambling process can be reversed. The output signals of the descrambler reach the elements 81 and 82, which can correspond structurally and functionally to the elements 74 and 75 and in this way form a status change indicator. The output signals of the gate 82 reach the decoder 83, which is implemented in connection with the coder 71, so that the original data elements can be restored at the output terminal 84, for example for use in the aforementioned central data processing system or in another user arrangement. The magnetic tape device 77 can be replaced in a corresponding manner by a line connection with transmit and receive amplifiers 76 and 78

PM 8061 609384/1040 - 13 -

the. In certain cases, the receiving element 78 has no differentiating effect: then the two-parter can also remain under.

Fig. 2 shows a second embodiment of the invention in a block circuit. Additional code elements are inserted here. The data elements reach the coder 71 via the terminal 70. The output signals of the coder reach the buffer register 85. If the buffer register has a certain degree of filling, for example contains 12 code elements, this is detected and these 12 code elements are transferred in parallel to the output register 87, which also receives a code element 1 and a code element from the code generator 86, in such a way that two code elements never follow one another directly in the end result. In the example of a code alphabet given earlier, the mentioned code element 1 of the encoder 86 would directly border the code element K described. The output signals of the output register 87 reach the medium 77 (the devices 76 indicated in FIG. 1 and are omitted for the sake of simplicity). The read-out signals arrive at register 88. When it has serially received 14 code elements, this is detected and the code elements are fed in parallel to register 90 and the final arrangement 89, which works, for example, as a register, with the insignificant code elements fed (from element 86) to these Final arrangement arrive and no longer be used. The signals of the register 90 reach the output terminal 84 via the decoder 83. The addition of the two additional code elements reduces the efficiency by a factor of 12/14, but an improvement has been achieved with the transmission speed of the channel symbols increased by a factor of 2. In addition, no more than 13 consecutive code elements 0 can occur in a closed manner. In general, this number will not be too high for a suitable synchronization. In other cases

PHK 8061 609 884/1040

it will be advantageous to give the registers 85 and 90 a different capacity, for example of 9 or 15 bits.

Fig. 3 shows a schematic of an encoder having a data input terminal 1, a shift register 2 with stages 3, 4, 5 and 6, a clock generator 7, two divisors 8 and 9, two logical AND gates 10 and 11, three logical OR gates 12, 13, 251, a delay element 25, a shift register 14 with stages 15, 16, 17, 18, 19 and 20 and a data output terminal 21 contains. FIG. 4 shows the clock pulse sequences used in the circuit according to FIG. 3 on three lines 22, 23 and 24.

At terminal 1, the data elements are in accordance with the above-described Organization received. The shift register 2 is controlled by the clock pulses according to FIG. 4, line 22. The divider 8 receives the clock pulses according to FIG. 4, line

After the first clock pulse on line 22, the stage contains the first data element. After the first clock pulse on the Line 23 switches the bistable two-part 8 to the "1" position. Included after the second clock pulse on line 22 levels 3, 4 the first two data items. If at least one of these two is a logical "1", the corresponding one is "1" output asserted and OR gate 12 provides a logic "1" signal to indicate that the first code word to be formed contains only three channel symbols. In this case, the level 3 contains the data item A and the level 4 the data element B of the transcoding example described earlier, The next clock pulse on line 23 resets the two-divider 8 to the zero position and initiates Carry output signal to the divider 9, which thereby switches to the "1" position, and also (a little later) to the logical AND gate 10, whereby the gates 11 and 13 receive a logic "1". The output signal of the gate 10 also brings the two-divider 9 into the zero position

PHN 8061 803884 / 104G "-15-

^ 2529799

Via the OR gate 13, the shift register stages 15 » 16 and 17 activated to accept input information, whereby the following functions are implemented:

IC (level 15): = 0 (by a singing terminal on a fixed

Potential)

L (level 16): = S (level 3)
M (level 17): = S (level 4).

Here, the symbol means: = in a known way to carry out a data change. If none of the stages 3 and 4 contain a data element "1" after the second shift pulse, however, nothing happens, because in this case the data word to be formed has a length of four bits. The two-part 9 also remains in the "1" position. After the following third clock pulse on line 23, the divider 8 switches to the "1" position. After the fourth clock pulse on the line, stages 3 »4, 5 and 6 contain the data elements A, B, C and D. After After the fourth clock pulse on line 23, the divider 9 switches back to the zero position and emits a carry output signal, which directly activates the shift register stages 18, 19 and 20 and, via the ODSR gate 13, the shift register stages 15 »16 and 17 for accepting input information This pulse is also fed to the reset input of stage 17 via delay element 25, whereby it returns to the zero position even if one of stages 3 and 4 had contained a data element "1." Otherwise the output signal of the element would 25 lead directly to the relevant reset input. This is how the following functions are implemented:

K (level 15): = 0

L (level 16): = 5 (level 3)

M (level 17): = 0

N (level 18): = 1

PHN 8061 609884/1040 "-16-

O (level 19) ί = Ο

P (level 20): = S (level 4)

Inversion is achieved by connecting to the inverted output of stages 3 and 4. The constant signal input terminals for stages 15 »13 and 19 are connected to non-illustrated, unchangeable signal sources. The shift register 14 receives the clock pulses on the line 24 with a return frequency 50% higher than on the line. The delay through element 25 may correspond to 1/3 clock pulse interval on line 23. Levels 5 and 6 can be omitted if necessary. The coder described serves only as an example of the element 71 in FIGS. 1, 2. It is also possible to use an exclusively combinatorial circuit. On the other hand, the coding can also take place with a permanently stored table, for example in a read-only memory.

Figure 5 shows a block diagram of a scrambler for use in an arrangement according to FIG. 3 with a clock generator 7 (see FIG. 3), a source for code elements 210, a Shift register 26 with stages 27, 28, 29, 30, an exclusive OR gate 31, an inverter 32, four logical AND gates 33, 34, 39, 40, a logical OR gate 41, two Delay elements 35 and 36, a scrambling element 42 and an output terminal 43. In this connection, FIG. 6 shows a timing diagram in which line 63 represents the sequence of indicates signal elements originating from the coder 71, in which, as previously assumed, there are never two elements with the value "1" can occur together within an elementary unit of time T. In this case, signal elements of line 63 with the value "1" represented by a pulse (line 63A), signal elements "0" represented by the absence of a pulse.

PHN 8061 609 3 84/1040 -17-

- YI -

The line 64 shows the output level of the signals of the two-divider 72, whereby (line 44) the convention in contrast to line 63 (A) is such that a "1" element corresponds to a high signal and an "O ^lt element to a The clock generator 7 can correspond to the clock generator 7 according to FIG. 3 and thus controls the source for code elements with a clock pulse sequence with a frequency according to FIG Divider 72. The shift register 26 receives these clock pulses, for example according to Fig. 6, line 49. It is now assumed that one of the gates 39 or 40 passes a clock pulse to the output of the OR gate 41. If the stages 27 and 28 have the same information contained, the exclusive-OR gate 31 gives a logic "0" signal, the inverter 32 a logic "1", so that the AND gate 34 is open and the delay element 36 starts. This element conducts the at its egg Incoming received signals true to form at its output with a delay time which corresponds to the length of two clock pulse intervals on line 49, so that the next clock pulse is blocked and only the following second is allowed by gate 40. However, if levels 27 and contain different information, that gives

Exclusive OR gate 31 has a logic "1" signal, so that

the AND gate 33 is conductive and the delay element 35 is started. This element conducts at its entrance received signals true to the form at its output with a delay time that is the length of three clock pulse periods on line 49, so that the next two clock pulses are blocked and only the following third Clock pulse from gate 39 is passed. The output pulses from gates 39 and 40 control via the OR gate the scrambler 42 on. This scrambling element largely corresponds to the description in the reference Article by Leeper. It contains two exclusive-OR gates or

^PHN8061 609634/1040 " ¹⁸ "

Modulo-2 adders 421 and 422 and in this simple case five shift register elements 423 ... 427, their information can be shifted by one place in each case under the control of the gate 41. The modulo-2 adders take care of it for feedback. If the input information from Modulo-2 adder 421 is passed on, it appears at output 43.

FIG. 6 is a timing diagram of the above description. Line 47 shows the code elements stored in FIG Stage 27, lines 46, 45, 44 the stored code elements for stages 28, 29 and 30. Line 49 gives the clock pulse , with which the phenomena on lines 44 ... 48 are isochronous: a signal change occurs on these lines always coincident with a rising clock pulse edge. Line 48 gives the output of gate 31. On the Line 50 assumes that the first clock pulse is passed, which of course is determined by the history will. Line 48 is low because lines 47 and 47 both indicate a high signal. This is the gate 34 permeable, and only one clock pulse is blocked. On line 51 it is assumed in the same way that the first Clock pulse is blocked. At the next clock pulse the elements 27 and 28 have different information, so that the Element 35 blocks two clock pulses. From this moment on, lines 50 and 51 are identical. It follows from this that the further possible passage of clock pulses depends exclusively on the information received and also no longer from the previous history mentioned above.

FIG. 11 shows an information scheme for the scrambling element 42 according to FIG. 5. The columns 30, 423, 424, 426 and 427 give the output information of the elements from the circuit according to FIG. 5 with the same reference numerals. The first line contains any starting position. The input information

PHN 8061 8G9884 / 104Ö -19-

- Λβ -

-tion is that of line 64 in Fig. 6 (also line 44), where in each case at the location of a point by a clock pulse on the line 50 according to FIG. 6 a notch is created: so two or three bits with the same data content on line 64 combined. Exclusive OR gates 421 and 422 directly determine the output information that corresponds to the output information shown here in column 423. In the second line according to Fig. 11 this becomes: (1 + 1 + 0) Mod 2 = O. In the third line: (0 + 0 + 1) Mod 2 = 1, while the information generated moves forward by one column position. This initial information is on of line 65 in FIG. 6. The elements 74 and 75 (state change indicator) of FIG. 1 further form at each Signal change on line 65 a code element 1 on line 66, with which the write amplifier 76 is controlled to to reverse the direction of magnetization in band 77. If the signal to be transmitted affects a signal level, the Elements 74 and 75 are omitted. For example, two consecutive code elements 1 do not appear on line 66 while the probability of a long sequence of consecutive code elements 0 is greatly reduced, see the last part of line 64, which still causes transitions in line 66. By practicing a long series of feedback Elements 423 ... 427 are included in the scramble element, the possibility of a long sequence more seamless Code elements can be reduced in size as required. The element 79 is analogous to the element 72, so that from the read Signal (line 66) the signal of line 65 is formed again. The specific properties of elements 76, 77 and 78 do not represent a limitation of the invention and are not described in detail. The element 80 is one with the Element 73 coupled designer. This means that the The scrambling element is constructed differently (see the article by Leeper), but that the elements according to FIG. 5 in FIG of the same design and configuration, the element 210 corresponding to the two-part 79.

PHN 8061 609884/1040 ~ ²⁰

With regard to the scrambling element, there is also a chain of five shifting elements ₉ of which the outputs of the third and fifth are fed back for a modulo-2 gate, the output of which is coupled to a further modulo 2, which also receives the input signal and the output signal supplies «On the other hand, however, the input signal is fed directly to the first slide element. In general, the designs of the scrambling and descrambling elements must be adapted to one another. The passing and blocking of clock pulses is carried out in the same way as in FIG. 5. Elements 31/82 correspond to elements 74/75. Thus the information of Figure 6, line 63, is restored.

ig. 7 shows a decoder for FIG. 3, which has a Singangsklemme a shift register 92 with stages 93 ... 98, a Singangscounter 99 with stages 100 ... 106, a delay element 107, a clock generator 109, logical GDSR gates 108, 11 and 113, logical AND gates 110, 112, 114 and 115 as well as a shift register 116 with stages 117 ... 120 and an output terminal 121 contains.

The code elements (see also Fig. 6, 1st line, reach the Singangsklemme 91 in an order that is specified earlier Table corresponds to a direction from left to right. The shifting in shift register 92 takes place under the control of the clock 109 from the same clock pulses that are also sent via the OR gate 108 to the ring counter move on. Only one stage of this ring counter always emits a logical "1" signal. In the initial position is it the stage 100. Under the control of the first clock pulse, the first code element is included in the stage 93, and the stage 101 switches to the "1" position Controlling the second and third clock pulses, the input counter stage 103 is brought into the "1" position, wherein the first three code elements cover levels 95, 94 or 93

PHN 8061 609884/1040 ~ ²¹ ~

- 34 -

If then stage 93 contains a code element 0, the AND gate 110 receives two logic "1" signals and indicates that it is one of the first three cells of the mentioned table is: element K = O. The following logical functions are carried out:

A (level 117): = L (level 94) B (level 118): = S (level 95)

The gate 112 is used via the gate 111 to fill the stage 117 with the inverted information (output 0) of the stage made transparent, gate 114 is used to fill stage 118 with the inverted information of stage 95 the gate 113 made permeable. In addition, the output signal of the gate 110 via the line 122 sets the ring counter 99 to the zero position, possibly with a slight delay, so that the process can be restarted can. However, if the aforementioned gate 110 does not receive two logical "1" signals, it is one of the four last lines of the table concerned, and the corresponding code word contains six bits. For the time being nothing happens but through the next three clock pulses the stage 106 finally outputs a logical; 1 ", while the code elements take steps 98 ... 93 one after the other »

At this moment the following logical functions are carried out:

A (level 117): = L (level 94)

B (level 118): = P (level 98)

C (level 119) 5 = 0

D (level 120): = 0.

Thereupon the gate 112 is set to the same via the gate 111

N 8061-22

S Λ Ci ^f-1 Q / / ^ ¹ I / Ί U υ OO 4 /! iJ "■ '." J

Way made permeable as previously described. Next, gate 115 is used to fill stage 118 with the inverted Information of the stage 98 through the gate 113 made transparent. Levels 119 and 120 are not specifically grounded controlled and can be omitted if necessary. It is assumed that the stages 117 ... 120 with a clock pulse from the clock 109 are controlled, which clock pulse is two-thirds of the frequency of the shift register 92 supplied clock pulse corresponds, without clock pulses in an analogous manner, as described in FIGS. 3 and 4, disturbing interact. In each case, level 117 is filled with the information 0, while levels 117 and 118 can then necessarily be overwritten with the information 1 from the gates 112 and 113. The data elements are restored at output 121; this notice can, for example, be directly connected to the output 84 according to FIG. 1 to match. The output signal of the stage 106 is with a short delay time via the element 107 and the gate 108 fed to the ring counter 99, whereby it is reset to the zero position.

A coding is then described in the case of the successive Transitions of the state variable of the medium can occur at intervals T, 4 / 3T, 5 / 3T, 6 / 3T ... from one another, where 1 / 3T is the length of a code element. A particularly short code alphabet is given below, which means that a considerable improvement in efficiency is achieved.

Data elements Code elements (Words) (Words) 0 00 10 0100 11 1000

UT UXWV

6 0 9 3 8 4/1 υ -k o

Each group of two or four code elements ends with two code elements ¹¹ CO "(no transitions), so that two or more code elements" 0 ⁿ always occur ^{between successive code elements 5I} 1 ^{! I.} Since the code word ^M 00 "also occurs, the number of code elements ^M 0" occurring one behind the other has no upper limit. Again, this is only one of the possible alphabets within the scope of the invention. In terms of structure, the coder can be analogous to the coder according to FIG. 3, but it is even simpler because at most two data elements need to be translated together into one code word. Since two code elements now always occur between successive code elements 1 (or more), the transmission speed can be increased by a factor of three at most, depending on the circumstances (here, too, only code elements 1 contain a state transition). This increases the transmission speed of the data bits by at most a factor of 1 ^ and the channel capacity is accordingly better utilized.

The coder for forming the code words can be constructed in the same way as in FIG a simpler structure results. The logical functions to be carried out \ * ground when coding:

a. first received data bit is zero:

V: = 0
W: = 0

b. first received data bit is not zero: wait until the second data bit is available:

V: = 0
W: = ΟΧ: = Ϊ

V: = T

^PHl18061 609884/1040

When decoding, a corresponding, simple logical Apply function.

In this code, FIG. 5 shows a scrambler which is largely constructed analogously to that of FIG. The circuit includes a clock 7 and a source of code elements 211 which meet the above-mentioned conditions, further a shift register 52 with stages 53, 54, 55, 56, 57 and 58, two exclusive-OR gates 61 and 62, one NI HT-ODKR gate 59, six logical AND gates 122, 123, 124, 128, 129, 130, a Scrambling element 42 with an output 43 (corresponding to FIG. 5), three delay elements 125, 126, 127 and a logical OR gate 60. The clock frequency is equal to the repetition frequency of the code elements. When a clock pulse is passed to the scrambling element 42 and the shift register elements 53, 54, 55 all the same information none of the exclusive OR gates 61 and 62 are logical "1", so that the logical NOR gate 59 through the output of a logical "1", the gate 122 permeable power. The element 125 routes the received clock pulse true to form and with a delay time of three clock pulse periods to AND gate 128, whereby the next two clock pulses are blocked before the third is let through. If the level information is different (one "zero" versus two "ones" or one "One" versus two "zeros"), the logical exclusive-OR gate 62 outputs a logical "1", and the gate 124 is permeable to a clock pulse. Element 127 creates a delay like element 125, but of four Clock pulse periods so that the next three clock pulses are blocked and only the following fourth is allowed through by the AND gate. If the information for level 53 is different is, the exclusive OR gate 61 outputs a logic "1", and the gate 123 is permeable to a clock pulse, the element 126 with a delay of five

609834/1040

- 35 -

Forward clock pulse periods so that the next four clock pulses are blocked and only the following fifth is allowed through. It is not possible for more than one of the gates 59, 61, 62 to emit a logic ⁿ 1 ⁿ ~ signal at the same time.

For the above description, FIG. 9 shows a timing diagram in a manner corresponding to FIG. 6 for the first described coding example. Line 131 shows the output signals of the coder, an ^M 1 "indicating a pulse-shaped code element. Line 132 gives the output signals of the two-parter (cf. element 72 in FIG. 1), in which transitions between successive zeros and ones occur Lines 133, 134 ... 138 give the information content of the elements 58, 57, 56, 55, 54 and 53 respectively. The line gives the output signal of the gate 59. The line 140 gives the output signal of the gate 61. The line 141 gives that Output signal of gate 62. Line 142 gives the clock pulses of the clock generator with which the signals on lines 133 ... 141 are isochronous: Elements 1 on line 131 follow each other at intervals of at least three clock pulse periods. Lines 143, 144 and Examples of possible configurations of the output clock pulses are given in 145. It is assumed that the first clock pulse is allowed through on line 143. All stages 53 ... 55 contain the information 0, s o that two clock pulses are suppressed. The same applies to the third clock pulse, so that again two are suppressed. On the line it is assumed that only the second clock pulse is allowed to pass. The gate 61 outputs a logic "1" so that four clock pulses are blocked. After that, the situation is identical to that of line 143. On line 145 it is assumed that only the third clock pulse is allowed to pass. In this case, the gate 62 outputs a logic "1", so that three clock pulses are blocked. After that is the situation

PHN 8061 - 26 -

609884/1 040

identical to that of lines 143 and 144. So that's enough a single output line that has a clock pulse control there, after a brief introduction to the history is still independent. The line 146 then yields the end signals of the scrambling element 42 FIG. 5, which started with the same data content as in FIG. 11. Line 14? gives the output signals of the State change indicator (for example, elements 74 and 75 in Fig. 1). With regard to the remaining circuit sections An example relating to the first code is given in FIGS. 3 to 6.

Fig. 10 shows, as part of the circuit of Fig. 2, an output arrangement, which can be used with both codes described, but especially in connection with the circuit according to Fig. 3 is described. At terminal 131 of this arrangement, the code elements, i.e. from terminal 21, receive. The corresponding Clock pulses received and counted in counter 134. When it reaches position 12, the routing arrangements become 140 and 139 activated, and the information of the shift register 132 and the code generator 100 v / earth in the shift register 137 saved. As a result, when the last stage of shift register 1321 contains a logic 1 the element 139 is controlled in a non-inverting manner, so that the last stages of the shift register 137 contain the information 101 contain. However, if it contains a 0, the element is controlled in an inverting manner, so that the last stages of the shift register 137 contain the information 010. This control is necessary because the last received Bit both a "1", the bit "N" from the table given earlier, as well as a "0", then so it is the "K" bit. It is not possible for two elements 1 to appear one after the other at output terminal 138, while at most 13 consecutive elements

PHN 8061 - 27 -

609884/1040

can be generated. The extra bits can be "at the beginning." or at the end of a sequence of twelve DatenMts. The clock pulse converter 136 receives the pulses of the Clock (terminal 135) and multiplies the clock frequency by 14/12. Such elements are known per se.

PATENT CLAIMS:

609884 / 1CUQ -28-

Claims (11)

PATENT CLAIMS ι 1. Arrangement for transmitting binary data elements via a medium or for storing binary data elements in a medium by means of a two-valued state variable of this medium, which data elements in a bit cell sequence can be freely received at an input of an existing coder which received data elements are each group alternatively at least two different numbers of data elements (Data words) and from these groups from the coder each corresponding to a data word, but larger numbers of code elements Let (code words) be formed in a sequence of channel symbols, and a code element possibly being one occurring transition between the two values of the state variable, characterized in that the coder successive Code elements of a first value that would cause a transition in the mentioned state variable, separated by at least one code element from the other value without the successive occurrence of a code element sequence this other value has an upper limit that further the output of the encoder with an input of an encryption device that is to avoid sequences of consecutive seamless code elements the number of code elements provided with a transition is then increased without directly successive code elements both show a transition in the mentioned state variable. 2. Arrangement according to claim 1, characterized in that the encryption device contains a scrambler which receives code elements serially and changes the value of the code elements to avoid sequences of successive seamless code elements without directly successive code elements both signifying a transition from which scrambler an input shift register nude of a ^{T FHH80S1} 609384/1040 pulse train of a clock is controlled with the code elements received therein are isochronous, with an output of the shift register is connected to an input of a scrambling element, and wherein the information of the input shift register a blocking circuit activated in order to only send a part of the mentioned clock pulses to the scrambling element to pass, an output of the scrambler connected to the medium. 3. Arrangement according to claim 1 or 2, characterized in that the coder delivers pulse-shaped signals and between a two-parter is connected to the coder and an input of the scrambler. 4. Arrangement according to claim 1, 2 or 3, characterized in that the scrambling element emits static signals and is connected to the medium via a change-of-state indicator. 5. Arrangement according to one of claims 1 to 4, in which the medium is read differentially, characterized in that an output element of the medium has a two-parter is connected to an input of a designer associated with the scrambler mentioned, an output of which is connected to a The input of a decoder associated with the coder mentioned is connected, and the data elements received at the input of the coder are output at the output restores. 6. Arrangement according to claim 5, characterized in that the descrambler emits static signals and via a State change indicator is connected to an input of the decoder. 7. Arrangement according to one of claims 2 to 6 _? characterized in that the expressed in numbers of elements PHN 8061 60SH84 / 1040 - 50 - Lengths of the groups of data elements and their respective corresponding groups of code elements behave only as 2: 3, that the mentioned clock frequency of the repetition frequency in the mentioned input shift register received Code elements corresponds and that under the control of the data content of two successive stages of the Singangsshiftregister a blocking unit blocks at least one clock pulse to the aforementioned scrambling element. 8. Arrangement according to claim 7, characterized in that under the control of the data content of the two mentioned successive shift register stages the blocking unit "blocks two clock pulses in the event of a state difference and otherwise blocked one clock pulse at a time. 9. Arrangement according to one of claims 2 to 6, characterized in that the coder is successive code elements of a first value that would cause a transition by at least two code elements of the other value from one another to separate without the successive occurrence of a sequence of code elements of this other value an upper limit is set that the lengths of the groups of data elements and the groups of code elements corresponding to them behave only as 1: 2 that the mentioned clock frequency of the repetition frequency in the mentioned input shift register received code elements and that under the control of the Data content of three successive stages of the input shift register a locking unit each at least two successive clock pulse © to the scrambling element mentioned locks. 10. The arrangement according to claim 9 _}, characterized in that under the control of the data content of said three successive shift register stages, the locking unit PHK 8061 609884/1040 - 31 - in the case of a different state of the first shift register stage with respect to the other two of the three successive ones mentioned Shift register stages four, if the state of the third shift register stage is different, three, and otherwise two clock pulses are blocked, 11. The arrangement according to claim 1, characterized in that the encryption device is an output device that receives code elements and, in order to avoid sequences of consecutive seamless code elements, a predetermined number of code elements in series in each case directly following one another code element with a transition and a Adds a code element without a transition without thereby both directly successive code elements signifying a transition would. 6098 8 A / 1040