SU1115043A1 - Device for executing input and output of information varying in dynamic mode - Google Patents

Abstract

DEVICE FOR INPUT AND OUTPUT DYNAMICALLY CHANGING INFORMATION, containing an input storage unit, a command analysis unit containing a counter, register, pulse frequency divider, decoders block and AND element, counter, write address generator, containing three registers, pulse frequency divider, two accumulators adder, a fixed memory, three counters and an OR element, two decoders, a register, a switch chip, a memory selector block containing a counter, a decoder, a register, and a fixed memory, a block of And elements, synchronized torus and two groups of P memory blocks (), where the information input of the input storage unit is the input of the device, the read-write input of the input storage unit is connected to the first output of the first synchronizer output group, the address input of the input storage unit is connected to the information output of the analysis unit counter commands, the information input of which is connected to the information input of the register of the instruction analysis block and with the first output of the input memory block, the second output of which is connected to the information the input of the first register of the write address generator and the third counter of the write address generator and with the information inputs of the first and second counters of the write address generator, the third output of the input storage unit is connected to the information register input of the device, the count input of the pulse frequency divider is connected to the second output of the first group synchronizer outputs, the first (second and second outputs of the decoder of the command analysis block, are connected respectively to the register write / read input) and with the recording inputs of the first register of the address generator and the first, second and third counters of the recording address generator, the clock input of the pulse frequency divider of the recording address generator U1 is connected to the third output of the first group of synchronizer outputs, 4 count input of the command analysis block is connected to the register recording input the command analysis unit and the output of the element AND the analysis unit co .mund, the first and second outputs of which are connected respectively to the output of the pulse frequency divider of the command analysis unit and tim decoder output command analysis block having an input connected to the output command analysis unit register nye informational outputs of the second and third ELAPSED

Description

the write address driver is connected to the first and second inputs of the first and second decoders of the device, respectively; the output of the first register of the write address generator is connected to the address input of the back memory of the back address generator, the output of which is connected to the information inputs of the second and third registers of the write address generator, outputs which are connected respectively with the information input of the first accumulating adder and with the information input of the second accumulating adder, the synchronization inputs which are connected to the counting inputs of the first, second and third counters of the write address generator, and the first output of the pulse frequency divider of the write address generator, the second output of which is connected to the read enable input of the write memory, and the write addresses of the second and third registers shaper address records, the outputs of the first and second accumulating adders are connected respectively to the information inputs of the lower bits of the first and second counters shaper address for The overflow output of the third counter of the address resolver is connected to the first input of the RSHI element of the write address inverter, the output of which is connected to the blocking input of the operation of the pulse frequency divider of the write address inverter, the fourth output of the first group of outputs of the device synchronizer is connected to the counter input of the device counter, first, second , the third and fourth information inputs of the first and second switches are connected respectively to the output of the second decoder of the device, with the fifth output of the first g The device synchronizer outputs, with the first output of the device register and the second output of the device register, the control inputs of the first and second switches are connected to the output memory group of the memory selector unit, the outputs of the first and second switches are connected respectively to the information the inputs of the memory blocks of the first and second groups, the sixth and seventh outputs of the first group of outputs of the device synchronizer are connected respectively to the counting input of the counter of the memory selector unit and to the control input ohm of the third switch, the first and second information inputs of which are connected respectively to the outputs of the memory blocks of the first and second groups, the group of information outputs of the counter of the memory selector unit is connected to the input group of the decoder of the memory selector unit, the group of outputs of which is connected through the memory selector register with the group of address inputs of the permanent memory of the memory selector unit, the output of the third switch is connected to the information input of the fourth switch, the control group of 1x inputs of which is connected to the second the group of outputs of the device synchronizer, the output of the fourth switch is the output of the device, characterized in that, in order to increase the speed, it additionally contains the fifth sixth, seventh and eighth switches, two executive address generators, each of which contains four switches and two registers, a shaper of operation modes containing two decoders, a shaper of recording conditions containing a comparison circuit, a decoder, an OR element and an AND element, the group of information outputs of the counter y The device is connected to the first groups of information inputs of the first, second and third switches of each driver of the address executive and with groups of inputs of the first and second decoders of the driver of operation modes; the first input of the second group of information inputs of the first switch of each former address generator is connected to the first input of the first group of information inputs of the fourth the switch of each driver of the executive address, with the information output of the first counter of the driver of the hell ENA recording, the first input of the first group of information inputs of the comparison circuit and the first input depmfratora shaper recording conditions, the second input of the second group of information inputs of the first switch kavdogo shaper effective address is connected to a second input of the first group

information inputs of the fourth switch of each generator of the executive address, with information output of the second counter of the write address generator, with the second input of the first group of information inputs of the comparison circuit, and with the second input of the decoder of the recording condition generator, the eighth output of the first group of outputs of the device synchronizer connected to the control inputs of the first, the second, third and fourth switches of the order shaper of the executive address second groups of information inputs of the second and third The other switches of each executive address generator are connected to the output group in the permanent memory of the memory selector unit, to the first groups of information inputs of the fifth, sixth, seventh and eighth switches and to the second group of information inputs of the comparison circuit, the output of which is connected to the first input of the OR conditioner of the recording conditions, the second input of which is connected to the output of the decoder of the conditioner of the recording, the output of the element OR of the conditioner of the conditioner is connected to the first input of the element AND of the former and the second input of the OR of the write address shaper, the second input of the AND shaper of recording conditions is connected to the ninth output of the first group of outputs of the device synchronizer, the output of the And shaper of recording conditions is connected to the fifth information inputs of the first and second switches, the second and the third switches of each former address maker are connected

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respectively, with the inputs of the first and second registers of each shaper of the executive address, the outputs of the first and fourth switches of each shaper of the executive address are connected respectively to the information inputs of the first and second registers of each shaper of the executive address, the output of the first register of each shaper of the executive address is connected to the second information input of the fourth switch each driver of the executive address, the output of the first decoder device is connected to the first control inputs of the fifth and seventh switches, the output of the first decoder of the operating mode driver is connected by the second control inputs of the fifth and seventh switches, the i -th outputs (1,2, ...,) of the fifth and seventh switches connected to the synchronization inputs of the 1st block of the first and second groups, the output of the second decoder of the operating mode generator is connected to the control inputs of the sixth and eighth switches, the outputs of which are connected respectively to the inputs of the reader. The records of the memory blocks of the first and second groups, the outputs of the first and second registers of the first driver of the executive address are connected respectively to the address inputs of the lower and upper bits of the memory blocks of the first group, the outputs of the first and second registers of the second driver of the executive address are connected respectively to the address inputs junior and senior bits of memory blocks of the second group.

The invention relates to electronic discrete devices of automation, telemechanics and computer technology and is intended for input, processing and output of dynamically changing information.

A device for input and output of dynamically changing information is known, which contains an information source connected to a special calculator and a processor that is connected to the synchronizer and connected to an output storage device through a control circuit. Cll The device’s disadvantage is that (in bits) is determined by the maximum information content of the peripheral equipment, which increases equipment costs, energy consumption and reduces the reliability of the product. The closest in technical essence to the invention is a device comprising an input storage unit, a coma analysis unit containing a counter, a register, a pulse frequency divider, a decoder unit and an And element, a counter, a write address generator that contains three registers, a pulse frequency divider, two accumulating adders Permanent memory, three counters and an OR element, two decoders, a register, four switches, a memory selector block containing a counter, a decoder, a register and a permanent memory, a synchronizer and two g Packs of Memory blocks (tlV2), the information input of the input storage block is the input of the device, the read-write input of the storage block is connected to the first output of the first group of synchronizer outputs, the input input of the input storage block is whose information input is connected to the information input of the register of the command analysis block and to the first output of the input memory block, the second output of which is connected to the information input of the first register the address of the write address and the third counter of the address formaker and with the information inputs of the first and second counters of the first and second counters of the write address generator; the third output of the input storage unit — with the information input of the device register; the count input of the pulse frequency divider — with the second output of the first group of outputs the synchronizer, the first and second outputs of the decoder of the command analysis block, respectively, with the write-read input of the device register and the write inputs of the first register of the write address generator and the first second, third, and third counters of a shaper address driver; 34 clock; clock input of a pulse frequency divider; write address addresses — with the third output of the synchronizer's first output; counting input of a command analysis block counter — with a register entry record of a command analysis block and with an output of an And analysis unit element commands, the first and second inputs of which are connected respectively to the output of the pulse frequency separator of the command analysis block and to the third output of the decoder of the command analysis block whose input is connected to the register output the command analysis block, the information outputs of the second and third counters of the write address generator, respectively, with the first and second inputs of the first and second decoders of the device; the output of the first register of the write address generator is connected to. the address input of the memory of the write address generator, the output of which is connected to the information inputs of the second and third registers of the recording address generator, the outputs of which are connected respectively to the information input of the first accumulating adder and information input of the second accumulating adder, the synchronization inputs of which are connected to the counting inputs of the first the second and third counters of the write address generator, and with the first output of the pulse frequency divider of the write address generator, second Its output is connected to the read input of the constant memory of the write address mapper and the write inputs of the second and third registers of the write address maker, the outputs of the first and second accumulators: their adders - respectively, with the information inputs of the lower bits of the first and second counters of the write address mapper , the overflow output of the third counter of the write address generator is connected to the first input of the OR element of the write address generator, the output of which is connected to the blocking input of the work deli the bodies of the frequency of the pulses of the write address generator, the fourth output of the first group of outputs of the device synchronizer is with the counting input of the device counter, the first, second, third and fourth information5. the input inputs of the first and second commutators, respectively, from the output of the second device decoder, with the fifth output of the first group of outputs of the device synchronizer, with the first output of the device register and with the second output of the device register, the group of control inputs of the first and second switches are connected to the group of outputs constant the memory of the memory selection unit, the outputs of the first and second switches are connected, respectively, with the information inputs of the memory blocks of the first and second groups, the sixth and seventh outputs of the first group, the output The device synchronizer is connected to the counting input of the memory selector counter and, respectively, to the control input of the third switch, the first and second information inputs of which are connected respectively to the outputs of the memory blocks of the first and second groups of information outputs of the memory selector counter the inputs of the decoder of the memory selection block, the output group of which is connected through the register of the memory selection block to the address input group of the memory of the memory selector block, the output of the third switch data input of the fourth switch, the group of control inputs of which is connected to the group output vtorby synchronizer device vghod fourth switch is the output device 2. The structure of the known apparatus allows to reduce the volume of the accumulator output due SEQ partitioning it into four zones, controllable independently. In this case, if the contents of the first zone of the output accumulator are counted synchronously with the operation of the peripheral equipment, then in the other three zones, the information is recorded, which will have to be read upon completion of work with the first zone. Such an organization of the output accumulator leads to the need to pre-sort the static information and to the need to solve in real-time software and hardware means of assigning the zones to the output accumulator dynamically changing 3. comprehensive information. This entails additional time spent on pre-sorting information. The aim of the invention is to improve the speed of the device by offloading software and an exchange channel with external computing means. The goal is achieved by the fact that a device for inputting and outputting dynamically changing information containing an input storage unit, a command analysis unit containing a counter, a register, a pulse frequency divider, a decoder block and an And element, a counter, a write address generator that contains three registers, a pulse frequency divider, and two accumulating sum-. tori, fixed memory, three counters and an OR element, two decoders, a register, four switches, a memory selector block containing a counter, a decoder, a register and a fixed memory, a synchronizer, and two groups of memory blocks () the information input of the input storage block is the input of the device, the read-write input of the input storage block is connected to the first output of the first group of outputs of the synchronizer, the address input of the input storage block is connected to the information output of the counter of the command analysis block, the information the input of which is connected to the information input of the register of the command analysis unit and the first output of the input storage unit, the second output of which is connected to the information input of the first register of the write address generator and the third counter of the write address generator and with the information inputs of the first bits of the first and second write address generator , the third output of the input storage unit - with the information input of the device register, the counting input of the pulse frequency divider - with the second output of the first group The outputs of the synchronizer outputs, the first and second outputs of the decoder of the command analysis block, respectively, with the write-read input of the device register and the write inputs of the first register of the address generator and the first, second and. 711 of the third counter of the write address mapper, clock input of the frequency divider pulse of the write address mapper — with the third output of the first synchronizer output group, the counting input of the counter of the command analysis block — with the register entry of the command analysis block and the output of the command AND block of the command analysis,. The first and second outputs of which are connected respectively with the output of the frequency divider imPuLs of the command analysis block and the third output of the decoder of the command analysis block, whose input is connected to the output of the command analysis block registra, the information outputs of the second and third counters of the write address maker are connected respectively to the first and second the second inputs of the first and second decoders of the device, the output of the first register of the write address generator is connected to the address input of the permanent memory of the write address generator, you the course of which is connected to information inputs of the second and third registers of the write address generator, the outputs of which are connected respectively to the information input of the first accumulating adder and information input of the second accumulating adder, whose synchronization inputs are connected to the counting inputs of the first and second write addresses and the first output the pulse frequency generator forms the write address, the second output of which is connected to the read enable input of the read-only memory format the address records of the second and third registers of the write address mapper, outputs of the first and second filament adders - respectively with information inputs of the lower bits of the first and second counters of the write address maker, overflow output of the third counter of the write address mapper - with the first input of the lilDi element of the write address mapper, output which is connected to the input of the blocking operation d JLITER of the pulse frequency of the write address generator, the fourth output of the first group of outputs of the device synchronizer - with s The first, second, third and fourth information inputs of the first and second switches are connected to the input of the second decoder of the device, with the fifth output of the first output section of the device synchronizer, the first output of the device register and the second output of the device register, control group the inputs of the first and second switches are connected to a group of vspodov of the permanent memory of the memory selector unit, the outputs of the first and second switches are respectively with the information inputs and memory blocks of the first and second groups, the sixth and seventh outputs of the first group of outputs of the device synchronizer, respectively, with the counting input of the counter of the memory selector unit and with the control input of the third switch, the first and second information inputs of which are connected respectively with the outputs of the memory blocks of the first and the second group, a group of information outputs of the counter of the memory selector unit, with a group of inputs of the decoder of the memory selector unit, the output group of which is connected through the register of the memory selector unit to the addressable group x inputs of the memory block of the memory selector unit, the output of the third switch is with the information input of the fourth switch, the group of control inputs of which is connected to the second group of outputs of the device synchronizer, the output of the fourth switch is the output of the device, entered five, sixth, seventh and eighth switches, two executive addresses, each of which is co-owned, holds four commissors and two registers, a driver of operating modes containing two decoders, a recording condition driver, and The general comparison circuit, the decoder, the OR element and the AND element, the group of information outputs of the device counter are connected to the first groups of information inputs of the first, second and third switches of each generator of the forward address and the groups of inputs of the first and second decoders of the operating mode generator, the first input of the second group information inputs of the first switch of each driver of the executive address - with the first input of the first group of information inputs

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the fourth switch of each actuator of the executive address, with the information output of the first counter of the write address generator, with the first input of the first group of information inputs of the comparison circuit and with the first input of the decoder of the recording condition generator, the second input of the second group of information inputs of the first switch of each actuator of the executive address with the second input the first group of information inputs of the fourth switch of each generator of the executive address, with information output of the second Forg-shrovele ovo counter; with the second input of the decoder of the write conditioner; the eighth output of the first group of outputs of the device synchronizer — with the control inputs of the first, second, third and fourth switches of each former address generator; the second groups of information inputs of the second and third switches of each shaper executive address — with a group of memory outlets of the memory block selector, with the first groups of information inputs of the fifth, sixth,. the seventh and eighth switches and the second group of information inputs of the comparison circuit, the output of which is connected to the first input of the OR element of the recording conditions, the second input of which is connected to the input of the decoder of the recording conditions shaper, the output of the OR element of the conditions shaper - with the first input of the AND element of the recording conditions shaper and with the second input of the element OR of the write address, the second input of the element AND of the conditioner of the record with the ninth output of the first group of outputs of the device synchronizer, output g element And the driver of the recording conditions - with the fifth information inputs of the first and second switches; the outputs of the second and third of its switches of each driver of the executive address are connected respectively to the recording inputs of the first and second registers of each form of the executive address; the outputs of the first and fourth switches of each driver of the executive 504310 addresses

respectively, with the information inputs of the first and second registers of each shaper of the executive address, the output of the first registrar of each shaper of the executive address — with the second information input of the fourth switch of the shaper of the executive address; output of the first decoder of the device — with the first control inputs of the fifth and seventh switches, outputs the first decoder of the operating mode driver is connected to the second control inputs of the fifth and seventh switches, the 1st outputs (1,2, ..., P ) of the fifth and seventh switches, respectively, with the synchronization inputs of the 1st memory block of the first and second groups, the output of the second

The 20 decoder of the operating mode generator - with the control inputs of the sixth and eighth switches, the outputs of which are connected respectively to the read and write inputs of the memory blocks

25 of the first and second groups, the outputs of the first and second registers of the first driver of the executive address, respectively, with the address inputs of the lower and higher bits of the blocks

30 memories of the first group, outputs of the first and second registers of the second driver of the executive address, respectively, with the address inputs of the lower and higher bits of the blocks

35 memories of the second group.

Figure 1 shows the functional diagram of the device; Fig.2 is a functional block diagram analysis

40 teams; in fig. 3 is a functional diagram of a write address driver; in fig. 4 shows a functional diagram of the memory selection block; in fig. 5 functional shaping circuit

45 recording conditions; in fig. 6 is a functional diagram of the driver of the executive address; FIG. 7 is a functional diagram of the switch in FIG. 8 - functional design of the former mode of operation.

The device contains (figure 1) input storage unit 1, block 2, 5S command analysis, driver 3 write addresses, counter 4, first driver 5 executive address, first decoder 6, register 7, second decoder 8, second driver 9 executive address, shaper 10 peipHMOB operation, fifth 11, first 12 and sixth 13 switches, block 14 memory selection, second switch 15, driver 16 recording conditions, seventh 17 and eighth 18 switches, first 19 and second 20 drives, synchronizer 21, third switch 22, the first group of blocks, memory, toruyu block group (,, chetvetry switch 25, input 26, output 27.

The command analysis code (FIG. 2) contains a counter 28, an AND element 29, a pulse frequency divider 30, a register 31, and a decoder block 32.

The write address generator (FIG. 3) contains registers 33-35, accumulating adders 36 and 37, a fixed memory 38, counters 39-41, an OR 42 element, and a pulse frequency divider 43.

The memory selector unit (Fig. 4) contains a counter 44, a decoder 45, a register 46 and a permanent memory 47.

The write condition shaper (FIG. 5) contains a comparison circuit 48, an element OR 49, an AND element 50, and a decoder 51.

Shaper Executive address (6) contains switches 52-55 and registers 56 and 57. Switches (7) contain switches 58-60.

The shaper mode of operation (Fig.8) contains decoders 61 and 62.

Device Ystvo works as follows.

The synchronizer 21 generates BpeMeHHj tags that go into all the blocks. The external computing means record in block 1 a concise description of the elements of the output information (i.e., information that must be input to the device input 27), as well as data for erasing (cleaning) the drives 19 and 20.

The output information is divided into portions that have a certain meaning for the peripheral equipment (by) that is connected to the output of the proposed device. For example, the Portion may contain a direct code equivalent (bit in memory - image point) of one television line. Consider the work for the case when the output information is output to the software cyclically (regeneratively) with a certain period T (for example, T 40 ms). In this case, time T is divided by V equal segments t .j .-. Tv (V is even). The time interval t corresponds to the i-th cycle of software operation. During each segment t in the software, m pieces of output information are output, which ensure the operation of the software in the i-th cycle. In total for the period T, the output is m -v of different portions of the output information. The values of m and V depend on the speed of blocks 2 and 3 and the requirements imposed by the peripheral equipment (for example, V 4 $ m 128; V 8, m 64).

The volume of each accumulator (19 or 20) is divided into zones. Each zone contains one portion of the output.

The erasing (cleaning) of the accumulators 19 and 20 is that the accumulators are brought to the desired initial state. At the same time, in the cell of the drives 19 and 20, some initial information (preassigned by external computational means) is recorded: erase data. In the particular case, the erase data is all zeros, or all ones. In general, erasure data is more complex and unequal for different portions of the output.

The output information in the software from drives 19 and 20 consists of erase data, on which (as the background) data records are superimposed

These records are recorded in accumulators 19 and 20 at the addresses formulated by shaper 3, and are an expanded representation of the elements, a concise description of which is recorded in block 1 by external computing means. The processing of blocks 2 and 3 of the compressed description of the elements of the output information is

in obtaining a detailed representation of these elements in accordance with the algorithms learning the specifics of the software. For example, in displaying dynamic graphic information, the elements of the output information are vectors, arcs, symbols, etc. The compressed vector description is the coordinates of the starting point, the angle of inclination and the length. The expanded representation of a vector is a sequence of addresses (the driver of the generator 3) of the points of this vector with simultaneous indication of the recording data — the code of the color of the points (black, white, gray, red, blue, etc.). In this case, of course, the color code should differ from the corresponding erase data (if the erase data is all zeros, then the color code is one). To obtain a detailed representation of the elements, the former 3 contains a ROM (for example, a sinus ROM, a symbol ROM, etc.), counters, registers, adders, control nodes. It can be said that the compressed microprogram description is implemented by blocks 2 and 3. The following processes are simultaneously carried out at a time interval t (1 1,3,5 ..., U-1): drive zone 19 enters the output (via switches 22 and 25), which ensures — and the software clock cycle the drive 19 is cleaned (erased a) after clearing a cell, erase data is written, Corresponding portions of the output information for the time interval t; J42 t drive 20 (cleaned as necessary at the time) are recorded through switch 12 to the addresses of the driver 5 prepared by the driver 3 write data (detailed representation of the elements) corresponding to time interval t. . In the next period of time (, 4,6, ..., V), the accumulators 19 and 20 change their roles, and at the same time they are carried out, the following processes m zones of the storage device 20 are output, providing (1 + 1) -th clock noj jobs and the accumulator 20 records the erase data corresponding to the time interval i, the data storage corresponding to the time interval tt (the index in the expression t; calculated modulo j 1 V- 1, then 1 —and V, 1 for example, if +2 v + 1). Blocks 2 and 3 during each time interval (t, e, with a period of T / v 3.14 provides processing (or at least viewing) of the entire array of compressed descriptions stored in block 1. However, the drive (20, if i 1,3,5,7, or 19, if 1 2,4,6, 8) only the recording data is received, corresponding to the interval to / i. This is ensured by the joint operation of blocks 14, 16 and 21. Synchronizer 21 generates time stamps, by which blocks 14 and 16 use counters, comparison circuits and decoders included in their composition to determine which time interval takes place. Block 14 determines 1,3,5 or i 2,4,6 and thus chooses which of the drives 19 and 20 works with the driver 3 (for writing), and which with the output switch 22 (for reading). At i 2,4, ..., V for recording works drive 19, with 1,3,5 ..., V-1 for recording works drive 20. Relevant signals are monitored by block 14 in drivers 5 and 9 and in blocks 11-13,15-18 Shaper 16 takes into account the peculiarities of this time interval and finally decides whether it is necessary to write data to the drive at the address obtained by shaper 3 at the current time. For example, when displaying dynamic information with interlaced scanning at V 4, g 128 is the time interval t ;, and 11, respectively, the upper and lower half of the image of the even half-frame, i. t is the upper and lower image, respectively, of the odd half frame. The data address of the recording under control of the unit, 14 is connected via the drivers 5 and 9 to the inputs of the accumulators 19 and 20. Counter 4, connected to the output of the synchronizer 21, generates the addresses of reading information stored in the accumulators 19 and 20 at a rate that takes into account software features. The reading address (output address) consists of two independent components: the accumulator zone number and the word number in the zone. The reading addresses are connected to the inputs of drives 19 and 20 respectively. „Cut shapers 5 and 9 under control of block 14. According to the signals from the output of block 2, erase data and write data from

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unit 1 is recorded in the corresponding bits of register 7. Record data (second output, register 7) and erase data (first output register 7) under the control of block 14 is fed through switches 12 and 15 to the inputs of drives 19 and 20.

The former 16, which is a combinatorial circuit, generates conditions for recording information regenerated by block 3 with the following conditions, the address of the record (second input) coming from block 3, the features of the time interval (for example, even / odd half frame, third input 7) coming from synchronizer 21, and the number 1 of segment 1 1 (first input) coming from block 14,

In order to ensure the simultaneity (in the length of time) of the processes of reading the output information from the accumulator and writing to the same accumulator, erasure data corresponding to the length of time i 4-1 and 20 are organized with a bundle;

Let, for example, n 2 and drive 20 work with an output device. Then the first accumulator block (i.e., block 23i) contains words with odd numbers for all (POS and the second accumulator block (block 23) contains words with even numbers of all m zones. The signals to the inputs of accumulator 20 are given in such a way that The moment when the word with the number (2i + 1) is read from block 23, in block 23, the erase data is written to the place of the previously read word with number (in this case, the executive addresses in blocks .23 and 23 differ by one

Then from block 23 the word with the number is read, and in block 23 / the data is erased in place of the word with the number (in this case, the executive addresses in blocks 23 and 232 coincide. Thus, blocks 23 and 23 alternate roles. Further description the device will work for the case of And 2.,

Consider the joint work of blocks 2 and 3 on the formation of address entries.

Divider 30 of block 2, receiving signals from the second output of the first group

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The outputs of the synchronizer 21, forms time stamps for which the command counter 28 with a period of T / V turns into block 1 for the next command of a compressed description of the elements of output information. The data from block 1 is sent to register 31 and further to decoder 32.

. Decoder 32 by opcode and

About the person in the command, generates control signals that gates the recording of the next command to the corresponding registers of the imaging unit 3 or to the corresponding bits

5 register 7.

If the next word read from block 1 to block 2 is a build command (for example, a vector build command), then the decoder

0 32 forms a strobe to write this word to the angle register 33 or to one of the counters 39-41. If the word read from block 1 is data for erasure or for recording, then it is written to register 7. Consider the process of generating write addresses by block 3. After writing a compressed image description, divider 43 gives the command to write

0 sine and co-angle angle, whose code is stored in register 33, in registers 34 and 35. Then the process of forming addresses begins. Accumulators 36 and 37, accumulating the value of sines and cosines, accumulate the fractional part of the address. Each transition through the fractional part of the address at the output of the adder 36 and 37 gives a command for a unit increment for the counters 39 and 40, respectively. Each summation of sines and cosines gives the output command for the length counter 41. The process of forming addresses of points describing the next image element continues until the length code in counter 41 is deleted (matched). Mathematical address

50 records, formed by block 3, enters the blocks 6 and 8 and identical shapers 5 and 9 of the executive address.

Blocks 6 and 8 and shapers 5 and 5 9 link the mathematical addresses of the output information, formulated by block 3, to the addresses of the accumulators 19 and 20. The lower bits of the mathematical address go to node 8, the higher bits to blocks 5, 6 and 9, and the digits of the mathematical address corresponding to the cell number in the block accumulate l enter the formers of 5 and 9. The former 5, shown in FIG. 6, works as follows. When the drive 19 is operating in the write mode, the address from block 3 through the switches 53 and 54, under the control of block 14, records to registers 57 and 56 and then enters the blocks of the drive. In this case, the switches 52 and 55 transmit pulses from the synchronizer 21 to the recording inputs of registers 57 and 56 simultaneously. Register 57 is connected to block 24, and register 56 is connected to block 242. The accumulator block (24 or 245) is selected by node 6, which decrypts the most significant bits of the record. The bits in the cell are selected by node 8, which decodes the lower bits of the address. Thus, the mathematical address formulated by block 3 is converted to the write write address for the accumulator. Simultaneously with reading information from the accumulator to the output device, it is necessary to ensure (write erase data, which is stored in register 7, into blocks of accumulator that work with the output device). Let us assume that the output device is currently running at time t, drive 19, then the blocks 24 and 242 are accessed according to the table. Counter 4 contains auxiliary (minor) times The synchronizer 21 receives a counting frequency twice as large as the frequency of information output to the peripheral equipment. The auxiliary bit is not included in the executive address of the read. NIN. This bit goes to the control inputs of the switches 52 and 55, which are pass a pulse from the synchronizer to the input of the register 5 (if the bit is O) or to the input of the register 56 (if the bit is 1). Consider the operation of block 14. Block 14 selects drive 19 or 20 18 for reading in the software. Then the other is transferred to the accumulator in recording mode from block 3. The chunk frequency from synchronizer 21 is fed to the counting input of counter 44, which is reset to the initial state by the beginning of the period T. The decoder 45 sets the segment number and writes it to the register 46. Thus, at the output of register 46 there is always an indication of what time interval t is taking place at the given moment. The memory 47 is stitched so that at its output the signals have the following connection with the time intervals t). At the time intervals ti -n, the signal connected to the driver 5 and the switches 11-13 transfers all the indicated nodes to the data recording mode to the drive 2 , 0 from block 3, and the signal connected to the driver 9 and the switches 15, 17 and .18, transfers the indicated nodes to the state of information from the accumulator 19 to the output device. At time intervals T /,, t, the signal at the output of block 14 switches switches 11-13 and shaper 5 to read information from accumulator 20, and switches 15, 17 and 18 shaper 9 - to write data to drive 19. In addition, the number of segment i is fed to the imaging unit 16 to the comparison circuit 48. Scheme 48 compares the ic address of the record coming from block 3. If the address of the record is outside the limits corresponding to the segment i. / (then a signal is sent to gate 50 through the LII 49 circuitry that blocks the write strobe to the accumulator. In addition, circuit 49 receives a signal from the comparison circuit 48, which compares the address with constants limiting the recording area (for example, output to the limits TV screen.) Thus, the shaper 16 generates sync pulses into the drive and, in addition, controls the operation of block 3 at the moments of the recording (pauses the calculation). Shapes 5 and 9 process the higher bits of the write address and allow to address The next, lower in weight, p 1zr write addresses are sent to the switch 11 after being decoded in block 6. These bits allow you to select a drive unit. If the block is two, then one bit is used for this purpose e The least significant bits are used for bit addressing to the storage cell during recording.These bits are decrypted by node 8 and fed to switches 12 and 15. Both switches are similar, therefore consider the structure of switch 12 (FIG. 7). The last input includes a 58-bit switch, a switch of 59 clock pulses and a data switch 60. Switch 58 is designed to control bit writing to storage units. In the recording mode, information from the first input of the switch 12 is transmitted to its output and allows access to those of the storage unit crystal, which are indicated in the recording address. In the read mode, a constant is applied to the output of the switch 58, allowing access to all storage chips. The switch 59 switches the clock for the drive. Moreover, in the data read mode, the sync impulse passes from the second input of the switch 12 to the drive, and the write mode - from the third input

Read-StiraRemim operation of block 24.,

block 24,

rashchaem bath

Auxiliary read address bit

Read- Erase

Reads 320 of the switch 12. Switch 60 connects either the write data or the erase data to the information inputs of the drive. Block 10 is shown in FIG. 8. The decoder for selecting block 61, in accordance with the table (for), selects (allows access) both blocks 24, | and 24 ij always with the exception of the beginning of the reading of the portion when the block 24 / does not need to be addressed. To block access to block 24 (decoder 62 selects the state when the read address and auxiliary bit are O. The work type decoder 61 for P 2 passes the output of the auxiliary and inverse auxiliary bit to the output in accordance with Table 1. If the software represents the display, the zone and the word are the direct code equivalent of the tele-line and familiarity, respectively; the word number is address X, the zone number is address Y. Thus, the proposed device eliminates the need to pre-sort the input dynamic Ski variable information, so it has a great speed in comparison with the known.

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Figg

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FIG 5

Fig.b

Claims (1)

DEVICE FOR INPUT AND OUTPUT OF DYNAMICALLY CHANGING INFORMATION, comprising an input storage unit, an instruction analysis unit comprising a counter, a register, a pulse frequency divider, a decoder unit and an And element, a counter, a recording address generator ,. containing three registers, a pulse frequency divider, two accumulative adders, read-only memory, three counters and an OR element, two decoders, a register, four switches, a memory selection unit, containing a counter, decoder, register read-only memory, an I block, a synchronizer and two groups P of memory blocks (p? / 2), and the information input of the input storage unit is the input of the device, the read-write input of the input storage unit is connected to the first output of the first group of outputs of the synchronizer, the address input of the input the memory unit is connected to the information output of the counter of the command analysis unit, the information input of which is connected to the information input of the register of the command analysis unit and · to the first output of the input storage unit, the second output of which is connected to the information input of the first register of the recording address generator and the third counter of the recording address generator and with the information inputs of the upper digits of the first and second counters of the recording address generator, the third output of the input storage unit is connected to inform by the input register of the device, the counting input of the pulse frequency divider is connected to the second output of the first group of synchronizer outputs, the first and second outputs of the decoder of the command analysis unit are connected respectively to the write-read input of the device register and to the write inputs of the first register of the address generator and the first, second and the third counters of the recording address generator, the clock input of the pulse frequency divider of the recording address generator is connected to the third output of the first group of outputs of the Synchronizer, counted input q the counter of the command analysis unit is connected to the input of the register of the command analysis unit and to the output of the AND element of the command analysis unit, the first and second outputs of which are connected respectively to the output of the pulse frequency divider of the command analysis unit and to the third output of the decoder of the command analysis unit, input which is connected to the output of the register of the command analysis unit, the information outputs of the second and third counters of the recording address generator are connected respectively to the first and second inputs of the first and second decoders of the device The output of the first register of the write address generator is connected to the address input of the read-write memory of the back address generator, the output of which is connected to the information inputs of the second and third registers of the write address generator, the outputs of which are connected to the information input of the first accumulating adder and the information input of the second accumulating adder, the synchronization inputs of which are connected to the counting inputs of the first, second and third counters of the shaper recording address and the first output ohms of the pulse frequency divider of the recording address generator, the second output of which is connected to the read permission input of the read-only memory of the recording address generator, and the recording inputs of the second and third registers of the recording address generator, the outputs of the first and second accumulating adders are connected respectively to the information inputs of the least significant bits of the first and second counters of the recording address generator, overflow output of the third counter of the recording address generator is connected to the first input of the element OR A recording processor, the output of which is connected to the blocking input of the pulse frequency divider of the recording address generator, the fourth output of the first group of outputs of the device synchronizer is connected to the counter input of the device counter, the first, second, third and fourth information inputs of the first and second switches are connected respectively to the output of the second device decoder , with the fifth output of the first group of outputs. of the device synchronizer, with the first output of the device register and with the second output of the device register, group The incoming inputs of the first and second switches are connected to the group of memory outputs of the memory selection block, the outputs of the first and second switches are connected respectively to the information inputs of the memory blocks of the first and second groups, the sixth and seventh outputs of the first group of outputs of the device synchronizer are connected respectively to the counting input of the block counter memory selection and with the control input of the third switch, the first and second information inputs of which are connected respectively with the outputs of the memory blocks of the first and of the second group, the group of information outputs of the counter of the memory selection block is connected to the group of inputs of the decoder of the memory selection block, the group of outputs of which is connected through the register of the memory selection block to the group of address inputs of the permanent memory of the memory selection block, the output of the third switch is connected to the information input of the fourth switch, the group of control the inputs of which are connected ₍ connected to the second group of outputs of the device synchronizer, the output of the fourth switch is the output of the device, characterized in that, for the purpose of improve performance, it additionally contains a fifth; the sixth, seventh and eighth switches, two shapers of the executive address, each of which contains four switches and two registers, a shaper of operating modes containing two decoders, a shaper of recording conditions containing a comparison circuit, a decoder, an OR element, and an I element, and a group of information outputs the device counter is connected to the first groups of information inputs of the first, second and third switches of each shaper of the executive address and to the groups of inputs of the first and second decrypto mover of the operating mode driver, the first input of the second group of information inputs of the first switch of each executive address generator is connected to the first input of the first group of information inputs of the fourth switch of each executive address generator, with the information output of the first counter of the recording address generator, with the first input of the first group of information inputs comparison schemes with the first input of the decoder of the conditioner of the recording, the second input of the second group of information inputs of the first the switch of each shaper of the executive address is connected to the second input of the first group 11504 3 information inputs of the fourth switch of each shaper of the executive address, with the information output of the second counter of the shaper of the write address, with the second input of the first group of information inputs of the comparison circuit and with the second input of the decoder of the shaper of recording conditions, the eighth output of the first group of outputs of the device synchronizer is connected to the control inputs the first, second, third and fourth switches of each shaper of the executive address, the second group of information inputs of the second the third switches of each executive address generator are connected to the group of outputs of the permanent memory of the memory selection unit, to the first groups of information inputs of the fifth, sixth, seventh and eighth switches and to the second group of information inputs of the comparison circuit, the output of which is connected to the first input of the OR element of the recording condition generator, the second input of which is connected to the output of the decoder of the conditioner of the recording, the output of the element OR of the conditioner is connected to the first input of the element And the form For the recording conditions and with the second input of the OR element of the recording address generator, the second input of the recording condition element AND is connected to the ninth output of the first group of device synchronizer outputs, the output of the recording conditioner element And is connected to the fifth information inputs of the first and second switches, the outputs of the second and third the switches of each shaper of the executive address are connected respectively to the recording inputs of the first and second registers of each shaper of the executive address, the outputs the first and fourth switches of each executive address generator are connected respectively to the information inputs of the first and second registers of each executive address generator, the output of the first register of each executive address generator is connected to the second information input of the fourth switch of each executive address generator, the output of the first device decoder is connected to the first control inputs fifth and seventh switches, the output of the first decoder shaper p operation mode connected to the second control inputs of the fifth and seventh switches, 4 outputs (* = 1,2,. . ., p) the fifth and seventh switches are connected respectively to the synchronization inputs of the 4th memory block of the first and second groups, the output of the second decoder of the mode shaper is connected to the control inputs of the sixth and eighth switches, the outputs of which are connected respectively to the read, write memory inputs of the first and the second group, the outputs of the first and second registers of the first shaper of the executive address are connected respectively to the address inputs of the lower and high bits of the memory blocks of the first group, the outputs are not first- and second-registers of the second effective address generator are connected respectively to the address inputs of lower and upper bits of the second group of memory blocks.