SU1483676A1 - Device for shaping video information - Google Patents

Abstract

The invention relates to automation and computing, and is intended to form an image by synthesizing portions of a plurality of originals on a computer and transmitting the obtained images to a plurality of peripheral devices such as television receivers. The purpose of the invention is to expand the functionality of the device by increasing the playback speed of information on each television receiver, increasing the speed of repeated calls to the previous video information screen and reducing the dependence of the video output speed to the television receiver screen on the operation of other video output channels. For this, a device comprising an operation unit 1, an external memory block 2, a RAM block 3, a multiplexer-distributor 4 and a group of channels 5 for outputting video information, each of which contains a channel block 7 of memory, a digital-to-analog converter 8, a television receiver 9, block 10 video selection, additionally introduced block 6 control in each channel issuing video information. 14 il.

Description

Optative Information

The invention relates to automation and computer technology and is intended to form an image by synthesizing portions of a plurality of originals on a computer and transmitting the received images to a variety of peripheral devices such as television receivers,

 The purpose of the invention is to expand 10 functional capabilities by increasing the playback speed of information on each television receiver, increasing the speed of repeated calls by 15 times the previous video information and reducing the dependence of the video output speed to the television receiver screen on the operation of other video information channels of the corpses.

Figure 1 shows the functional diagram of the device; Fig 2 is a functional block diagram of the control unit; FIG. 3 is a functional diagram of a channel memory block; in fig. 4 shows a functional diagram, diagrams for selecting a screen and printing data included in the control unit; in fig. 5 - functional diagram of the recording circuit - the read of the channel memory block, which is part of the control unit; Fig. 6 is a functional diagram of a synchronization circuit included in the control unit; in fig. 7 - a table for programming the address of the memory page of the channel memory block; in fig. 8 and 9 are timing charts of the synchronization unit shown in FIG. 6; in fig. 10 is an algorithm 40 for operating a video storage unit; in fig. 11 and 12 are algorithms for the operation of the multiplexer-distributor in the initialization modes on the side of the channel and 45 on the side of the video storage unit, respectively; FIGS. 13 and 14 are channel addressing codes, interrupt operations, operation codes on

TIRE LINES, cn

The device (Fig. 1) contains an operational unit 1, an external memory unit 2, a main memory unit 3 included in a video information storage unit, a multiplexer-distributor 55 4, a group of channels 5 for issuing video information, the number of which is K. Each channel 5 group contains a block of 6 control channel block

7, a digital-to-analog converter 8, a TV receiver 9, a video storage unit 10.

The control unit 6 of each channel (Fig. 2) contains M processors 11, M address registers 13, a screen selection and printing circuit 12, a read-write circuit 14 of a channel memory block, a first block K of multiplexers 15, a second block T of multiplexers 16, block 17 of the R-schemes for programming the pages of the memory of block 7 and the circuit 18 for synchronization. Here K is the number of bits of the address registers 13, T is the number of bits of the page code of block 7, and P is equal to the logarithm of T at base 2.

The number of information i-inputs and control 1-inputs of each multiplexer 16 is selected in accordance with the expressions:

I

i (logtT) + 1; 1 log4M,

where M is the number of processors in the control unit.

Channel memory unit 7 (FIG. 3) contains M memory blocks 19 and a shift register 20. This or that memory page uniquely corresponds to this or that memory block 19,

Data from the corresponding bus is fed to the inputs of the memory blocks 19, and the output data from the corresponding memory blocks is outputted via the corresponding bus. Signals of the memory at the input of the VC record-read information into or out of the corresponding memory blocks.

The shift register is recorded by a parallel code and outputted by a serial code of information from one or another block of memory 19 to a digital-to-analog converter 8, which perceives this information as a video signal and, together with the OXC, OXK, BS signals, produce the corresponding control pulses for TV receiver.

The screen selection and printing data (figure 4) contains M decoders 20 and 21, two schemes AND-OR 22 and "23,. a group of AND-OR 24 circuits, the number of which is T, which is numerically equal to the number of page code bits of the channel block of 7 memory, two registers 25 and 26, two multiplexers

27 and 28, the output decoder 29 and the scheme OR 30.

The read-write circuit 14 of the channel memory block (FIG. 5) contains M logical blocks, each of which contains a decoder 31, four flip-flops 32, 33, 34 and 35, an OR circuit 36 and two circuits And 37 and 38, register 39, bus driver 40, in addition, the circuit 14 contains a group of elements AND-OR 41, the element OR 42, the encoder 43

Each logical block of the read-write circuit of the channel memory carries out the reception-transmission of information from / to the NB bus, and using the decoder 31 three modes are organized depending on the state at the outputs of the decoder.

When a signal appears at the first output of the decoder 31, the information unit is transmitted via trigger 32 to trigger 33 and then to input of circuit AND 37, at the output of which signal T1 forms a recording signal to the channel memory, simultaneously the signal from the output of circuit OR 36 enters to the encoder 43, at the output of which the control code of the address of one or another page of the channel memory is formed. At the same time, through the open circuits of the group of the AND-OR 41 circuits, information from the output of the register 39 enters the buses.

When the signal appears at the second output of the decoder 31, the circuit operates in the mode of reading information on the ШП1 bus from the input bus. Similarly to the described, the triggers 34 and 35 are triggered, the corresponding signals are generated and the data is transmitted via the bus driver to the ШП1 bus. The reset signals bring the elements of the logic block circuits to their initial state.

0

0

five

0

five

0

The channel block of memory also contains a decoder 57.

Timing diagrams of the operation of the synchronization circuit are shown in FIG. 8 and 9, where Tp is the period of the BS signals following (page blanking); t f is the pulse duration of the BS signal; t 2 - the pulse duration of the signal OHS; t e is the pause between the pulses of the signal; t 4 is the pulse duration of the OCC signal.

The transcript and composition of the tires and signals encountered in FIG. 1-14 are shown below:

And - information bus connecting multiplexer-distributor 4 with control units 6; A1 is the bus address of the channel memory block; - the number of lines in the bus; A i is the bus address of the page of the channel memory block 7; T - the number of lines in the bus; E — data bus channel memory block 7; D 01 - input data - 5 nge, D og - output data, moreover, the data C 0 and C 01 are received via their X-buses; V К3у - control bus of block 7, containing three lines: read-write of block 7, (34 k3y), strobe (C "charger) and clock signals (G); ССТР - bus of synchronization and control signals of a TV receiver, containing three lines: reverse line stroke (OHS), reverse motion to the core (OCC), page blanking (BS); L “l data bus of the video selection block; UKL - the bus for controlling the keyboard of the video selection block containing two lines: the SCL keyboard strobe, the keyboard request 3; D p-bus data to print; Pack - print management tire, containing two lines: print request 3,

P

Cn print strobe; Ш Л- tires process

When the TG signal appears at the third output of the decoder 31, it is transmitted to the output of the circuit to control the address registers 11 of the control unit 6.

The synchronization circuit 18 (FIG. 6) of the control unit 6 comprises a pulse generator 44, three triggers 45, 46 and 47, two serially connected binary counters 48 and 49, two circuits And 50 and 51, two decoders 52 and 53, and a single vibrator 54 with a capacitor 55 and a resistor 56 at the input.

ROV 11; P to the output bus address registers 13; M - the number of tires; K - the number of lines (bits) in each bus; Sp, C Cl are the individual lines through which the corresponding strobe signals are supplied; 3 CL - separate M-lines, on which the keyboard recording signals (3 CL-3kA) of block 10 are sent; H c - individual M-lines through which print data is transmitted from the corresponding processor 11; Pj- separate M-lines for controlling pa1H

bot of address registers 13; T R t the synchronization and control signals received on separate

lines from the synchronization circuit 18; D - the number of lines from the circuit 18 synchronization, which receives the signals of the address of the cell (pixel) channel storage device; Vj - Vp - code lines of the bus controlling the address of the page of the channel memory; D} - Dp - buses of switching signals coming from the R-circuits block of programming the memory page of the channel memory.

The operation of the device is as follows.

According to commands from the keyboard of the video selection block 10 from any of the n-channels (Fig. 1), the corresponding control unit 6 connects to one or another bus I.

After the operating system of the operating unit 1 is started, the operator from the keypad 10 sprinkles commands through the control unit 6, the AND bus and the information multiplexer-distributor 4 into unit 1. At the same time, the control unit 6 adds information about the address of the peripheral device to the information from the keyboard, to which video selection unit 10. Information multiplexer 4 also adds information about the channel number from which it was received.

According to the commands received, the operating system of the unit 1 in the video storage unit launches the corresponding tasks for this channel 5.

These tasks may include, for example, tasks associated with generating a frame (page) of information for display on a TV receiver. In this case, block 1 selects information from the corresponding cells of block 2 and sends it to block 3, where it is added to the address of the peripheral device and is formed in a form convenient for transmission through the information distribution device to the corresponding buses I. The control unit 6 is from the corresponding peripheral channel, at its address, decodes information coming to it from block 3, generates A2 addresses of memory pages of memory channel block 7, addresses A1 of the corresponding pixels of the memory channel block, control signals UK The GUI exposes the data on the D0 bus, (FIG. 1). Data

Q

0 5 0

five

0 s

0

five

from the bus D01 is brought into the corresponding blocks of the memory of blocks 7.

Further, according to the operator's commands from the video information selection unit 10, information from one or another memory page can be displayed on the TV receiver 9. In this case, the control unit 6 generates the address A2, the address A1, and the CHI control lines are sent to the CCFL. TV9, why a raster such as a television is created on the screen of the TV receiver 9.

The At buses generate addresses of pixels related to this memory page with address A2. According to these addresses, the channel memory unit 7 outputs the information pixels to the D / A converter 8, where they are converted into the form necessary for display on the TV receiver 9 The transmission of information from the D / A converter 8 to the TV receiver is carried out under the control of the control signals of the CCTV.

The operator can edit the information on the TV receiver, i.e. editing information recorded in one or another block of memory of block 7. For this purpose, control signals are sent from video selection block 10 via a U-l line and data from a D-L line. The control unit 6 decodes this data, performs the corresponding operations with the information in the channel memory and displays the results on the TV receiver screen.

According to the operator's instructions, information from the channel memory 7 can be sent by the control unit 6 to the printing device via the D bus, the print control bus U is used, and also sent via the buses AND, the multiplexer-distributor 4 and block 3 to block 2.

The system operation is described in more detail in separate modes of operation.

The keyboard access mode of the video selection block to the control unit processor.

When the operator types any information on the keyboard unit 10

the data bus is formed byte-by-byte on the D-CL bus, which is accompanied by the C-CL signal.

This signal is sent to the decoder 29 (FIGS. 2, 4) and in accordance with the state of the register 26 is transmitted

on one of the lines С kA to the corresponding processor 11 of the control unit 6.

Data D cd comes to all processors 11 in parallel. The processor, which received information from the bus D k / l, processes it according to the corresponding internal program, while this processor removes the corresponding signal. 3 KL.t

According to commands from the keyboard, the operator can select and organize communication with any of the processors 11. Connecting the keyboard to one or another

The processor 11 may also occur via commands from block 1 via the buses I (FIG. 1). In this case, the processor received from the bus And such a command exposes an address on its bus, which is interpreted in the screen selection circuit 12 and printing the data as a command to connect the keyboard to the corresponding processor. The decoder 20 (or 21) decrypts this command and, through a group of AND-OR 24 circuits, the data from the corresponding bus is written to register 26, the state of which determines the number of the processor and channel to which the keyboard is currently connected.

Reading mode on the screen.

This mode is one of the main ones. In the absence of information on the WB buses (Fig. 2) from the processor 11 on certain lines, block 14 (Fig. 5) generates a code 0 at the outputs V; -V-, which means executing a read command on the screen of information from the channel memory. At the same time, information from the corresponding processor may be present on the other lines of one of the PW buses, which, passing through block 12 (FIG. 4), is formed at the output of register 25 and, through the block of multiplexers 16, forms 6 on buses And the address of one of the pages of blocks 19

TV receiver wounds. Signal C .c from block 18 (Fig. 6) information from the corresponding memory page of block 19 is written to register 20 (Fig. 3) and further signals C k3; (with a serial code is copied to a DAC, where after conversion to analog form is displayed on monitor screen 9.

. If the bus D received information from the first processor, then ectO

thirty

(5 20 25

P

35

five

0

five

The first memory page is displayed on the wound, if from the second - the second memory page, etc. Thus, the operator can read any of the memory pages and in any sequence, without directly accessing blocks 1 and 2. At this time, block 1 of the video storage unit can transmit and receive information from other peripheral devices and fill the channel block 7 memory

The processor access mode to the channel memory block 7.

In this mode, information is recorded from the processor to block 7 and reading information to the processor from block 7.

The recording is carried out as follows (Fig. 2). A processor, e.g. 11t, via the NBF bus and block 14 forms a corresponding code on V1-Vt buses, as a result of which D1 bus lines of multiplexers, 16, connected to one of the programmable blocks, in this case block 17, are connected to the AJ bus, Forming the address of the page of the channel memory for recording information from the first processor 11. On other lines of the NB bus, through the address register 13 from the processor 11 1, information is received via bus P Kl to inputs D, multiplexers 15, which causes bus address A to be generated The memory inside the selected page (by a dresu A.J). When a signal 34 at a signal appears at the input of block 19 from block 14, data is recorded from processor 11,, through block 14 via the data bus D01 to the corresponding cells

selected page, i

The selection of the address of the information reading cell from block 7 to the processor is carried out in the manner described, i.e. the address of the page A is formed, the address of the cell A ,, and the reading of information is carried out on the data bus D 01 (Fig. 3) in the absence of a 3-channel memory signal. The data on the bus DG comes to the block 14 (Fig. 5) and through the bus driver 40 are sent to the WB1 bus of the processor 11 ,.

FIG. Fig. 7 shows the programming table (connection) of 17: 1 block buses in a cell means that this line in this block is connected to the Ep bus of the power source, O - to the 0V bus of the power source.

The processor access mode of the control unit to the video storage unit.

Each of the M processors of each channel can be turned on (connected) to block 1 or by command from its own console of block 10, or by commands of its own internal program. In both cases, data from the corresponding processor is set to the corresponding bus I (Figs. 1 and 2). Unit 1 at the appropriate time decrypts the data set on a particular bus AND, sets the address of the processor to be addressed and the address of the channel in which it is located, then decrypts the task and turns on the information exchange program. The data can come both from the processor (information of the edited page) and to the processor from block 1 or block 2 under the control of block 1.

If the initiator of information exchange is block 1, then on the appropriate bus I the address of the corresponding processor is set up, which, according to its internal program, decrypts the request sent to it from block 1, establishes a connection with block 1 and the specified bus This is how information is exchanged either in this or the other direction. This mode provides relative independence of information transmission from block 1 to each channel, without affecting the process of displaying information in TV receivers, thus ensuring their independent work in interactive mode with the operator.

DESCRIPTION OF THE ALGORITHM OF THE FUNCTIONING OF THE STORAGE BLOCK VIDEO INFORMATION

After turning on the power, the video storage unit operates as follows (see Figs. 10 and 1) 4j

 one . Initializing block 1, including loading the operating system, starting the task, etc.

2. Analysis of the interrupt request from the multiplexer-distributor 4.

If there is an interrupt, go to step 3.

3. Signal processing Interruption from block 4 under the control of operation Q 0 0

0 o

five

0

five

Noah system. Signal The interrupt enters the 4-1 bus.

4. Receiving information about the type of instruction, its contents and its recording in block 3 via bus 4-3 (for example, input / output operation, video block address, control block address) under control of signals through bus 1-3.

5. Analysis of the end of the receipt of instructions in block 3 according to the data received in block 1 via line 3-1. After the receipt of the instruction is completed in block 3, the input operation /

the output recorded in the instruction, on line 1-3,

6. Analysis of I / O operations. As a result of the analysis of this operation, a transition is made to the operation Read in block 2 or Write in block 2.

7. Initialization of the operation Reading to block 2 via bus 1-2.

8. Transfer of fragments of the requested video information from block 2 to block 3 via bus 2-3,

9. Converting image fragments into a single image

in block 3, under the control of signals coming along the bus 1-3,

10. Initialization of the operation Record in the block of the multiplexer-distributor 4 via line 1-4 to the address of the control unit 6, which issued the instructions in step 4.

11. Video transmission from block 3 via blocks 4 and 6 to block 7, via bus 3-4.

12. Analysis of the condition of displaying the received video information by the control unit 6 and forming a response on line 4-1 about the end of the received information - the end of the operation Read in block 2.

13. If, as a result of the analysis in operation 6, it is necessary to carry out the operation Write to block 2, then the block

1, after performing operation 6, proceeds to the initialization of the operation Read in the multiplexer block of the distributor 4 at the address of the control unit 6, which has set up to service this mode.

14.After performing operation 13, the video information is transferred from block 7 through blocks 6, 4, bus 4-3 to block 3.

15. Further, in accordance with the instruction stored in block 3, the whole video image is converted into fragments under the control of block 1 via buses 1-3, 3-1.

16. Initialization of operation Za-. writing in block 2 on line 1-2.

17. Transferring information from the unit

3 to block 2 on line 3-2, under the control of signals along lines 1-3, 1-2.

18. Analysis of the location of the received information in block 2 and assessment of the end of the operation Record in

block 2 (tires 1-2, 2-1 are used)

ALGORITHM WORK MULTIPLECTS

SORA-DISTRIBUTOR AT

INITIALIZATION OF SIGNALS ON

INPUTS / OUTPUTS

The multiplexer-distributor is initialized in 2 modes: a) initialization from the side of channel 5; b) initialization from the sides of the block 1 of the storage unit of the video information.

The algorithm of operation of the multiplexer-distributor 4 at initialization from the side of channel 5 is shown in FIG.

one . Initializing an I / O operation on the side of channel 5 on one or more buses.

2. Evaluation of the presence of a request-interrupt signal on buses And by block 4 (distribution multiplexer). If there is a signal on multiple buses, then the bus is prioritized.

3. If there is a request-interrupt signal on a particular bus, AND the multiplexer-distributor 4 transmits the request-interrupt signal to block 1 via bus 4-1 with the addition of the corresponding channel address.

4. Maintenance of the corresponding channel by the multiplexer-distributor 4 (connection of the channel) after receiving the signal from block 1 on completion of the analysis of the request-interrupt signal (via bus 1-4).

5. Addressing the address in block 3 of block 1 via bus 1-3.

6. The transfer of information from channel 5 on the corresponding bus And in block

 3 through the bus 4-3.

7. Analysis by block 1 of the end of the recording of information in block 3 and the formation of a signal on the bus 1-4 of the end of the data of the operation mode in multiplex

s

Jq

15

20

25

thirty

35

40

45

0

five

sor distributor. The channel address codes and interrupt operations for m 7 are shown in the table in FIG. 13.

WORKING ALGORITHM OF THE MULTIPLEX-DISTRIBUTOR 4 AT INITIALIZATION FROM THE BLOCK 1 OF THE VIDEO INFORMATION STORAGE UNIT The algorithm is shown in FIG. 12.

Claims (10)

1. Initialization of block 1 I / O operation to block 4 and transmission of the corresponding opcode on bus 1-4 (here there can be two cases: opcode read into block 3 or operation code Write in block 3. 2. Reception by the multiplexer-distributor by the bus 4 through the bus 1-4 of the operation code Read or Write in the block 2, its decoding and transition to the operation 3. 3. Analysis of the channel occupancy AND at the received address. 4. If the corresponding channel is not occupied, a response is sent from the distribution multiplexer 4c block 1 bus 4-1. 5. When a free channel response is received, block 1 via bus 1-3 generates the cell address of block 3, from which data 3-4 is written via bus 3-4 via multiplexer-distributor 4, block 6 to block 7 of the corresponding channel 5. 6. Analysis of conditions End of reading and sending a signal to block 1 about the end of the operation. If the distribution multiplexer 4 on the bus 1-4 received the operation code Write to block 3, then this code is decoded in step 2, and then 7, i 7. Analysis of channel occupancy at the received address from block 1 in accordance with claim 7. and establishing a connection with this channel. 8. When the corresponding channel is idle, the multiplexer-distributor 4 sends a response over the bus 4-1. about it. 9.When receiving the answer about the absence of the corresponding channel, the block 1 sends control over bus 1-3 to block 3 and data is written to block 3 from block 7 via blocks 6 and 4 via bus 4-3. 10. Analysis of the condition. End of recording in block 3 and sprinkling in block 1 of the signal for performing the operation Record. , Channel addressing codes and operation codes on bus lines 1–4 are listed in the table in FIG. 14.  ; Forum of the invention A video information forming device containing an operation unit, an external memory block, a RAM block, a multiplexer distributor and a group of video output channels, a group of information inputs-outputs of each of which are connected respectively to a group of inputs-outputs of the multiplexer distributor, the first and the second inputs-outputs of which are connected respectively with the first inputs-outputs of the RAM block and the inputs-outputs of the operation unit whose first input is an information input m device, the second input, the first output, the third input and the fourth output of the operating unit are connected respectively to the input and the output of the external memory block and the input and output of the RAM block, the second input-output of which is connected to the input-output block of the external memory block, each video output channel contains a channel memory block, a television receiver, a video selection block and a digital-analog converter, distinguished by the fact that 5 0 5 0 about five in order to increase the speed of reproduction of information on each television receiver, to increase the speed of repeated calls. on the screen of the previous video information and reducing the dependence of the video information output rate on the television receiver screen from the operation of other video group output channels, each of the group video output channels contains a control unit, the first and second address outputs of which are connected respectively to the first and second address inputs of the channel memory block , the information output of which is connected to the information input of the digital-analog converter, the output of which is connected to the input of the video signal a levization receiver, the synchronization input of which is connected to the output of the synchronization signal of the control unit, the input and data output of which are connected respectively to the information output and input of the channel memory block, the write-read, gating and clock inputs of which are connected to the corresponding outputs of the control unit, the control output keyboard and input of data from the keyboard of which are connected respectively to the input of control of the keyboard and the output of issuing commands of the keyboard of the video selection block, outputs Regents of the seal and a print data control unit are respective outputs dispensing channel video. years old } Fsh.g iruirinjiriJinjinjirLnjii IMIIIIMIIIIIIIIIIIMIIIIIIMIIIIIIIIllllllllllll Hi zil 5С OH C. ; y; LJTJTJiJi QW rTUTLJTL- - Jz JTTUTiirL JT LTpTir -44 WT-LH g51 // f / 77 FIG. ten one Start FIG. 12 FIG. / J