SU1107264A1 - Random digital sequence generator - Google Patents

Abstract

A GENERATOR OF A RANDOM DIGITAL SEQUENCE, containing a noise signal source, a divider number with a variable division factor, the control inputs of which are connected to the outputs of the control unit, and a clock pulse generator, characterized in that in order to increase the stability of the probability distribution of logical levels, between the output of the source of the noise signal 1 and the counting input of the pulse number divider with a variable division factor, a forming trigger is turned on, and an output trigger is introduced, the formation input of which is connected to the output of the pulse number divider with a variable division factor, the clock input to the output of the clock generator, and the direct and inverse outputs you. the travel trigger are the outputs of a random digital sequence generator. (L A A / 7v 7 V

Description

The invention relates to communication technology and is intended to simulate a random digital sequence, in particular in models of digital communication channels.

A known random number generator comprising a source of random noise signal connected in series, a transducer of said signal P is a square-wave signal with varying duty cycle and a pulse generation unit, as well as a block of temporal sampling of pulses 11.

In this random number generator, the probabilities of occurrence of low and high logic levels are regulated, however, when the distribution of the random noise signal is unstable, an error signal of the probability of the output of the random digital sequence is always generated.

The closest technical solution to the invention is a random pulse generator comprising a noise signal source, a divider number divider with a variable division factor, the control inputs of which are connected to the outputs of the control unit, and a clock pulse generator .21.

However, in the known random pulse generator, the stability of the probability distribution of low and high logic levels is not sufficiently high.

The purpose of the invention is to increase the stability of the probability distribution of logical levels.

The goal is achieved by the fact that a random digital sequence generator containing a noise signal source, a divider number of pulses with a variable division factor, the control inputs of which are connected to the outputs of the control unit, and a clock generator, between the output of the noise signal source and the counting input of the divider the number of pulses with a variable division factor included forming a trigger, and also entered the output trigger, the information input of which is connected to the output of the number divider pulses with a variable division factor, a clock input to the output of the clock pulse generator, and the direct and inverse outputs of the output trigger are the outputs of a random digital sequence generator.

The drawing shows a structural electrical circuit of the claimed random digital sequence generator. . . .

The generator of random digital compositon contains a source of 1 mental signal, forming a rigger 2, a divider 3 of the number of impulses

variable dividing owls, control block 4, 5 clock pulse generator and output trigger b.

The random number sequence generator works as follows.

From source 1, a random noise signal is fed to a clock input of a forming trigger 2, which converts it into a square wave signal with a uniform probability of voltage distribution of low and high logic levels. The shaping trigger 2 operates in the frequency division mode by two, since when operating in the division mode, the dependence of the probability distribution of the logic levels at the output of the shaping trigger 2 on the distribution of the random noise signal is reduced. From the output of the forming trigger 2, random pulses, with a uniformly distributed probability of occurrence of low and high logic levels, arrive at the counter input of the divider 3 number of pulses with a variable division factor, performed, for example, on a counter. To the control inputs (V, Ve, V, e, Vji) divider

3 Binary code signals are received from control block 4. The control unit 4 can be implemented on the basis of reversible counters, buffer registers or a set of 6 microswitches. The principle of operation of the divider 3 of the number of pulses with a variable division factor is as follows.

Out of every 64 low-level pulses, successively arriving at the counting input of the splitter | 3, at the output of divider 3, the number of low-level pulse is equal to L, where W is the tenth equivalent of the binary code specified by the control unit 4. Thus, the probability formula for the occurrence of a low logic level at the output of divider 3 is

P N

(1 (“128

From the output of the divider 3, random pulses with a given probability of distribution arrive at the information input of the output trigger 6, and operate in synchronization mode. The clock input of the output trigger 6 receives signals from the generator 5 clock pulses. At the forward output, the output trigger 6 sets the logic level of the voltage that was at the information input at the time of arrival of the clock pulse to the synchronization input. Thus, at the output of the output trigger 6, a random sequence with a pulse following frequency specified by the generator of the 5th contact pulses and the probability of distribution of the logic levels specified by the digital code using the control unit 4 is obtained. The probability of occurrence of a low logic level voltage at the direct output of the output trigger 6 will be PfA-. 128a at the inverse output, respectively, 1 1 - 128 (.3 Thus, in the proposed random digital sequence generator; the error in the probability distribution of logical levels is reduced due to the influence of instability of the random noise signal distribution and is represented by a possible digital code with a small elementary step adjustments vary the likelihood of distribution.

Claims (1)

A RANDOM DIGITAL SEQUENCE GENERATOR containing a noise signal source, a pulse divider with a variable division coefficient, the control inputs of which are connected to the outputs of the control unit, and a clock pulse generator, characterized in that, in order to increase the stability of the probability of distribution of logical levels between the output the source of the noise signal and the counting input of the divider of the number of pulses with a variable division coefficient includes the forming trigger, and also the output trigger is introduced, information Ion input of which is connected to the output pulses of the divider with a variable division factor, a clock input to the output of the clock, and direct and inverse outputs you. The triggers are the outputs of a random digital sequence generator.