SU1092500A1 - Device for calculating sum of squares of k pulse-number values - Google Patents

Abstract

A DEVICE FOR CALCULATING THE SUM OF SQUARES TO NUMBER IMPULSE VALUES, containing the element OR, the counter, the first group of elements AND, the delay element accumulating the adder whose output is the output of the device, the discharge outputs of the counter are connected respectively to the first inputs of the elements AND of the first group, distinguished by that, in order to increase speed, M-1 groups of elements AND (M is the code width of the number of input buses), H-1 delay elements, a group of elements OR, an encoder, whose inputs are connected to the input device buses, respectively, and the inputs of the OR element, whose output through the delay element is connected to the counter input of the counter, the bit outputs of which are connected to the first inputs of the elements AND of all groups, respectively, the first output of the encoder is connected to the second inputs of the elements of the first group and the decimal bit of the accumulating adder , the i-th output of the encoder is connected via the corresponding § delay element (, 3, ..., M) with the second inputs of the AND elements of the i-th group (Lp and the first input of the corresponding element OR group, the output element nta AND of the i-th group (, 2, ..., N), ..., M, where N is the counter width connected to the corresponding input () -ro of the OR element of the group, the output (i + j-1) - The ro element of the OR group is connected to the corresponding input of the accumulating adder.

Description

The invention relates to digital computing and can be used in the creation of information processing systems and devices. A device for calculating the Sum of squares to numbers is known, which contains a counter, the counting input of which is connected to the output of a block element, and the bit outputs to the first inputs of the first group of elements AND, and the accumulator Cl 3. The disadvantage of this device is the low speed that it is necessary to square each addend separately, submitting them to a single device input consistently over time and summing the results. The closest to the proposed technical essence is the device To calculate the sum of squares of K numbers, which contains an OR element whose inputs are connected to device inputs, a counter connected to the first outputs of the first group of AND elements, delay elements and a drive whose output is the C 211 device. The disadvantages of the known device are The low speed, as well as the complexity, of the circuit, due to the presence in its composition of k strobe pulse formers as well as the excessive discharge of the counter (its first discharge is always in the unit state and) and, accordingly, the elements of the group. The purpose of the invention is to increase the speed of the device. The delivered circuit is achieved by the fact that the device containing the element OR, the counter, the first group of elements AND, the delay element accumulating an adder, the output of which is the output of the device, separate outputs of the counter are connected respectively to the first inputs of the elements AND of the first group, M -1 groups of elements AND (M is the code width of the number of input buses), M-1 delay elements, the group of elements OR, the encoder, the inputs which are connected to the input buses of the device, respectively, and the inputs of the element OR whose output through the element The delay is connected to the counter input of the counter, the bit outputs of which are connected to the first inputs of elements AND of all groups, respectively, the first output of the encoder is connected to the second inputs of elements AND of the first group and the low-order accumulator, and the output of the encoder is connected to the delay element (i 2, 3, ..., M) with the second inputs of the elements AND of the i-th group and the first input of the corresponding element of the OR group, the output of the j-ro element AND of the i-th group (j 1,2 ,. .., N, i 1,2, ..., M, where H is the counter width (connected to the corresponding input of the (i + j-1) -th element of the IL group, output (i + j-1) -ro of the IL element the group is connected to the corresponding input of the accumulating adder. The drawing shows the block diagram of the device. The device contains the encoder 1, the element OR 2, the elements 3, 4 and 5 delays, the counter 6, the groups of elements AND 7, 8 and 9, the group of elements OR 10, the accumulating adder 11. The principle of operation of the invention is based on the following representation of the square of the number: m L (2i-i-1). Let the input variables be satisfied Then the condition (1) implies. 22 2, (2t-f1) i- () l t. + m, 4 ,, .ttTt 1. n X (2H () f ...-fX -г h The necessary operating conditions for the device are the simultaneity of the beginning of the formation of all quantities rn, as well as the synchronism of the pulses on all inputs (these pulses can, for example, be formed by the same generator). At the same time, the number of input variables whose formation of values is not complete ( the number of inputs to which pulses are received in the next cycle, we will say the number of non-zero input signals), is a non-increasing in time value. Denote the number of non-zero input signals at the moment of the beginning of their formation (i.e. the number of device inputs to which the first impulses of input packets arrive) K. At some point, the formation of one or several simultaneously input values, the number of remaining non-zero input signals is denoted by K ( obviously, K, K). If, then at some point the number of non-zero input signals decreases again - to K, etc., until the formation of the maximum of the input values is completed. Thus, we obtain the sequence that kills in time KoK-jK.j. Well oh where. Let the transition from K-, to K c, nonzero input quantities occur after n input pulses (ticks), the transition from K to K after n, input pulses, etc. Obviously, min mi. n, .nj ... n max m; . Then the formula (3) can be written in the form n, mf4 ... 4mjzk T: (2,4-r) fV 1: (2, о п п ч d-1-i) с (2,4-0. ( 4) J Suppose further that, in order to write the number K in the binary positional code, it requires C digits, then any of the numbers of the sequence K can be represented as (i ..,. O (. «V) (SP and, accordingly,; The -th summand of the right side of formula (4) is in the form: mch (2i4) (6) 1.0 Jl It is in this form that the proposed arrangement forms the conspicuous sums (4) of the encoder 1, due to the corresponding combination of the outputs on the elements ШШ, forms a binary parallel pulse to the outputs of these elements one number of non-zero input signals (encoder 1 and OR elements are pulsed). For example, encoder 1 should have seven output buses (zero input combination does not need encryption) Outputs 1-3 of the encoder are connected to the input of the first OR element, output 4 - from the input of the first and second elements OR, the remaining outputs with the inputs of the second element OR. The structure of the encoder 1 for any number of input signals can be obtained similarly. The delay element 3 delays the pulses by the time T, / M-1) 4t, and the condition T + T must be fulfilled, where 2 is the response time of the counter; T is the minimum time interval between the input pulses of the device, and the time ut must be sufficient to trigger the accumulating adder 11, i.e. may be quite small. Elements 4 and 5 of the delay (their number is equal to M-1) delay the pulses, respectively, for the time At, 2 / it, ..., (M-1) At. The number of groups of elements And 7, 8, and 9 is M - the number of outputs of the encoder 1, the number of elements AND in each group is N. The number of elements OR in group 10 is N-bM-2 (since the last element OR is born) has only one input, i.e., is a direct connection of the output of the N-ro element of the M-th group to the input of the M + N-ro discharge accumulating adder 11). I The device works in the following way. In the initial state, the pulses at the inputs of the device are absent, the counter 6 and the capacitor, and the adder 11 are set to zero. At some point, the first pulses arrive at the inputs. Due to the synchronism of the input pulses at the output of the OR 2 element, a single pulse is generated, regardless of the value of K:,. Suppose, for definiteness, K-, K 7, TeN 3. Then, for as long as the number of non-zero input signals remains seven, simultaneously with the input pulses of the device pulses will be generated on the first, second and third outputs of the encoder 1 (since 7-111 in binary numbering). The impulse from the first output of the encoder 1, arriving at the input of the first (younger) bit of accumulating adder 11 and to the second inputs of elements AND of the first group 7, causes the 11 accumulator to add to the content of the accumulating adder 11 2P + 1 (here-r, - contained in the counter 6 number), since the outputs of the AND elements of this group are connected to the bit inputs of accumulating adder 11 (through the elements of OR of group 10) with a shift by one bit to the side of the higher bits. A pulse from the second output of the diffractor 1, delayed by element 4 for a time sufficient to complete the transient processes in the accumulator, causes its contents to increase by 2 (2n + 1), since the output of element 4 is connected (via the OR element of group 10) to the input of the second bit accumulating adder 11, and the outputs of the elements of the second group are connected to the bit inputs of the accumulating adder 11 (through a group of elements OR 10) with a shift towards the higher bits by two bits.

Similarly, after the end of the transient processes in the accumulating adder 11, the pulse from the third output of the encoder 1, delayed by element 5, causes the addition of 11 to the content of the incandescent adder 11 of the number 2 (Zh + 1). Since in this case, the content of accumulative adder 11 is increased by 1 + 2 + 4 7, i.e. on K. After that, the momentum from the output element

3 delay increases content

P counter 6 per unit. So it will continue until the formation of one or several simultaneously input values is completed (the corresponding packets of input pulses are finished), and the accumulator 11 all the time will be added to the numbers (2n + 1) K, n 0, 1, 2,. ..

The processing of each input pulse requires M clock cycles instead of K + 1 clock cycles in the device prototype (3 instead of 8 in the considered example, and already when we have

4 ticks instead of 16, etc.).

Let two packets of input pulses (i.e., 101 in binary number) end at the same time. Now each input pulse will increase the content of accumulating adder 11 by the value of K (2t-1), and T1,,. .., P2-1 (since the pulses will occur only on the first and third outputs of the encoder 1), in full accordance with formula (6).

Quite similarly, the operation of the device will continue after the number of pulse packets arriving at its inputs decreases to Kj, K

a 4 input pulses do not stop (at). The accumulating adder 11 records at the same time the sum of the squares of the input numbers in accordance with formula (4) - (6).

The proposed device provides the processing of each input

impulse during M cycles (3 instead of K + 1 cycles in the device-prototype), as a result of which it has a significantly higher speed, performance in speed

0 grows very rapidly with the growth of K, so already when we have M 5, i.e. 5 cycles together 52 (winning more than 6 times).

In addition, since the strobe pulse shaper and a number of other elements are excluded from the composition of the device, it turns out to be more npocTMMj containing a smaller number

0 different types of blocks.

As a basic sample, it is advisable to adopt a device for calculating the sum of squares K of 5 C2J numbers, in comparison with which the proposed device has a much higher speed and a smaller hardware volume.

Claims (1)

DEVICE FOR CALCULATING THE AMOUNT OF SQUARES TO NUMEROUS PULSE QUANTITIES, containing an OR element, a counter, a first group of AND elements, a delay element accumulating an adder whose output is the output of the device, the bit outputs of the counter are connected respectively to the first inputs of the AND elements of the first group, characterized in that , in order to improve performance, it introduced M-1 groups of AND elements (M is the bit code of the number of input buses), M-1 delay elements, a group of OR elements, an encoder whose inputs are connected to the input buses devices, respectively, with the inputs of the OR element, the output of which through the delay element is connected to the counter input of the counter, the bit outputs of which are connected to the first inputs of the AND elements of all groups, respectively, the first output of the encoder is connected to the second inputs of the And elements of the first group and the incident discharge of the accumulating adder, 1 the ith output of the encoder is connected through the corresponding delay element (1 = 2,3, ..., M) to the second inputs of the elements of the ϊth group and the first input of the corresponding element of the OR group, the output of the j-ro element of the ith group (j = 1,2 ... -1) -ro of an element OR group is connected to the corresponding input of the accumulating adder. ί