SU1088117A1 - Error-correcting code decoder - Google Patents

Abstract

CORRECTIVE CODE DEFLATER, containing inverters connected to the input buses, the first and second groups of code elements I, the inputs of which are connected respectively to the corresponding input buses not. The outputs of the respective inverters are different from the fact that, in order to increase reliability, the first and second groups of buffer amplifiers, the first and second blocks for separating nonequilibrium combinations, the first and second elements And, the first and second supplementary an inverter, a parity checker and a block, a control, the outputs of the code elements of the first and second groups through the corresponding buffer amplifiers of the first and second groups are pairwise combined and connected to the corresponding first . output buses, the inputs of the first and second blocks of the nonequilibrium combinations are connected respectively to the input buses and inverters, and the outputs are connected to the corresponding inputs of the control unit, to the first inputs of the first and second elements And, respectively, and through the first and second additional buffer amplifiers with the corresponding second output tires, while the second inputs of the first and second elements And are connected to the clock bus, the first control input of the control unit and I h Through an additional inverter - with control inputs of the first and second (additional buffer amplifiers, outputs of the first and second elements AND connected to the control inputs of the buffer amplifiers of the first and second groups, in addition, outputs of the code elements of the first and second groups are connected to the corresponding 00 СХ) to the inputs of the control unit, the outputs of which are connected to the corresponding third output buses, and the second control input of the control unit is connected to the output of the parity check unit, the inputs of which connected to the corresponding input tires.

Description

The invention relates to a pulsed and computing technique and can be used in digital information transmission devices in codes obtained using Hadamard matrices. Decoders are known that contain input buses, inverters and a matrix of zlemeite And f 1 J. The disadvantage of this device is a large amount of equipment decoding environment, which reduces reliability. Closest to the proposed technical entity is a rectangular decoder containing inverters connected to the input buses, first and second groups of code elements I, whose inputs are connected respectively to the corresponding input buses and to the outputs of the corresponding inverter 22-. A disadvantage of the known device is the low reliability due to the impossibility of detecting an error in the input information when decrypting redundant codes. The aim of the invention is to increase reliability. This goal is achieved by the fact that the first and second groups of buffer amplifiers, the first and the second, are connected to the decoder of the correction code containing inverters connected to the input buses, the first and second groups of code elements I, whose inputs are connected respectively to the corresponding input buses and outputs of the corresponding inverters. and the second block for selecting nonequilibrium combinations, the first and second elements of AND, the first and second additional buffer amplifiers, an additional inverter, a parity checker and a control unit, The outputs of the code elements of the first and second groups, through the corresponding buffer amplifiers of the first and second groups, are combined in pairs and connected to the corresponding first output buses, the inputs of the first and second blocks are allocated to non-equilibrium combiners connected to the input buses and to the outputs of the inverter, and outputs - connected to the corresponding inputs of the control unit, to the first inputs of the first and second elements, respectively, and through the first and second, respectively, additional buffer amplifiers are connected to The corresponding second input buses, with the second inputs of the first and second elements And are connected to the clock bus, the first M control input of the control unit and through an additional inverter are connected to the control inputs of the first and second additional buffer amplifiers, the outputs of the first and second And elements are connected to control inputs of the buffer amplifiers, respectively, of the first and second groups, in addition, the outputs of the code elements of the first and second groups are connected to the corresponding inputs of the control unit, the output of which connected to the corresponding third output buses, and the second control input of the control unit is connected to the output of the parity check unit, the inputs of which are connected to the corresponding input buses. The drawing shows a functional diagram of the device. The decoder contains the first and second groups of code elements And 1 and 2, the first and second groups of buffer amplifiers 3 and 4, the first and second additional buffer amplifiers 5 and 6, the first and second elements And 7 and 8, inverters 9, additional inverter 10, the first and second non-equilibrium allocation units 11 and 12, parity check unit 13, control unit 14, input tires 15, clocking bus 16, first, second, and third highways 17-19. The input busbars 15 of the decoder are connected to the corresponding inputs of code elements I 1 of the first group, inputs of inverters 9, inputs of the parity checker 13 and inputs of the first non-equilibrium combination selection unit 11. The outputs of the inverter 9 are connected to the corresponding inputs of the code elements AND 2 of the second group and the inputs of the second allocation unit 12 for nonequilibrium combinations. The outputs of the code elements And 1 and 2 of the first and second groups are connected to the inputs of the corresponding buffer amplifiers 3 and 4 of the first and second groups, the outputs of which are pairwise combined and connected to the corresponding first output buses 17. The outputs of the first and second blocks 11 and 12 of the nonequilibrium combination are connected to the inputs of the first and second optional buffer amplifiers 5 3108 and 6, respectively, to the first inputs of the first and second elements, And 7 and 8, and to the corresponding inputs of the control unit 14. The outputs of the additional buffer amplifiers 5 and 6 are connected to the second extrusion buses 18. The second inputs of the first and second elements I 7 and 8 are connected to the bus bar 16 and the first one, the first control input of the control unit 14 and through the additional inverter 10 to the control inputs of the additional buffer amplifiers 5 and 6. The outputs of the first and second elements And 7 and 8 are connected to the control inputs of the buffer amplifiers 3 and 4, respectively, 00000000

0001111

011O 1, 1

0111100

1010101

1011010

1100110

1101001

in the case of error-free entry of the code on the input buses 15, for example, 35 when the combination 00110011 arrives in the first group of code elements I 1, an element is triggered, the input part of which is connected to the corresponding input buses 15, exactly according to which they receive 1. In this case, no other code element AND 1 in this group does not work, so. As of the four inputs of these elements, at least two 45 inputs remain in the O state. Being inverted by inverters 9, the same code is triggered in the second group of the AND 2 code element corresponding to the inverse of the received code combination jg, i.e. combinations 1100 1100. Similarly, in the second group, no other code element AND 2 works, the AND and 12 blocks do not work in this situation; 55 equilibrium combinations that are configured to decrypt only two non-equilibrium combinations.

0010110

0011001

0100101

0101010

1000011

1001100

1110000

1111111

Accordingly, at the outputs of the And 1 and 2 code elements triggered there are low level signals, and at the outputs of the non-triggered And 1 and 2 code elements, as well as the outputs of blocks 11 and 12, there are high level potentials. The latter keep the elements And 7 and 8 in the open state, and the additional buffer amplifiers 5 and 6 .- in the closed state.

When a polling signal from the decoder (supplied as a high level potential) arrives from the clock 16 of the clock, elements 7 and 8 trigger, which passes the interrogation signal (low level) to the control inputs of buffer amplifiers 3 and 4. This allows the outputs of these amplifiers to be skipped with their information inputs. Accordingly, the outputs of the buffer amplifiers 3 and 4, the code elements And 1 and 2 which did not work, remain high level signals, and the outputs of the buffer amplifiers 3 and 4, 74 but the first and second groups. The second control input of the control unit 14 is connected to the output of the parity check unit 13, the remaining inputs of the control unit 14 are connected to the outputs of code elements I 1 and 2 of the first and second groups, and the outputs of the control unit 14 are connected to the corresponding third output buses 19. Operation The decoder is illustrated by the example of decoding a correction code formed from an 8x8 Hadamard matrix. This code has the following sixteen combinations: the code elements AND 1 and 2 of which have worked are a low level signal. The outputs of the buffer amplifiers 3 and 4, which are related to direct and corresponding inverse coding combinations, are pairwise combined by mounting OR (output level coupling resistors are not shown). Such combined outputs of the buffer amplifiers 3 and 4 are connected to the first output buses 17, in which the decoded output signal from the triggered pair of buffer amplifiers 3 and 4 appears. Since the input bus 15 receives an error-free code that contains an even number of units, then the parity check unit 13 does not work, while there are no signals on the third output buses 19. Similarly, the decoder is triggered when any other equilibrium code combinations arrive. Upon receipt of one of the nonequilibrium code combinations in the decoder, one of the blocks 1 and 12 is activated. The decoding is performed as follows. For example, when the code 1111 1111 arrives in the first group, all And 1 code elements are triggered, and from the output of block 11 a low level signal is received. As a result, AND 7 is closed, blocking the polling; buffer amplifiers 3, and the additional buffer amplifier 5 opens, allowing the clock signal to pass. In this case, in the group of inverse combinations, with the code 1111 1111, neither the code element I 2 nor block 12 works. When the signal comes from the bus 16. the clocking to the output of the additional buffer amplifier 5 passes a signal, which ensures that the decoded output signal is transmitted to the corresponding output bus 18. As in the previous case, the parity checker 13 does not work, and no signals are output to the output of the control unit 14. Similar work takes place when deciphering a nonequilibrium combination containing all zeros. In this case, the unit 12 is connected, connected to the outputs of the inverters 9, where. in this case, a combination of 1111 1111 is formed. In the operation of the decoder when correcting single errors, it is necessary to select two cases of input information distortions: an error in the type of aiming, when true input signal O goes to state 1, and an error in the form of erasure, when, instead of the true signal 1, O arrives. If in the equilibrium combination 0011 0011 there was a distortion of the form of the tip, as a result of which the input bus 15 received the code 0111 0011, then in the first group of code elements AND 1 the same element is triggered, which relates to an unmistakable combination, since all of its input signals receive 1 signal. In the group of code elements And 2, no element is triggered, since when the input combination is inverted, the code 1000 1100 is formed, in which none of the AND 2 code elements will have 1 signal on all four inputs. Blocks 11 and 12 are not sensitive to this situation either. The activation of code element I 1 is enough so that there is a regular output signal on the output bus 17 corresponding to the true code 0011 0011. However, the mere fact of an error has not been missed. In this case, the output of the parity check block 13 is an output signal indicating a violation of the evenness of the number of units in the incoming input combination. This signal is fed to the input of the control unit 14 and, when a signal arrives from the 16-speed bus, a signal appears on the corresponding output bus 19 indicating the error correction in the first group. If in the equilibrium combination pro: an erasure type error occurred, for example, instead of the combination 0011 0011, the combination 0010 OOP arrived, then the decoder works in the following way. In the first group of code elements I 1, not a single element works, since there are only three units on their inputs. However, in the second group, where after inversion the code 1101 1100 is formed, the code element And 2 is triggered, which corresponds to the true input OOP combination of the OOP.

As a result, despite the absence of a signal from the first group, the corresponding output signal formed by the code element I 2 of the second group appears on the corresponding output bus 17. In this case, the control unit 14 issues a signal to the corresponding output, bus 19, to the evidence of error correction by the second group.

In the combination of 1111 1111, only errors of the form of erasure are possible, and in the combination of 0000 0000 only the type of guidance.

If erasure occurred, for example, the code 1101 1111 arrived, then block 11 is operated. This blocks the clocking signal from polling buffer amplifiers 3 and allows the signal to be output by an additional buffer amplifier 5, from where this signal passes to the output bus 18 corresponding to an error-free combination 1111 1111. this in the second group, where the code 0010 0000 is held at the outputs of the inverters 9, neither the code element AND 2 nor the block 12 is broken.

The fact of violation of the parity of the units in the received combination is recorded by block 13, the signal from the output of which is triggered by the control unit 14, which on the corresponding you, the front bus 19, triggers an error correction signal by the first group.

When combinations 0000 0000 are received, a block 12 operates in the decoder, which in fact introduces the code 1111 1111, obtained after the initial combination has been inferred. The mechanism of action of this unit and the decoder is generally similar to that considered.

If any of the forbidden combinations come to the input. If the control module 14 is triggered, which is not included in the error-free or containing any single error, the signal on this situation is transmitted to the corresponding output bus 19, indicating a multiple error.

Finally, the decoder controls its own errors. In particular, if, when detecting a parity violation, the clocking signal records in block 14 the fact that two groups operate at once, then a control signal arriving at the corresponding output bus 19 is detected, indicating that a decryption error has been detected.

Thus, due to the introduction of buffer amplifiers, additional, AND elements, blocks of non-equilibrium combinations, a parity check block, a control block and an additional inverter, the redundant code is reliably deciphered in the device.

Claims (1)

CORRECTING CODE DECODER, containing inverters connected to the input buses, the first and second groups of code elements AND, the inputs of which are connected respectively to the corresponding input buses and. ·. the outputs of the respective inverters, characterized in that, in order to increase reliability, the first and second groups of buffer amplifiers, the first and second blocks for distinguishing nonequilibrium combinations, the first and second elements And, the first and second additional buffer amplifiers, an additional inverter, a check unit are introduced into it on the parity and the control unit, and the outputs of the code elements And the first and second groups through the corresponding buffer amplifiers of the first and second groups are paired and connected to the corresponding first output to the buses, the inputs of the first and second blocks for distinguishing nonequilibrium combinations are connected respectively to the input buses AND with the outputs of the inverters, and the outputs are connected to the corresponding inputs of the control unit, to the first inputs of the first and second elements And, respectively, and through the first and second additional buffer amplifiers are connected to the corresponding second output buses, while the second inputs of the first and second elements And are connected to the clock bus, the first control input of the control unit and through additional the second inverter - with the control inputs of the first and second additional buffer amplifiers, the outputs of the first and second elements AND are connected to the control inputs of the buffer amplifiers, respectively, of the first and second groups, in addition, the outputs of the code elements And the first and second groups are connected to the corresponding inputs of the control unit, the outputs of which connected to the corresponding third output buses, and the second control input of the control unit is connected to the output of the parity check unit, the inputs of which are connected to the corresponding inputs single tires. SU ,. „1088117