SU1133624A1 - Storage with error correction - Google Patents

Abstract

STORAGE DEVICE p. FIXED ERRORS containing the drive, the first and second registers, the first block of the EXCLUSIVE OR elements, the AND-OR element, the decoding block, the control block, the information input of the storage device connected to one output of the first register, the output of the storage device connected to the information inputs of the first and second registers , the outputs of the second register and other outputs of the first register are connected to the inputs of the first block of the ULAWNE OR elements, the outputs of which are connected to the same inputs of the I-SHSh element, the output of which is connected to the first input control unit one, second, third and fourth. the inputs of which are the control inputs of the device, the first, second and third outputs of the control unit are connected respectively to the control inputs of the accumulator and the first and second registers, the fourth output of the control unit is the control output of the device, characterized in that devices, a switch, a second block of EXCLUSIVE OR elements, a decoder, an OR element, a third register are entered into it, and the information inputs of the switch are connected to the outputs of the second register and yes | The first register, the fifth and the sixth outputs (L of the control unit are connected to the control inputs of the switch, the outputs of which are connected to the inputs of the decoding unit, the outputs of which are connected to the inputs of the decoder and the OR element, the output of which is connected to the fifth input of the control unit, the outputs of the switch and the decoder are connected to the inputs of the second block ED of the EXCLUSIVE OR elements, the outputs of which are connected to the information inputs of the third register whose outputs are the information outputs of the device controlled The input of the third register is connected to the seventh output of the control unit, the outputs of the decoder are connected to other inputs of the AND-OR element.

Description

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The invention relates to computing and can be used to create highly reliable storage devices and systems made on functional units with a high degree of integration.

A self-monitoring memory device is known, which contains a drive, forward and reverse code address registers, a decoding coding unit, a comparison circuit, a counter, a distributor, and a buffer register.

The disadvantages of this storage device are the large hardware costs for the implementation of the counter and signal distributor, which reduces the reliability of the device, and, in addition, to correct the detected errors, additional time is needed to go through all the possible combinations and check the correct type of each of the sets that reduces the speed of the system as a whole.

The closest to the technical essence of the invention is a memory device containing a drive connected to the inputs. the forward and reverse code registers whose outputs are connected to the block of detection of failed bits, the correction device whose input is connected to the output of the register of the direct code, the first information output with the block of elements AND, the second information code with. a code equality circuit, to the second input of which the output of the unit for detection of failed bits and the control unit 2j is connected.

A disadvantage of the known device is that the correction is low. ability to apply code.

The purpose of the invention is to increase the reliability of the storage device.

This goal is achieved in that the error-correcting memory device containing the accumulator, the first and second registers, the first block of the EXCLUSIVE OR elements, the AND-OR element, the decoding unit, the control unit, and the information input of the accumulator is connected to one output of the first register, the accumulator outputs are connected to the information inputs of the first and second registers; the outputs of the second register and other outputs of the first register are connected to the inputs of the first

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block EXCLUSIVE OR, the outputs of which are connected to one input of the element whose output is connected to the first input of block 5, the control, the second, third and fourth inputs of which are the control inputs of the device, the first, second and third outputs of the control unit are connected respectively to

About the control inputs of the accumulator and the first and second registers, the fourth output of the control unit is the control output of the device, the switch is entered, the second block of elements

S EXCLUSIVE OR, decoder, element OR, third register, and the information inputs of the switch are connected to the outputs of the second register and other outputs of the first register, the fifth

0 and the sixth outputs of the control unit are connected to the control inputs of the switch, the outputs of which are connected to the inputs of the decoding unit, the outputs of which are connected to the inputs

5 of the decoder and the OR element, the output of which is connected to the fifth input of the control unit, the outputs of the switch and the decoder are connected to the inputs of the second block of the EXCLUSIVE

0 OR, the outputs of which are connected to the information inputs of the third register, the outputs of which are information outputs of the device, the control input of the third register is connected to the seventh output of the control unit, the outputs of the decoder are connected to the other inputs of the element Il.

FIG. 1 shows a structural diagram of the proposed storage device; Fig. 2 shows an example implementation of the control unit; in fig. 3 decoding unit.

The storage device contains a drive i, the output of which is connected to the information inputs, registers of the DIRECT (R11K) 2 and reverse ROCK (ROCK) 3 codes. The inverse outputs of register 2 are connected to the informational inputs of the accumulator, and the direct outputs

9 RPK 2 and inverse outputs ROCK 3 are connected to the inputs of switch 4 built on I-EPI elements and to the inputs of a block of EXCLUSIVE OR 5o elements. The outputs of the switch are connected to the inputs of decoding unit 6 and to the first inputs of a block of elements IS1 SHOCKING OR 7 whose outputs are connected with information311

and the inputs of the output register 8, the outputs of the latter are the information outputs 9 of the memory device. The outputs of the decoding block 6 are connected to. the inputs of element LI 10 and the inputs of the decoder 11, the outputs of which are connected to the second strokes of block 7 and to the first inputs of the element AND-OR 12, with the second inputs of which are connected the outputs of the block of elements EXCLUSIVE OR 5. The outputs of the elements OR 10 and AND-12 are connected with the inputs of the control unit 13, the outputs of which are connected to the control inputs of the registers of forward 2, inverse 3 codes, output register 8, as well as to the control inputs of accumulator 1 and switch 4.

Each of the device registers is a group of D-triggers. For example, in register 2, the inputs D of all flip-flops are connected to the outputs of the nick Pitle 1, the direct outputs of the flip-flops are connected to the inputs of block 4, and the inverse ones to the inputs of accumulator 1. Synchronous inputs From all triggers are connected to each other and connected to one of the outputs of the control unit.

An example implementation of the control unit 13 is shown in FIG. 2. It consists of TX triggers t4, RS trigger 15, decoder 16, elements AND 17, OR 18, and I-STI 19. After power is applied, the initial state of the control unit is set by the Reset signal, which sets all 2 triggers In the zero state, and the operation of the control unit begins with a start signal, arriving at the nd input 20. The control unit has an input 21 of the Reset signal and an input 22, which receives signals from the clock source. On output 23 of the control unit, an unrecoverable error signal is output.

The implementation of the decoding block depends on the correction code used in the storage device. To use the Hamming code, a decoding block is easily constructed using modulo-two adders, whose inputs receive the values of codeword bits included in a data-controlled group. The decoding unit (Fig. 3) contains three 4-input adders 24 modulo two, the inputs of which are connected to the outputs of the switch 4, and the outputs are connected

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with the inputs of the corresponding elements NOT 25, the outputs of which are connected to the inputs of the IL 10 circuit and the decoder 1, bits 26 of the control code, and

bits 27 read words.

The storage device operates as follows.

A word coded by the applied error correcting code is stored in the memory. When counting from the selected accumulator cell, the control unit generates a control signal, allowing the code signal to be received. words on the PKK 2. Then the control unit 13 generates a signal on which the contents of register 2 is transmitted through the switch 4 to the decoding unit 6, in which the values of the test ratios are calculated.

 If all test ratios

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equal to zero means the word read from the accumulator contains no errors), then the control unit allows the reception of the word to the output register 8 by the signal from the output of the element OR 10. At the same time, this enabling signal is provided to the consumer and allows the information from the outputs of register 9 to be copied. If at least one The test ratio is different from .е. the decoded word contains an error, then the signal at the output of elenench OR 10 leads to the control unit to sequence control signals

follow cich action. The control unit generates a signal arriving at the control input of accumulator 1, according to which the contents of the direct code register through inverse outputs

is written to the same cell of the accumulator, and then read and received on ROCK 3.

Thus, in these two registers are direct and reverse

5 codes read words. These codes from the direct outputs of register 2 and inverse outputs of register 3 enter into block 5, consisting of the elements EXCLUSIVE OR, in which

For a drop in the bits of the received codes, the set of numbers of the failed bits is determined. At the outputs of block 5, there are 1 at those positions that correspond to the numbers of the failed bits of the drive cell.

At the same time, the computed ratios calculated for the contents of the direct code register are decrypted. The single signals at the outputs of the decoder 11 correspond to the numbers of the expected error bits. Information from the outputs of the switch 4 is transmitted to a block of EXCLUSIVE OR elements 7, in which the estimated erroneous bits are corrected (those bits for which the corresponding outputs of the decoder are present are inverted, and the word enters the information inputs of the output register 8. At the same time, the same digits The codes from the outputs of the decoder and the block of detection of failed bits are fed to the corresponding inputs of the AND-OR element. 12. At the output of the AND-OR element, a single signal appears only if in one pair of like codes of the codes coming from the decoder 11 and block 5. Units at the output of the element 12 of the single signal mean that the set of numbers of the bits to be corrected falls into the set of numbers of the failed bits. the signal that permits the reception of the corrected word on register 8 and reading from its outputs 9. If the output of the AND-OR 12 element in vgLS is a zero signal, it means the set of numbers of the bits to be corrected, determined when decoding the pr th code does not get to the set of failed bits. In this case, the control unit generates a signal arriving at the control inputs of the switch 4 and allowing the transfer through it of the inverse content ROK 3 / i.e. right code). This code word enters the decoding unit and on one of the inputs of block 7. In decoding unit 6, decoding is performed in the same way as in the first case. If all calculated test ratios are equal to zero (this is possible if G multiple failure caused the T multiple error), then the control unit allows the reception of the word in register 8 and reading from its outputs 9. Otherwise, in block 7, the estimated erroneous bits, the numbers of which are determined by the decoder 11, and the word arrives 46 at the information inputs of register 8, and the hit of the multis. the correctness of the bits to be corrected, as determined by decoding the inverse contents of the register. 3 in many failed bits. In the case of the appearance of a single signal at the output of the element AND-OR 12 (which indicates the presence of such a hit), the control unit 13 permits writing the word to register 8 and reading from it. If there is a zero signal at the output of element I2, the control unit signals that the detected errors cannot be corrected by generating a signal at output 23; 1fixable error. Consider the operation of the proposed storage device when using a Hamming code correcting one error. Let the word 0111101 1234567 be written in a certain cell. At the positions and 4, the values of the check bits. Let bits 2.3 and 5 fail, with 2 and 3 bits being given continuously O, and 5 bits d- Then, when reading a word on the PKK, we get 0001101, i.e. word contains 2 errors. When decoding it, it is determined that the error is in the first bit (QO 1) (0, after writing the return code of the RPC content, read the code on the reverse code register, we get code 10001 10. The content of the PKK and ROCK is received in block 5, which determines that my and inverse codes are the same in bits 2,3 and 5. These bits form the set of numbers of the failed bits. The AND-OR 12 element determines that the number G1 | erroneous bit, defined when decoding the contents of the PKK, does not match with one of the elements of the i-sequence of the numbers of the failed bits. Poet It is decoding the inverse value of the content of the ROK, i.e., 0111001, entering the decoding unit. When decoding a word, it is determined that the error is 5 bits (1 O 1) 2 (5, 0), In this case, the number 5 is an erroneous bit Yes, it falls into the set of 2,3,5 numbers of the failed bits, therefore the control unit allows the issuance of the corrected word from the output register 8 to the outputs 9: 0: 1 1 1 О 1. 1336, 248. Thus, in the proposed memory device correction oshi side. the detecting and correcting abilities of applied correction codes are increased, and consequently, the reliability of the device is increased.

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Claims (1)

ERROR MEMORY DEVICE, containing a drive, first and second registers, the first block of EXCLUSIVE OR elements, an AND-OR element, a decoding unit, a control unit, the drive information input being connected to one of the outputs of the first register, the drive outputs are connected to the information inputs of the first. and the second registers, the outputs of the second register and other outputs of the first register are connected to the inputs of the first block of EXCLUSIVE OR elements, the outputs of which are connected to one of the inputs of the AND-OR element, the output of which connected to the first input of the control unit, the second, third and fourth inputs of which are the control inputs of the device, the first, second and third outputs of the control unit are connected respectively to the control inputs of the drive and the first and second registers, the fourth output of the control unit is the control output of the device, characterized in that, in order to increase the reliability of the device, a switch, a second block of EXCLUSIVE OR elements, a decoder, an OR element, a third register, and information inputs are introduced into it the switch is connected to the outputs of the second register and other outputs of the first register, the fifth and sixth outputs of the control unit are connected to the control inputs of the switch, the outputs of which are connected to the inputs of the decoding unit, the outputs of which are connected to the inputs of the decoder and the OR element, the output of which is connected to the fifth input of the control unit , the outputs of the switch and the decoder are connected to the inputs of the second block of elements EXCLUSIVE OR, the outputs of which are connected to the information inputs of the third register, the outputs of which are information outputs of the device, the control input of the third register is connected to the seventh output of the control unit, the outputs of the decoder are connected to other inputs of the AND-OR element.