SU1095183A1 - Error correction device - Google Patents

Abstract

A DEVICE FOR CORRECTING ERRORS containing a trigger register, a decoder, the first element OR, a group of elements AND, a group of elements OR, and the information inputs of the trigger register are information inputs of the device, the outputs of the decoder corresponding to the permitted combinations are connected to the inputs of the first element OR, the outputs the decoder corresponding to forbidden combinations with a single error in the i-th bit are connected to the inputs of the i -th element of the OR group, the output of which is connected to the first input of the i-th element AND the group, the output of which is connected to the counting input of the i-th digit of the trigger register, the second inputs of all elements of the AND group are combined, in order to expand the functional capabilities of the device by correcting double errors and generating error rate signals, into it the shift register, the second and the third elements are entered, the two elements of the IPI-NOT, the four elements AND, the element NOT, the two delay elements and the group of modulo-two adders, the outputs of the register connected to the first inputs of the corresponding adders modulo two groups, outputs of adders modulo two groups are connected to the inputs of the decoder and are information inputs of the device, the outputs of the OR groups are connected to the inputs of the second OR element, the output of which is connected to the first input of the first OR-NOT element and is a single onshbki output device, the output of the first element OR is the output of the device health and is connected to the second input of the first element OR NOT and the input of the element NOT whose output g is connected to the first inputs of the first and second elements And, the outputs of which (L ryh connected to the inputs of the third (Element OR, the output of which through the first delay element is connected to (the second input of the first element And the group to the input of the second element. delays, the output of which is connected to the second input of the second element AND, the outputs of the shift register are connected to 1C by the second inputs of adders in O1 module two groups and the inputs of the second element OR NOT, the output of which 00 is connected to the first input of the third element AND, the output of which is connected a single input of the lower order of the shift register, the first input of the fourth element, and is connected to the output of the second delay element,. , the output of the first, OR-NOT element is the output of a double error of the device and is connected to the second inputs of the third and fourth elements AND, the code of the fourth element AND

Description

1095183 is connected to the shift input of the register of the house shift, the second input of the first element, K is connected to the installation input. the sdriga register

The invention relates to computing and can be used in devices for processing and transferring discrete information.

A device for error correction is known, which contains the receive register, the matrix decoder, the first one, the WL element, the shift register, the AND element, the first prohibition element, the supporting element, the first input of the AND element is the first input of the device, the second input of the AND element is connected to the first input of the shift register and the output of the first interdiction element, and the output with the second input of the shift register, the output of which is connected to the first input of the reception register, the output of which is connected to the input of the matrix decoder, the outputs of which are connected to the inputs of the first the OR element, the output of which is connected to the first input of the first prohibition element and the device output, the second input of the device connected to the input of the delay element, the output of which is connected to the second input of the first prohibition element, the second and third prohibition element, memory register, key block, second element OR and a single error decoder, the input of which is connected to the output of the reception register, and its outputs to the inputs of the second SHS element, the output of which is connected to the first input of the second prohibition element, the second input of which is connected to the second ode device, and the output - with the first input of the third prohibition element, the second input of which is connected to the output of the first OR element, and the output to the first input of the key block, the second input of which is connected to the memory controller output, and the output to the second input of the receive register .

The disadvantage of this device is that it makes correction of double errors only

case where the location of one of them is known. If errors are caused. two failures, they cannot be fixed.

The closest technical solution to the present invention is an error correction device containing a register of receiving elements, a decoder, an OR element, a fixation element, the end of the reception of a code combination, a prohibition element, the outputs of the register of receiving elements are connected to the inputs of the decoder, the outputs of which correspond to the allowed combinations, connected to the inputs of the OR element, the output of the RSHI element is connected to the control input of the apret element, the information input of which is connected to the output of the fixation eye element The reception of a code combination, an OR group of elements and an AND group of elements; the output of the prohibition element is connected to the first inputs of the AND elements of the group: the device clock input is connected to the second inputs of the AND groups, the decoder outputs corresponding to the forbidden combinations are connected to the inputs of the elements OR groups, the outputs of which are connected to the third inputs of the corresponding elements AND groups, the outputs of the elements AND groups Connected to the inputs of the register of receiving elements 2.

The disadvantage of the device is its narrow functionality, which consists in the fact that. it does not allow to correct double errors and generate signals about

multiplicity of errors.

The purpose of the invention is to expand the functional capabilities of the device by correcting double faults and generating signals about the magnitude of errors. ..

The goal is achieved in that an error correction device containing a trigger register. the decoder, the first element OR, the group of elements AND, the group of elements OR, and the information inputs of the trigger register are information inputs of the device, the output of the decoder corresponding to the permitted combinations are connected to the inputs of the first element OR, the outputs of the decoder corresponding to the prohibition of the combinations with a single error in the iM bit is connected to the inputs of the i-ro element OR of the group, the output of which is connected to the first input of the i-ro element AND of the group whose output is connected to the counting input of the i-ro bit of the trigger register Istra, the second inputs of all elements AND groups are combined, the shift register is entered, the second and third elements OR, two elements OR NOT, four elements AND, the element NOT, two delay elements and a group of modulators are two, and the outputs of the register are connected to the first inputs of the corresponding modulo adders are two groups, the outputs of modulo adders are two groups connected to the descriptor descents and are information inputs of the device, the outputs of the OR elements are connected to the inputs of the second OR element, the output of which is connected to the first the input of the first element OR NOT is the output of a single device error, the output of the first element OR is the output of a corrected

device and is connected to the second input of the first OR-NOT element and the input of the NOT element, the output of which is connected to the first inputs of the first and second AND elements, the outputs of which 40 are connected to the inputs of the third OR element, the output of which is connected to the second input through the first delay element The first element AND group and the input of the second delay element, output 45 of which is connected to the second input, the second element AND, the outputs of the shift register are connected to the second inputs of modulators two groups and the inputs isToporo of the element OR NOT, output d15o

which is connected to the first input of the third element And, the output of which is connected to the single input of the lower digit of the shift register, the first input of the fourth element AND is connected to the output of the second delay element, the output of the first element OR NOT is the output of the device double error and is connected to the second the inputs of the third is that the received word is encoded with a redundant code that allows for double errors to be corrected (i.e., the code distance is not

If there are no errors in the received word, 1 then the word recorded in register 1 without changes through the adders 2 modulo two groups is fed to the inputs of degrader 3. At one of the decoder's outputs, which are connected to the inputs of the OR 5 element, there is a unit level. This single signal A of the fourth element I, the output of the fourth element I is connected to the shift input of the shift register, the second input of the first element I is connected to the installation input of the shift register and is the device start input. The drawing shows a block diagram of a device for correcting errors. The device for correcting errors includes the trigger register 1, group 2 modulo-2 adders, decoder 3, group 4 elements OR, first element OR 5, second element DI 6, first and second elements OR-NOT 7 and 8, third and the fourth elements And 9 and 10 group 11 elements And, the register 12 shift, the element NOT 13, the input 1L of the shift register 12 shift, the information inputs 15 of the device, the information outputs 16 of the device, the output 17 of the health of the device, the output 18 of a single device error, the output 19 double errors set. device, the launch of the device 20, the first and second elements And 21 and 22, the third element OR 23, the first and second delay elements 24 and 25. The device operates as follows. In the initial state, register 1 and shift register 12 are reset. The information inputs 15 of the device receive the decoded word and write it into register 1. Next, less than five). After receiving the word in register 1, a single impulse is applied to input 20 of the device start, indicating the beginning of the decoding of the word. This signal is used to reset the shift register 12 and, if there are errors, correct them. The process of functioning of the device in three different situations that may occur when decoding a word is as follows. j10 arrives at the output 17 of the health of the device and indicates that the decoded word can be read from the information output 16 of the device. At the same time, this signal is fed to the input element NO 13. Due to this, the elements And 21 and 22 are closed. At outputs 18 and 19 of the device in this situation, the code is O, If there is one error in the received word, then the word is also from register 1 unchanged through adders 2 modulo two groups are fed to the inputs of the decoder 3. At one of the outputs of the decoder 3, connected with the corresponding element OR 4 groups, a single signal appears. This signal is sent to the corresponding element AND group 11 and through the element OR 6 to the output 18 of a single device error, evidence of a single error. At outputs 17 and 19, the code is O. A single signal from the start-up input 20 of the device enters the second input of the element. And 21 and opens it, since code 1 comes from the output of element NOT 13. A single signal through the element OR 2 and delay element 24 opens one of the elements of group 11, corresponding to the bit received with distortion and in register 1 Perform: Corrects a distorted bit by inverting by applying a signal to the trigger input. At one of the outputs of the decoder 3, connected to the inputs of the element OR 5, a single level appears, which is output to the device output 17, indicative of the end of word decoding. Simultaneously, at the output of the element HE 13, the code O appears, which closes the elements AND 21 and 22. The decoded word is output to the output 16 of the device. I. ., .- ,, If there are two errors in the received word, then there will not be a single signal on any output of the decoder 3. At the exit of the elements: OR 4 groups of the element OR. 5 and the element OR 6 code O. At the output of the element ILI-NOT 7, and therefore, at the output 19 of the device, a code which indicates the presence of a double error. The shift register 12 is pre-cleared by the signal From the device start input 20. Therefore, at the output of the element OR-NOT, 8 code 1 and the unit level from the output 36 of the element OR-NOT 7 opens Element I 9 and the unit is written to the low-order bit of the shift register 12. Consider two cases: one of the errors occurred in the low-order received words; There is no error in the younger word of the received word The lower order bits of the word are located in register 1 bits shown on the right. In the first case, the occurrence 1 at the output of the low bit of the shift register 12 causes the low distorted bit of the received word to be inverted using the corresponding adder 2 modulo two. In this case, at the output of adders 2. modulo two groups, a word appears with only one error. Therefore, at the corresponding output of decoders 3, code 1 appears, which is fed to the input of one of the elements of OR 4 group with the appearance of code 1 at the output of the first element 24 delay. One of the elements of group 11 and 11 is opened, and the second error is corrected. At one of the outputs of the decoder 3, connected to the inputs of the element OR 5, a single signal appears, which passes to the output of the element of RSHI 5 and indicates the decoding of the received word. At the same time, the code O from the output of the element NOT 13 enters for the first time the inputs of the elements 21 and 22 and closes them. In addition, the code About from the output of the element OR NOT 7 enters the input of the element And 10 and prohibits the passage of a single signal from the output of the second element 25 of the delay in the bus shift register 12 shift. The corrected word is displayed on device output 16. In this case, the low-order word is corrected due to the presence of 1 in the low-order bit of the shift register 12, and the other distorted bit is inverted by applying code 1 to the corresponding trigger of the register 1. When there is no error in the low-order de-received word then occurrence 1 in the low order of de reg. 12 does not result in the output of adders 2 modulo two groups of words that have one distorted bit. Therefore, on all outputs of the decoder 3, the code O, Single signal .c output of the element OR- NOT 7 permits passing s code 1 output from the second member 25 via the AND gate eaderzhki units X

Claims (1)

DEVICE FOR CORRECTING ERRORS, containing a trigger register, a decoder, a first OR element, a group of AND elements, a group of OR elements, the information inputs of a trigger register being information inputs of a device, the decoder outputs corresponding to allowed combinations are connected to the inputs of the first OR element, decoder outputs, corresponding to forbidden combinations with a single error in the i-th category, connected to the inputs of the t-th element OR group, the output of which is connected to the first input of the i-th element AND groups the output of which is connected to the counting input of the ΐ-th category of the trigger register, the second inputs of all elements AND groups are combined, characterized in that, in order to expand the functionality of the device by correcting double errors and generating error multiplicity signals, a shift register is entered into it, the second and the third elements are OR. two elements OR-HE, four elements AND, element NOT, two delay elements and a group of adders modulo two, with the outputs of the register connected to the first inputs of the respective adders modulo two groups, the outputs of the adders modulo two groups connected to the inputs of the decoder and are information the inputs of the device, the outputs of the OR elements of the group are connected to the inputs of the second OR element, the output of which is connected to the first input of the first OR-HE element and is the output of a single device error, the output of the first OR element is the health of the device and is connected to the second input of the first OR-HE element and the input of the NOT element, the output of which is connected to the first inputs of the first and second AND elements, the outputs of which are connected to the inputs of the third (OR element, the output of which through the first delay element is connected to (the second the input of the first element AND of the group and the input of the second element T of the delay, the output of which is connected to the second input of the second element Y, the outputs of the shift register are connected to the second inputs of the adders modulo two groups and the inputs of the second element IL AND-HE, the output of which is connected to the first input of the third element And, the output of which is connected to the unit input of the least significant bit of the shift register, the first input of the fourth element And is connected to the output of the second delay element,. The output of the first, the OR element is NOT a double error output of the device and is connected to the second inputs of the third and fourth AND elements, ^{1 the} output of the fourth AND element J .... 1095183 is connected to the shift input of the shift register, the second input of the first element, And is connected to the installation input of the shift register and is the start input of the device.