SU1059576A1 - Device for checking digital units - Google Patents

Abstract

A DIGITAL NODE CONTROL DEVICE containing a shift register, a modulo-two adder, a control unit, a display unit, a switch unit, a counter, two switches, a single pulse driver and a master oscillator, the first output of the control unit being connected to the control input of the register. shift, the installation input of which is connected to the first output of the switch unit, the reset input of the control unit, the installation input of the digital node being scanned, the installation input of the single im- ,: pulse generator and the installation input of the counter, the counting input of which is connected to the second output of the control unit and information input of the adder on the mon. a two, the output of which is connected to the information input of the shift register, the group of outputs of which is connected to the group of inputs of the adder. the two, the shift register output group is connected respectively to the first group of information inputs of the first switch, the second group of information inputs of which is connected respectively to the group of outputs of the counter, the overflow output of which is connected to the first input of the first group of information inputs of the second switch, the second input of the first group of information inputs connected to the output of the single pulse generator, the synchronous input of which is connected to the output of the master oscillator, with the third input of the first The second group of information inputs of the second switch, the first, second and third inputs of the second group of information inputs of which are connected respectively to the shutdown, start and synchronization outputs of the tested node, the first, second, third and fourth outputs of the second switch are connected respectively to the first, second, third and the fourth information inputs of the control unit, the controls, the input of the second switch is connected to the second output of the switch unit, the third output of which is connected to the O $ 5 equalizing input of the pho worldviewer (L night pulses, the fourth output of the switch unit is connected to the control input of the first switch, the output group of which is connected to the indication input group of the indication, t-ff, which, in order to increase the reliability of the control, the block is entered delays, the third switch and the coding accuracy analysis block, the auxiliary input of the display unit is unified with the output of the coding reliability analysis block, whose information input is connected to the output of the third switch and the second input 05 of the second group of information inputs of the second switch, the information output of the tested node is connected to the input of the delay unit and the input of the third switch, the group of inputs of which is connected respectively to the outputs of the delay unit, the synchronization output of the checked node is encoded, the analysis unit encoding accuracy contains two elements of addition modulo two, two triggers, two elements NAND, element AND, two elements NOT and three keys, with

Description

the sync input of the block is connected to the first input of the first addition unit modulo two, the second input of which is connected to the output of the first key, the power supply bus of the block, the output of the second key and the first input of the second addition element modulo two, the second input of which is connected to the information input of the block, the output of which is connected to the output of the first element NOT, the input of the first key is connected to the input of the second key, the input of the third key, the information input of the second trigger and the zero potential bus of the block, the output of the third key dinene with the power supply bus of the unit and a single input of the first trigger, the synchronous input of which is connected to the output of the first AND-NO element, the first input of which is connected to the output of the first

trigger and input of the first element is NOT, the second input of the first element AND-H is connected to the output of the element AND, the first input of which is connected to the output of the second element NOT, the input of which is connected to the output of the second addition element rto module two and the synchronous input of the second trigger whose zero input is connected with the power supply bus, the block and the zero input of the first trigger, the information input of which is connected to the output of the first addition element modulo two and the first input of the second AND – NE element whose output is connected to the single input of the second rigger inverse output of which is connected to the second input of the AND gate and a second input of the second AND-NO element.

The invention relates to computing and can be used to encode logic, the state of digital systems, their control and search for faulty components (connecting elements, microcircuits, typical replacement elements and modules, devices and subsystems, etc.).

A device for detecting faulty modules in digital systems is known, containing a common frequency generator with a digital object and analyzing a selected number of control points of a digital object that is limited once and for all (the selected points are rigidly connected to the device input) 1 J.

The disadvantages of this device are the impossibility of using it in the most widespread asynchronous systems, as well as the inability to carry out diagnostics with an accuracy of a typical replacement element in complex digital objects, the diagnostics of which requires the analysis of a relatively large and not always predictable number of control points.

Closest to the present invention is a device for monitoring "digital objects" containing a shift register, an adder, a control unit, an indicating unit, a control panel, a first switch, a counter, a single pulse driver, a master oscillator, and a second switch, the first and second counters connected respectively with the first exit

2

control unit, the first output of the counter is connected to the first input of the first switch, the first output of the control unit is connected to the first inputs of the counter and adder, the output of which is connected to the first input of the shift register, the second output of the control unit -. laziness is connected to the second input of the register. shift, the first output of which

0 is connected to the second input of the adder, the first output of the control panel is connected to the third input of the shift register and the fifth input of the control unit, the second and third inputs of the first switch are connected respectively to

the second output of the shift register and the second output of the control panel, and the output to the input of the display unit, the second output of the counter is connected to the first input of the second switch, the second input of which is connected to the third output of the control panel, the first output of which is connected to the input of the digital object, third, fourth , the fifth and sixth inputs of the second switch are connected to the group of outputs of the digital object, and the first, second, third and fourth outputs of the second switch are connected to the first, second, third and fourth inputs of the bl Single control, oscillator output is connected to the seventh and eighth inputs of the second switch and the first input of the single impulss, second and third inputs

5 of which are connected respectively to the first and fourth outputs of the control panel, and the output to the ninth input of the second switch. The known device allows one to take a binary signal from any clock, a digital object built on an element base with any degree of integration, and to diagnose both synchronous and asynchronous digital objects with any degree of diagnostic resolution. It is endowed with effective self-monitoring CsJ . However, the known device does not exclude the effect on the conversion result of random failures, noise and transients. It should be noted that only one erroneous conversion result, for example, when searching for a faulty component can lead to its incorrect definition. In order to avoid the effect of random failures and interference, it is necessary to re-encode (convert) the binary signal at each control point of the object, which leads to double the loss of time. However, re-encoding does not allow to avoid an unreliable result in the case of a stable coincidence of the front of the synchronization pulse and the front of the pulse of the encoded signal. The purpose of the invention is to increase the reliability of the control. The goal is achieved in that a device for controlling digital nodes, containing a modulo two adder shift register, a control unit, a display unit, a switch unit, a counter, two switches, a single pulse generator, and a master oscillator, the first output of the connection control unit the control input of the shift register, the installation input of which is connected to the first output of the switch unit, the reset input of the control unit, the installation input of the checked digital node, the installation input the single pulse pulse and the installation input of the counter, the counting input of which is connected to the second output of the control unit and the information input of the modulo two adder, the output of which is connected to the informational input of the shift register, the group of outputs of which is connected to the group of inputs of the modulo adder two, the group of outputs of the shift register connected respectively to the first group of information inputs of the first switch, the second group of information inputs of which are connected respectively to the output group of the counter, output the overflow of which is connected to the first input of the first group of information inputs of the second switch, the second input of the first group of information inputs of which is connected to the output of the single pulse generator, the synchronous input of which is connected to the output of the first generator of the second switch, the first, second and the third inputs of the second group of information inputs of which are connected respectively to the outputs of stopping, starting and synchronizing the tested node, first, second, t The second and fourth outputs of the second switch are connected respectively to the first, second, third and fourth information inputs of the control unit, the control of the second switch input is connected to the second output of the switch block, the third output of which is connected to the control input of the single pulse generator, the fourth output of the switch block connected to the control input of the first switch, the group of outputs of which is connected to the group of inputs of the display unit, the delay unit, the third switch and. the coding confidence analysis unit, the auxiliary input of the display unit is connected to the output of the coding confidence analysis unit, the information input of which is connected to the output of the third switch and a quarter 1-1 input of the second group of information inputs of the second switch, the information output of the tested node is connected to the input of the delay unit and the input of the third switch , the group of inputs of which is connected respectively to the outputs of the delay unit, the synchronization output of the tested node is connected to the synchronous input b coding confidence analysis locale, coding reliability analysis block contains two addition elements modulo two, two triggers, two AND-NOT elements, AND element, two NOT elements and three keys, with the synchronous input of the block connected to the first input of the first addition element modulo two, the second input of which is connected to the output of the first key, the power supply bus of the block, the output of the second key and the first input of the second addition element p моду module two, the second input of which is connected to the information input of the block whose output is connected to the output the first element is not connected, the first key input is connected to the second key input, the third key input, the second trigger information input and the block zero potential bus, the third key output is connected to the power supply bus of the block and the single input of the first trigger, the synchronous input of which is connected to the output of the first I element NOT, the first input of which is connected to the output of the first trigger and the input of the

the second element, the first input of the first element is NOT connected to the output of the element I, the first input of which is connected to the output of the second element NOT, the input of which is connected to the output of the second element of the terminal two and the synchronous input of the second trigger, zero input which is connected to the power supply bus of the unit and the zero input of the first trigger, the information input of which is connected to the output of the first addition element modulo two and the first input of the second NAND element, the output of which is connected to the single input of the second trigger, inv rsny output of which is connected to the second input of the AND gate and the second input of second AND-NO

FIG. 1 shows a block diagram of a device for monitoring digital nodes j at .2 — an example of implementing an encoding reliability analysis unit; FIG. 3 is a timing diagram of the operation of the reliability analysis block, coding in the presence of random positive interference, which coincides with the level of the logical unit of the synchronization signal; in figs 4-6 -. time diagram of the operation of the coding confidence analysis unit in the presence of a random positive interference coinciding with the level of the logical zero of the synchronization signal, in the presence of a random negative interference, coinciding with the level of the logical zero of the synchronization signal, and in the presence of a random negative interference coinciding with the level of the logical unit of the synchronization signal, respectively .

The device contains a register 1 sdv ga, an adder 2 modulo two, a control unit 3, an indication unit 4, a switch unit 5, a first switch 6, a counter 7, a second switch 8, a single impulse driver 9, a master oscillator 10, a test node 11, which is not included in the device and is provided only for explanation of the operation of the device, block 12 of the analysis of the reliability of the coding, the third switch 13 and block 14 of the delay.

The encoding reliability analysis block 12 contains triggers 15 and 16, modulo two elements 17 and 18, an AND-NOT element 19, an AND 20 element, an AND-NOT element 21, a NOT element 22 and 23., and keys 24-26,

The essence of the proposed technical solution consists in prompt detection of the effect on the coding result of random failures, interferences or coincidence of the fronts of synchronization pulses with the encodes of the binary sequence, for this purpose synchronous and informational

the inputs of the coding confidence analysis block provide a sequence of clock pulses and a binary sequence to be coded, where the edges of these signals are analyzed with high accuracy (a nanosecond disturbance of several nanoseconds is detected). If interference is detected, the resulting code: code is not used (transcoding is performed), but if transcoding is stable, it detects an error, this means that the error is not a result of random interference, failure, but of a stable coincidence of the sync pulse and the binary coded sequence . In this case, the operator through the third switch introduces a delay and achieves the elimination of an undesirable coincidence. In the following, the encoding result obtained using a certain delay is used.

The encoding confidence analysis unit 12 is designed to detect critical situations in which, for example, the front sync pulse (at the synchronous input of block 12) coincides with the pulse front of the encoded binary sequence (at the information output of the 12, the signal is generated at the output of the encoding confidence analysis section 12 which lights the indicator element on the display unit 4.

The third switch 13 is designed to enable the coding of a binary sequence to the input of the second switch 8 and the information input of the encoding reliability analysis block 12 from any of the outputs of the delay block 14. To do this as a third switch

13 Any typical comm5 -tator can be used for one direction and for several positions according to the number of outputs of a block of 14 delays. Switching by switch 13 is carried out manually.

Delay unit 14 is intended for artificially shifting the encoded binary sequence arriving at the input of delay unit 14 relative to the sequence of sync pulses. In general, block.

14 delays contains h typical bipolar delay elements with different delay times, the inputs of which are interconnected and represent the input of the delay block 14, and the outputs form the n outputs of the delay block 14.

The control unit 3 is designed to receive from the tested node 11 Through the second switch 8) control signals Start, Stop and Synchronization and the formation of the above clock signals of control pulses that coincide in frequency and phase with the Sync signals, but existing only in the time interval which starts at the start signal and ends at the stop signal. The control unit 3 also receives from the tested node 11 a coded binary sequence of signals (via the third switch 13 I, which is outputted to the adder 2 modulo two only in the time interval between the Start and signal signals. In addition, in the control unit 3, all of the above input signals. In accordance with the purpose, the control unit 3 contains four unrelated amplifiers, a trigger, two opposite inputs of which are given the Start and Stop signals, and two AND elements connected with the trigger output. The specified trigger output opens the AND elements when receiving the Start signal and closes when the Stop signal is received. Through one element AND the encoded binary sequence of signals is passed, and through the second synchronization signals. The display unit 4 is designed to decrypt the binary code received ( as a result of conversion of the encoded binary sequence on shift register 1 (or on counter 7) to a seven-segment decimal code convenient for human visual perception. In addition, the display unit 4 displays (using an LED or other indication element): a signal from the output of the encoding reliability analysis unit 12. In accordance with the purpose, the display unit 4 contains a decoder, the input of which receives the binary code from the output of the first switch b, seven-segment LEDs connected by inputs to the output of the above decoder, and a LED displaying the result of the encoding reliability analysis unit 12 Instead of seven-segment LEDs, you can other display elements, such as decatrons, etc., should be used. The shift register 1, the counter and the sum Ti-ir) 2 according to the MODULE two are typical computer units, the size of which does not have a fundamental value and affects only the coding accuracy. The first switch 6 is designed to split the display on the display 4 of the encoding results using the shift register 1 or counter 7. In accordance with the purpose, it is a typical control, through its control switch in one direction and two positions. The second switch 8 is designed to feed the inputs of the control unit 3 for operating signals Start, Stop, Sync and a coded binary sequence (via the inputs of the second group of inputs of the second switch 8) or in the mode of self-control of the device - their simulating signals (via the inputs of the first group of inputs of the second emitter eight). In accordance with the purpose, the second switch 8 is a typical controllable (through its second input) switch in four directions and two positions. It should be noted that the third input of the first group of inputs of the switch 8 inside the switch is connected to the fourth output of the first group of inputs to receive four inputs of the first group of inputs of the switch 8. The single pulse shaper 9 is a typical element that forms at its output a continuous sequence of pulses coming from the master oscillator 10, only one pulse, which coincides with the input to the input of the imaging unit 9 of a single pulse signal, allowing its production from the block 5 switch s. The master oscillator 10 is a typical crystal oscillator generating a continuous sequence of standard pulses, while satisfying the amplitude and steepness requirements of the fronts for both the device itself and the tested node 11. The switch unit 5 contains four independent switches the state of the device and the tested node 11, and the control of the first switch b, the second switch 8 and the single pulse shaper 9. The device operates as follows. The first, second and third inputs of the second group of inputs of the switch 8 are connected respectively to the stop, start and synchronization outputs of the node under test until the completion, for example, of the process of finding the faulty component. The input of the delay unit 14 is connected using the pytiHoro probe or auto probe to the test point of the tested node 11. In block 5 of the switches, settings are sequentially made that provide, through its fourth output, the outputs of the shift register 1 with the outputs of the switch 6 and the connection of the second group of inputs of the switch 8 the outputs of the switch 8 and, respectively, with the first, second, third and fourth information inputs of the control unit 3. In addition, a reset is made from the first output of the block 5 of the driver 9, the counter 1 of the tested node 11, the block 3 of the control and the register 1 of the shift. The third switch 13 is set to the initial position at which its output is connected to its separate input, i.e. without the fate of a block of 14 delays. The reset signal permits the start of the stimulation of the tested node 11 (with the help of an internal, as in the considered example, or an external stimulator). As a result of excitation of the tested node 11, a definite dynamic binary process is unfolded in its selected control point in a coded binary sequence, which from the output of the third comlutator 13 goes to the second input of the encoding reliability analysis unit 12 and to the fourth input of the second group of inputs of the second covertor 8 then through its fourth input further to the fourth information input of the control unit 3. Then a binary sequence is encoded with the generated signal Start and Stop, respectively, entering the second and first inputs of control unit 3 via switch 8 from stop and start outputs, respectively, of node 11, via information output of control unit 3, is output for coding to the input of adder 2, which is bitwise added to the corresponding bits of the reverse circuit connections connecting the outputs of the shift register and the inputs of the adder 2, at the same time, by the clocking clock pulses arriving at the information input of the shift register 1 from the information output of the control unit 3 (to the third information The control unit 3 input clock signals are received from the synchronization output of the tested node II through the third input of the second input group of the second switch 8 and its control output), the contents of the shift register 1 are shifted along each clock sync pulse by one bit from the lot bits to the highest ones, in the lower position of the shift register 1, the result of the summing from the output of the adder 2 to the first input of the shift register 1 is recorded. At the end of the coding interval (between start and stop) the information in the reg register is stopped Istr 1 shift and shifts of information in it. The contents of shift register 1, the result of encoding a binary sequence of hooks, are transmitted through the first switch 6 to block 4 of the display, where it is displayed in the converted compact form. Simultaneously with the encoding process discussed above, E, block 12 of the analysis of the reliability of the encoding, evaluates the reliability of the encoding process itself. Before starting the coding of binary sequences, the keys 24-2b are set to the required positions. The key 26 sets the initial state of block 12. At that, noHcjc Kaic of negative and positive interference pulses is possible (correspondingly, the 24 Jo key is Using the key: 25, the polarity of the synchronization pulses can be specified, entered into the code of the first element of the modulo 2. Another pulse of the binary sequence to be encoded through the element 18 of The PS module is awakened by trigger 15 through its synchronous input. Shortly before this moment, the low level at the output of the first element HE 22 is low and the second element AND 20 does not have a logic state. During the search phase, the low level at the single trigger input 15 Since the output of element 19 is connected to a single trigger trigger input .15, Since the zero level of trigger 15 has an VRLS level, this level must (remain throughout the search phase, otherwise the output of the NB 22 is Vits high level and AND gate 20 outputs a pulse that starts the clock terminal of flip-flop 16. Then, through the element NO23, at the output of the encoding reliability analysis block 12, a signal that will ignite the light emission element in the display unit 4 will be illuminated until the operator closes the key 26 AND-NOT element 21, the output of which is connected to the trigger synchronous switch 16 Prevents information loss after detection of interference. The flip-flop 15 is reset via the first AND-HAY element 19 and prepares the flip-flop to receive the next pulse of the binary sequence being encoded. Thanks to this, there is no time in the circuit when it can skip the noise. However, situations arise in which false alarms occur when interference occurs immediately after the synchronization signal. In order to eliminate these spurious signals, a signal to a single input of the trigger 16 is supplied through the first addition element 17 modulo two, which acts as a buffer stage. Consider in more detail the operation of block 12 using the time diagrams of figure 3-6. In the upper part of FIG. 3 (upper twelve signals), the time diagram of unit 12 operation is shown in the absence of interference, and in its lower part (lower nine signals - in the presence of a random positive interference (filled pulse j, which coincides with the level of the logical unit of the synchronization signal For all cases considered in Figure 4, the same signals were selected as input signals from block 12. To simplify timing diagrams, these signals are not repeated in Figures 4-6, and the interlacing that occurs in the data circuit is shown directly An impulse pulse is shown on the output signal of element 18 in Figures 3-6. As follows from the time diagrams presented, any amplitude disturbance is detected by block 12 if, at the output of element 18, it is represented as a positive impulse superimposed on a logic zero level. data and coinciding with the logical zero level of the sync pulse at the output of the element 17. It is for this purpose that the keys 25 to 24 must be respectively for the case represented in the lower part of FIG. 3, open and closed, for the case represented in ig.4, closed, and closed, for the case shown in Figure 5, is closed and opened, and for the case shown in Figure 6, i.; open and open. After setting the keys 25 and 24 to the position determined by the nature of the disturbance acting in the object, by briefly closing the key 26, the block 12 is reset. At the same time, by the signal drop from 1 to O (signal 266 in Fig. 3), the trigger 16 is set to one, and a signal with a logic zero level (output.e.) is generated at the output of the HE element 23 (at the output of block 12). 1b and 23 in FIG. 3. This unchanged state corresponds to the absence of interference in the control process of the object (the top twelve signals in FIG. 3). The general logic of operation of block 12 is also that for each differential from O to 1 on the synchronous input trigger 15 (out. el.18 / the specified trigger is set to the zero state, and through feedback connecting Trigger trigger Ij through an AND-HE element 19 with its second input, the specified trigger after a short time (commensurate with the trigger trigger time} is again set to unit sorts (output 15 and 19 in Fig. 3). In the absence of clutter at the output of the element I 20, the level of the logical unit remains unchanged, since the input signals of the indicated element (output.e.) 15 and 22 in the upper part (Fig. 3) are always in antiphase. At the same time, at the output of the element 21, the level logical zero, since its inputs remain unchanged level a logic unit (20 -to vyh.el.16 and upper part fig.Z /. The trigger 16 retains its original state (out.el.16). If there is interference (the lower part of FIG. 3), at the moment of forming its leading edge (by paralleling from O to 1), the trigger 15 is set to the zero state via the synchronous input, and it is established to its single input (through the circuit ...). feedback) only at the time of the drop from the next sync pulse. As a result of this, the output of the element 20 produces a negative pulse generated in the interval of coincidence of the unit levels of its input signals (lower part of FIG. 3, output 15, 22 and 20). As a consequence, at the output of element 21 a level of logical unit is formed, the leading edge of which switches the trigger 16 from one state to zero, as a result of which the output of block 12 forms a level of single state, signaling the presence of interference (output 16 and 23 ). Similarly, the block 12 operates under the action of interference of a different nature (Fig.4-6). The use of the proposed device in the mode of counting drops, as well as in the mode of operational self-monitoring is fully considered in. the prototype and here are not critical. The checked node 11, as well as the search for the faulty component in it, is performed using the proposed device by the above-described process of coding the dynamics of the tested node 11 at its characteristic control points and comparing the actual keywords obtained with the corresponding reference ones. With the help of the proposed device, also get etshonnye keywords. At the same time, having received the next keyword, they check if the indicator of the coding reliability analysis block lights up. If he doesn't

turned on, the key word is received at the next control point of the tested node 11 (transfer the probe to another control point and perform the next coding}. But the specified indicator zgazhegs, the obtained key word is unreliable, and the transcoding is performed using one of the delays of block 14 of delays entered using the third switch 13, this registers the keyword and the position of the third switch 13, which corresponds to the non-ignition of the indicator of the analysis block 12 Coding accuracy, etc. for all control points of the tested node 11.

When registering the technical state of the tested node (i.e., when obtaining reference keywords I) using the P: supplied device, the time costs are reduced by about a factor of two due to the absence of the need for re-coding to avoid accidental failures and interference. The fact that there are no accidental failures and noise in the proposed device is indicated.

The economic effect of the application of the proposed device is reflected both in the control and in the search for faulty components.

In addition, a significant advantage of the device's UniteMoro device, unlike the prototype, is that it can be determined (the indicator of the block for analyzing the reliability of the J stable sync of the fronts of the sync pulse and the ig-shulvs of the coded binary sequence will also light up, which also increases the reliability of the reference keywords digital nodes and search in them for faulty components.

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Claims (1)

DEVICE FOR MONITORING DIGITAL NODES, comprising a shift register, modulo two adder, a control unit, an indication unit, a switch unit, a counter, two switches, a single pulse shaper and a master oscillator, the first output of the control unit being connected to the control input of the shift register, the installation input of which is connected to the first output of the switch block, the reset input of the control unit, the installation input of the digital node under test, the installation input of the single-imager, ·: pulse and m counter input, the count input of which is connected to the second output of the control unit and the data input of the adder MO. two barrel, the output of which is connected to the information input of the shift register, the group of outputs of which is connected to the group of inputs of the adder modulo two, the group of outputs of the shift register is connected respectively to the first group of information inputs of the first switch, the second group of information inputs of which is connected respectively to the group of outputs of the counter, the overflow output of which is connected to the first input of the first group of information inputs of the second switch, the second input of the first group of information inputs of which inen with the output of the single pulse generator, the sync input of which is connected to the output of the master oscillator, with the third input of the first group of information inputs of the second switch, the first, second and third inputs of the second group of information inputs of which are connected respectively to the outputs of the stop, start and synchronization of the tested node, the first, second, third and fourth outputs of the second switch are connected respectively to the first, second, third and fourth information inputs of the control unit, the control input to The second switch is connected to the second output of the switch block, the third output of which is connected to the control input of the shaper alone. night pulses, the fourth output of the switch block is connected to the control input of the first switch, the group of outputs of which is connected to the group of inputs of the display side, about τSU „„ 1059576 characterized in that, in order to increase the reliability of control>, a delay block, a third switch and a coding reliability analysis unit, the additional input of the indication unit being connected to the output of the coding reliability analysis unit, the information input of which is connected to the output of the third switch and the fourth input of the second groups of information inputs of the second switch, the information output of the checked node is connected to the input of the delay block and the input of the third switch, the group of inputs of which is connected respectively to the outputs of the delay block, the synchronization output of the checked node is connected to the sync input of the coding confidence analysis block, the coding confidence analysis block contains two addition elements modulo two, two flip-flops, two AND-NOT elements, AND element, two NOT elements and three keys, wherein the sync block input is connected to the first input the first element is ^ modulo two additions, the second input of which is connected to the output of the first key, the power supply bus of the unit, the output of the second key and the first input of the second addition element modulo two, the second input of which is connected to the information input of the unit, the output of which is connected to the output of the first element NOT, the input of the first key is connected to the input of the second key, the input of the third key, the information input of the second trigger and the bus of the zero potential of the block, the output of the third key is connected to the power bus of the block and a single input m ^ of the first trigger, the sync input of which is connected to the output of the first element AND, the first input of which is connected to the output of the first trigger and the input of the first element NOT, the second input of the first element AND is NOT connected to the output of the element AND, the first input of which is connected to the output of the second element NOT, the input of which is connected to the output of the second addition element Modulo two and the sync input of the second trigger, the zero input of which is connected to the power bus. block and the zero input of the first trigger, the information input of which is connected to the output of the first addition element modulo two and the first input of the second AND-NOT element, the output of which is connected to the unit input of the second trigger, the inverse output of which is connected to the second input of the AND element and to the second input second element AND NOT.