SU1054873A1 - Multi-frequency discriminator - Google Patents

Abstract

A MULTI-FREQUENCY DISCRIMINATOR containing a series-connected pulse driver, a signal converter, an AND element, a first counter, a memory register, and a first expander, with the second AND element, is the input of a reference signal, different. m and and G by the fact that, in order to increase the sensitivity to small frequency mismatches in the high-frequency pulse packets, the serially connected counter was entered into it, the second decoder and the delay element, the second counter input connected to the second output of the signal converter, the output of the second decoder connected to the synchronization input of the memory register, and the output of the delay element is connected to the installation inputs of both counters. (L

Description

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W The invention relates to radio engineering and can be used in systems of frequency auto-tuning. Known digital (Frequency discriminator using the pulse-counting method when adjusting the frequency and determining the value of the difference between the input frequencies and the sign of this difference Cl. The known frequency discriminator is characterized by low frequency tuning accuracy of the pulse signal under study with short pulses with a great repetition frequency in addition, it is narrowband. The closest in technical essence is a myo-frequency discriminator containing a series-connected pulse shaper, the signal converter, the element I, the first counter, the memory register, and the first deitfrator, the second input of the element and the input of the reference signal, as well as included at the output of the integrator discriminator, made on two analog C2 J switches. but wideband, however, it does not have a sufficiently high sensitivity to small frequency mismatches in the high-frequency pulse packets, due to the quantization error introduced into the frequency tuning accuracy, equal to K — the number of pulses iksirovannyh counter; t is the time equal to the duration of the pulse envelope. signal frequency. The purpose of the invention is to increase the sensitivity to small frequency mismatches in the high-frequency bursts. The goal is achieved. We can say that the multi-frequency discriminator / containing gs are consequently connected to a pulse former, a signal converter, an element I, the first counter, a memory register and the first action, and this is the second input of the element I is an input of the reference signal. connected second counter, second dis11 | a1 and an element of delay, the second counter input is connected to the second signal converter, the second decoder output is connected to the memory register synchronization input, and the delay element output is connected to the installation inputs of both counters. The drawing shows the proposed multi-frequency discriminator . The multi-frequency discriminator contains a driver of 1 pulses, a converter of 2 signals, an element I 3, the first counter 4, a register 5. memory, the first decoder b, the second counter 7, the second decoder 8 and the delay element 9. The proposed multi-frequency discriminator operates as follows. The inputs of the device are two frequency signals: reference and signal. Converter .2 signals produces a strobe-pulse, the duration of which is equal to the duration of the envelope of the pulses of the signal frequency necessary to control the element And 3, and also produces pulses rewriting. The repetition rate of these pulses is divided N times and the information rewrite is formed by the second counter 7- and in the TopbiM decoder 8 From the output of the delay element 9 you take off; a reset signal that returns both counters 4 and 7 to their initial state. The strobe pulse and the reference frequency signal arrive at the element AND 3 G output of the element And 3 packs of reference frequency pulses arrive at the first counter 4, which counts the pulses contained in the W bursts. At the end, the rewrite pulse opens the memory register 5 and overwrites the information to register 5. Then the counters 4 and 7 of the pulses of reset are set to the initial state, and the decoder b converts the signal of the binary system to a logic level 1 with frequency detuning f 4f relative to the reference frequency. The positive effect is due to an increase in the number of measured reference frequency pulses, filling video pulses G with an increase in the number N, the sensitivity to small frequency detuning increases. If in the prototype the output signal varies from 0 to 2.5 V with Fg.pt detuning on il, 25 MHz, t, e, the slope of the amplitude-frequency characteristic (frequency response is 1 V / MHz, then in the proposed device I N 25 and ± 50 kHz detuning sigial: output varies from 0 to D.O2 to 4.5V, those steepness is 259 / MHz. The multi-frequency drive is equal to -or o6jRt4BlkeT by broadband:. The main unit of the former ./ 1, a block diagram of the transformation 1054873 "

The bodies of 2 signals and the limit of memory, which is decoded into the register, 5, are in excess of logical elements. From the previous tact of work,

changing the repetition frequency of the packs. Thus, the proposed multi-high-frequency pulses per point-frequency discriminator works in

The characteristics of the device are narrow and the frequency range

the carrier can be influenced by a continuous sensitivity (RUN) If the signal on the LCH / is lost, the discriminator will give out in high frequency

signal corresponding to the information pulses.

Claims (1)

MULTI-FREQUENCY DISCRIMINATOR comprising serially connected pulse shaper, signal converter, element And, the first counter, the memory register and the first decoder, while the second element in the iodine is the input of the reference signal, I distinguish. In order to increase the sensitivity to small frequency mismatches in the packets of high-frequency pulses, a second counter, a second decoder and a delay element are introduced in series with the input of the second counter connected to the second output of the signal converter,. the output of the second decoder is connected to the synchronization input of the memory register, and the output of the delay element is connected to the installation inputs of both counters. SU L 054873