SU777809A1 - Coding converter - Google Patents

Description

(54) CODE DISPLAY UNIT

The invention relates to radio engineering and can be applied in communication systems with code-pulse modulation, as well as in automation systems.

A device comprising an olor generator, a clock generator, a valve, a rectangular pulse generator, frequency dividers, step voltage geyrators, a phase-pulse modulator, circuits I 1 is known.

It is also known a device containing a clock generator, a counter, a pulse-phase modulator, and a memory cell of bit 2.

A disadvantage of the known devices is a decrease in the signal-to-noise ratio with a decrease in signal amplitude.

The aim of the invention is to increase the signal-to-sound ratio for signals with low amplitude.

This is achieved by the fact that, in a coding converter containing a clock generator, the output of which is connected to the counter input of the counter, the outputs of which are connected to the first inputs of the first elements AND, the second element AND whose inputs are connected to the outputs of the counter, is a phase-pulse modulator whose input is connected with the input width, and the output with the second inputs of the first elements AND, the outputs of which are connected to the inputs of the memory cell, the element OR is inserted, the inputs of which are connected to the outputs of the elements AND, the third inputs of the first elements 5 And connected to the installation input of the counter, the sampling input of the phase-pulse modulator and the output of the element OR NOT.

FIG. 1 shows the flow chart

10 of the coding converter, in FIG. 2 - time diagrams that show his work.

The device contains a clock generator 1, the output of which is connected to the counting

5 by the input of the counter; 2 the outputs of which are connected to the first inputs of the first elements I 3, the second element I 4, whose inputs are connected to the outputs of the counter 2, the phase-pulse modulator 5, whose input

20 is connected to the input bus and the output is connected to the BTOipbiMH inputs of the first And 3 elements, the outputs of which are connected to the inputs of the memory cell 6, the OR element is NOT 7,

25 inputs of which are connected to the outputs of the elements And 3, and the third inputs of the first elements And 3 are connected to the installation input of the counter 2, the sampling input of the phase-pulse Modulator 5 and the output of the element IL, AND - NOT.

thirty

The device works as follows.

From the output of the clock generator 1 to the counting input of the counter 2 receives the pulses of the reference frequency f (see Fig. 2, b). When all the bits of the counter 2 are filled with units, the four-input element I 4 is triggered, the generated pulse, passing through the input element OR-HE 7 (see Fig. 2, e), acts on the disk | reversing input of the phase-pulse modulator 5 and sets phase pulse modulator to zero state. The same impulse resets the triggers of counter 2, wrapped them, and imposes a ban on third inputs for the duration of its operation, 3 three-input elements AND 3. Thus, three-input elements AND 3, blocked during the installation of the phase-pulse modulator 5, to the zero state and interfere with the passage of signals of intermediate states of the trigger 2 of the trigger in the memory cell of bit 6.

Thus, when there is no signal at the input of the phase-pulse modulator 5, the sampling pulses of setting to the zero state of the phase-pulse modulator 5 appear with the frequency:

± ft,

P

the division ratio of counter 2 of the encoder; pulse frequency of the clock generator 1.

In this case, the cell 6 of the memory of the discharge through the three-input elements And 3 is filled with "zeros.

When a signal is received at the input of the phase-pulse modulator 5 signal (see Fig. 2, a), immediately after the start of the zeroing cycle of the triggers of the counter 2 (see Fig. 2, c), the accumulation of the number of pulses proportional to the amplitude by the counter 5 begins. of the input signal until the moment of triggering the phase-pulse modulator 5, at which the output pulse of resolution (see Fig. 2, d) is generated at its output (see Fig. 2, d) for the operation of the three-input elements And, and the information accumulated by the counter 2 (see Fig. 2, e) 6 memory times, row (om. Fig. 2, g).

In parallel with the recording of information, the memory cell 6 of the bit of any or several logical units from the outputs of the three input elements AND 3, arriving at the input of the two input element OR - NOT 7, is inverted into a logical "zero" (see Fig. 2, e), - which resets the counter 2, zeroes its triggers, prohibits the third inputs of the three-input elements AND 5 and sets the sampling input to the zero state. Phase pulse modulus 5. After that, the information conversion cycles are repeated.

Thus, the frequency p2 of the following sampling pulses at (the conversion of the input signal will be inversely proportional to the amplitude of the input signal:

P.,

where "2 is the division factor of counter 2, depending on the amplitude of the signal, and lies within L.

Claims (2)

1. USSR author's certificate number 320044, cl. H 03 K 13/02, 197i6. 2. Kethermoul K.V. Principles of Pulse-Zhod Modulation.- M., 1974, p. 305. shhhhhh & w ppppp well ZZDI in nnninn g ILDJl I o