SU1042062A1 - Data receiving device - Google Patents

Abstract

A DEVICE FOR RECEIVING INFORMATION containing a chronizer, the first output of which is connected to the first input of the first register, the first and second outputs of which are connected respectively to the combined first inputs of the first and second And elements, and the combined first inputs of the third and fourth And elements, the third output - to the first input of the fifth element And, the outputs of the first and third elements And are connected respectively with the first and second vogog: dami counter i whose third input is connected to the second output of the chroniser, the third output x The sensor is connected to the first inputs of the adder and the second register, the second input of the first register and the fourth input of the counter, the output of which is connected to the first input of the memory unit, the output of which is connected to the first input-. The first and second keys, the fourth and fifth outputs of the chronizer are connected respectively to the second input of the memory block and the second input of the second register, the first output of which is connected to the third input of the memory block, the fourth input of which is connected to the input of the device, the second output The second register is connected to the second inputs of the first, third, fourth and fifth elements And through the first element is NOT to the second input of the second element And, the third output of the second register is connected to the third inputs of the second, third and fifth elements in And through the second element NOT - with the third input of the fourth element And, the outputs of the second, fourth and fifth elements And connected to the inputs of the first element Or, the output of which is connected directly to the second input of the first key and through the third element NOT to the second input of the second key, the output of which is connected to the second input of the adder, the output of which is connected to the output of the device, characterized in that, in order to improve the speed of the device device, the decoder, memory cells, shift register, third are entered into it. The key, second, third, fourth 0 and fifth elements OR, the fourth output of the first register is connected to the first input of the decoder, the first outputs of which through the second element OR are connected to the first input of the shift register, the input of the synchronizer and the first input of the third element OR, the output of which connected to the third input of the second register, the second outputs of the decoder are connected through the fourth element OR to the second input of the third element OR and the first input of the first

Description

the third memory of the decoder via the fifth OR element is connected to the third input of the third OR element and the first input of the second memory cell, the output of the first key is connected to the second input of the shift register, the third input of which is connected to the third output of the clock, memory outputs The ti and the shift register output are connected respectively to the second and third inputs of the adder, the output of which is connected to the combined second inputs of the memory cells and the first input of the third key, the output and the second input of which are connected respectively but with the memory input and the sixth output of the chronizer, the seventh, eighth, ninth and tenth outputs of the chronizer, respectively, with the second input

the decoder, the third input of the first register, the third input of the first memory cell and the third input of the second

memory cells.

The invention relates to telemetry and can be used to recover processes from compressed data at the receiving end of the telemetry system.

A known device recovered. nor the initial information on compressed data, when the essential coordinates are the coefficients V obtained as a result of decomposing the controlled process in ophogonal basis functions, containing the generator of orthogonal functions, analog multipliers, resistances and summing operational amplifier TI J.

A disadvantage of this device is the low accuracy of the reproduction of the monitored parameter due to the fact that the system of Walsh functions obtained from the generator, even at high orders of the normalized frequency, the sequence must retain orthogonality.

The closest technical solution to the present invention is a device for receiving information comprising a control unit, a memory unit, a counter, AND elements, registers, NOT elements, an OR element, keys, an adder, the first counter input is connected to the first output of the control unit, the second output of which connected to the first input of the memory block, the second input of which is connected to the input of the device; the output of the memory block is connected via keys to the inputs of the analog adder; the third output of the control unit is connected to

the control input of the analog adder, to the second counter input and to the first register inputs, the second inputs of which are connected to the fourth and fifth outputs of the control unit, the counter outputs are connected to the third memory input of the fourth input of which is connected to the first outputs of the second register second whose output through the first element is NOT connected to the first input of the first element AND and directly to the first inputs of the remaining AND elements, the second output of the second register through the second element is NOT connected to the second input of the second And the second element, and directly - SVTOR inputs of the first, third and fourth elements, and the first output,

the second and third elements AND are connected to the inputs of the OR element, the output of which is directly through the third element is NOT connected to the control inputs of the keys, the first output of the first register is connected to the second input of the first element AND, the second output of the first register is connected to the third inputs of the second and fourth elements And, the third output of the first register is connected to

the third input of the third element MC2j

A disadvantage of the known device is the low speed, so as to restore the original

Information requires a large number of operations such as addition - subtraction. The purpose of the invention is to increase speed, i.e. reducing the number of operations such as addition — subtraction during the synthesis of the initial information — is achieved by the fact that p is a device for receiving information containing a chronizer, the first output of which is connected to the first input of the first register, the first and second outputs of which are connected respectively to the combined first inputs of the first and second elements and the combined first inputs of the third and fourth elements And, the third output - with the first input of the fifth element And, the outputs of the first and third elements And do with the first and the second respectively The third inputs of the counter, the third input of which is connected to the second output of the chronizer, the third output of the internalizer is connected to the first inputs of the adder and the second register, the second input of the first register and the fourth input of the counter, the output of which is connected to the first input of the memory unit whose output is connected to the first The inputs of the first and second keys, the fourth and fifth outputs of xp & nizator are connected respectively to the second input of the memory unit and the second input of the second register, the first output of which is connected to the third input of the fourth memory unit The third input of which is connected to the input of the device, the second output of the second register is connected to the second inputs of the first, third, fourth and fifth elements AND, and through the first element NOT to the second input of the second element AND, the third output of the second register is connected to the third inputs of the second, the third and fifth elements And through the second element NOT with the third input of the fourth element And, the outputs of the second, fourth and fifth elements And connected to the inputs of the first element OR, the output of which is connected directly to the second input of the first key and through TR Tille NOT element - to a second input of the second switch, the output of which is connected to the second input of the adder; the output of which is connected to the output of the device, a descrambler, memory sticks, shift register, third key, second, third, fourth and fifth OR elements are entered, the fourth output of the first register is connected to the first input of the decoder, the first outputs of which are connected through the second OR element the first input of the shift register, the input of the clock and the first input of the third element, OR, the output of which is connected to the third input of the second register, the second outputs of the decoder are connected through the fourth element OR to the second input of the third element OR and The first input of the first memory cell, the third outputs of the decoder through the fifth OR element are connected to the third input of the third OR element and the first input of the second memory cell, the output of the first key is connected to the second input of the shift register, the third input of which is connected to the third output of the chroniser, outputs the memory cells and the output of the shift register are connected respectively to the second and third inputs of the adder, the output of which is connected to the combined second memory inputs and the first input of the third key, the output and the second input of which are connected to Responsibly with the fifth input of the memory unit and the sixth output of the chroniser, the seventh, eighth, ninth and tenth outputs of the chronizer are connected respectively to the second input of the decoder, the third input of the first register, the third input of the first memory cell. . The drawing shows a block diagram of the proposed device. The device contains a chronizer 1, memory block 2, counter 3v elements 4 and 5, first register 6, second register 7 elements 8 and 9, elements AND 10, 11 and 12, element OR 13, element NOT 1, first key 15, second a key 16, an adder 17, a decoder 18, elements OR 19, 20, 21, and 22, a first memory cell 23, a second memory cell 2, a shift register 25, a third key 26, the following arguments are carried out, allowing in comparison with the prototype, reduce the number of operations of the type of addition — subtraction about the restoration of the initial information, when the essential coordinates are the coefficients Xaa a. The operation of the prototype is based on the following relationship: (-) b. J ,, (1) Р „(х) where, 6, is the binary value of the argument; .and generalized coefficients: Haar factors. Then, for each m, it is easy to single out the digits e, .t-l-D of which only the simplest logical operations are needed. By the values of m and j, it is possible to form the address of a cell containing b, jj. If the next digit is in binary. The number of x (i.e., C) is zero, then q, j is the accumulated amount, and if the next digit is one, then b, y is calculated, then. (Starting, we obtain, Pr „(x). Note that tr is 1 2 2P, where n is the number of recoverable function counts or the same as the number of Haar coefficients. In one cycle, there is one addition and several logical operations. Therefore, the total number of elementary operations spent on the calculation of P, (x) at one point is 1od-, and to restore the original function at eight of its points, niog-n or 81092 2A operations of addition type - subtraction are required. This number of operations can be significantly reduced. .1) and (2), we will write down a row for eight points: Ро (0.000) and fb + b Р, (0.00 1) P2 (0.010) p (0.011) ac-b:: -b |; -b 2, P4 (0.100Ba; -cKe (P (0.101) a .PO) a -b -bgfb p (0.11l) For expression 3, we write the intermediate sums in the form Vs. Then the expression (3) can be rewritten as, (x) b2, -u3 1P5 (x) -c, + b, -, P, (x) Vb2t-4l P ( x) s, P2U)) C2-22-E4 P (x) C, (. 5) The value of the sum at the odd-numbered point differs from the value of the sum calculated at the previous even point by twice the value of the coefficient with the index of the maximum value Thus, the expression (5) can be finally written down as P4 (X) 02., 3 Pl () Po (x) -2b3, P5 (x) P4 (x) -2H3 P2 (P (X) P (xL2B34). D1x) (x) -2b. The number of operations of the type of subtraction in expression (6) is twelve, and two more operations should be added for expression (4) and the total number of operations will be fourteen. The operation mode of the device is set by the clock 1. From the outputs of clock 1 to the first 6 and second 7 registers, the binary value, 000 and, 000 is entered. Elements k and 5 are locked at y. the left values of the binary code are not received from the register of the counter 3 counter. At the first input of the counter 3, from the output of the clock 1, one is fed and to the inputs of the memory block 2 the value of the address 001 and 000 is received, from which the coefficient a is read. Elements 10, 11, and 12 are blocked from the outputs of register 7, in which the value 000 is located. Negative signals from the outputs of these elements t are fed to the inputs of the element OR 13. A low signal from the output of this element, inverted by the element NOT AND, is fed to the control input key 16 and allows the passage of the coefficient a to the direct input of the adder 17. Key 15 does not work, since its control input will be a negative signal from the output of the element OR 13. The adder 17 must be of accumulating type. In the second register 7, the unit is added and its contents become equal to 001. Elements 4 and 5 remain blocked and the contents of the counter, 3 is 001. Thus, the addresses 001 and 001 are fed to the inputs of memory 2 and the output of memory 2 is read coefficient b. The key 16 remains open, and the readable coefficient C is fed to the direct input of the adder 17. The control input from the output of the clock 1 is fed to the right input of the memory cell 23, thereby allowing the intermediate sum value to be written to it (c a + b j c The output of the adder 17. Then the chronizer 1 sets the first 6 and second 7 registers to the initial zero state, as well as the adder 17. From the output of the chroniser 1, the binary register 100 is entered in the first register 6, and the value 000 is entered in the second register 7. the memory again reads the coefficient a l and arrives at n A row of the adder 17 is inserted. A unit is added to the second register 7 and the coefficient b is read from memory block 2. Element I 10 is triggered, since its inputs will have the enable signals from the first bit of the second register 7 from the first output of the first register 6 (high the bit is on the left) and the output of the element is NOT 8. A positive signal from the output of the element OR 13 opens the key 15, and the coefficient C is fed through the shift register 25 to the inverse input of the adder 17. There is no control signal from decoder 18 from the output of chroniser 1 and the OR element 19 remains blocked, thereby allowing the passage of information through change register 25, t, e without a left-shift by one bit. The control signal from the output of chroniser 1 goes to the first the input of the second cell 2 of the memory and allows the entry of the intermediate sum value into it (-C from the output of the adder 17. The signal from the output of the chronization. Tutor 1 sets the registers 6 and 7 and the adder 17 to the initial state. In the first register 6 and the second register 7 is entered, 00 and "0.000. A control signal is received at the control input of the encoder 18 from the clock output. 1. A positive signal is present at the zero output of the decoder 18, because the value of the first register 6 is 0.000. The positive signal from the output for the OR 20 reads the value of the interim sum from the first cell 23 of the memory, which goes to the direct input of the adder 17. From the output of the OR 22 element, the positive signal writes the unit to the second register 7. Timer 1 removes the control signal from the output, thereby blocking the operation of the decoder 18, and in The second register adds one and its value becomes equal to 010. From block 2 of memory, the value of coefficient b is read, since counter 3 contains code 001, and register 2 reads code 010. It is easy to see that the key 16 is triggered and the value goes to the direct input of the adder 17. The time clock 1 adds a unit to the second register 7 and from the memory block 2 the coefficient L oo is read, which also goes to the direct input of the adder 17. Thus, in the adder 17 there is the value of the restored function at the zero point (, Control signal L 1 hronizatora output opens switch 26, thereby allowing entry value F (x) in the memory unit 2. A unit is added to the first register 6. and the control signal from the output of the clock 1 starts the operation of the decoder 18, the G of the decoder 18, the signal appears at its first output and one goes to the second register 7 and its value does not change, i.e. remains equal to three (011). From block 2 of memory, the coefficient bg is read as the element 12 is triggered, the positive signal from the output of the element OR 13 opens the key 15 and the value of the coefficient b goes to register 25, at the control input of which there is an enabling signal from the element OR 19. In register 25, the number is shifted to the left and one bit, which is equivalent to multiplying it by two, and the inverse input of the adder 17 receives a double value of the coefficient b In the adder 17, thus, the error J. The value of the function at the point P (x). The control signal from the output of the clock 1 opens the key 26, allowing the writing of the value P, (x) to the memory block 2. The signal from the output of the element OR 19 is fed to the input of the chroniser 1, signaling the end of the work cycle. The control signal from the tenth output of the clock 1 sets the registers 6 and 7 and the adder 17 to the initial state. Then the binary value (010) is entered into the first register 6, and the value and processing process is completely repeated as described in the second register 7. At the end of the full cycle of operation in memory block 2, the values of the restored function are found. eight points according to the expression (6).

Thus, the proposed device makes it possible to reduce the number of operations such as addition-subtraction compared to the prototype, which increases labor productivity and makes the computation process more cost-effective.

Claims (1)

A device for receiving information, comprising a chronizer, the first output of which is connected to the first input of the first register, the first and second outputs of which are connected respectively to the combined first inputs of the first and second elements AND and the combined first inputs of the third and fourth elements AND, the third output to the first input of the fifth element And, the outputs of the first and third elements And are connected respectively to the first and second inputs? the counter, the third input of which is connected to the second output of the chronizer, the third output of the chronizer is connected to the first inputs of the adder and the second register, the second input of the first register and the fourth input of the counter, the output of which is connected to the first input of the memory unit, the output of which is connected to the first inputs of the first and second keys, the fourth and fifth outputs of the soya-chronizer. respectively, with the second input of the memory unit and the second input of the second register, the first output of which is connected to the third input of the memory unit, the fourth input of which is connected to the input of the device, the second output of the second register is connected to the second inputs of the first, third, fourth and fifth elements • and through the first element NOT with the second input of the second element AND, the third output of the second register is connected to the third inputs of the second, third and fifth elements And and through the second element NOT with the third input of the fourth element And, the outputs the second, fourth and fifth AND elements are connected to the inputs of the first OR element, the output of which is connected directly to the second input of the first key and through the third element is NOT to the second input of the second key, the output of which is connected to the second input of the adder, the output of which is connected to the output of the device, characterized in that, in order to improve the performance of the device, a decoder, memory cells, shift register, and three are introduced into it. the second key, the second, third, fourth and fifth OR elements, the fourth output of the first register is connected to the first input of the decoder, the first outputs of which are connected through the second OR element to the first input of the shift register, the input of the chronizer and the first input of the third OR element, the output of which is connected to the third input of the second register, the second outputs of the decoder are connected through the fourth OR element to the second input of the third OR element and the first input of the first memory cell, the third outputs of the decoder through the fifth OR element are connected to the third input of the third OR element and the first input of the second memory cell, the output of the first key is connected to the second input of the shift register, the third input of which is connected to the third output of the chronizer, the outputs of the memory cells and the output of the shift register are connected respectively to the second and third inputs of the adder, the output of which is connected with the combined second inputs of the memory cells and the first input of the third key, the output and second input of which are connected respectively to the fifth input of the memory unit and the sixth output of the chronizer, the seventh, eighth, ninth minutes and tenth hronizatora outputs connected respectively to the second input of decoder *, the third input of the first register, the third input of the first memory meshes ki and the third input of the second memory cell.