SU1039019A1 - Analog-digital filter - Google Patents

Description

The invention relates to computing and can be used, in particular, in digital filtering and smoothing systems, when filtering broadband analog signals in real time, such as radar and communications. An analog-digital filter containing a random access memory, address generator, accumulating adders and control unit C1.

However, the filter is characterized by a large filtering error, due to the large time interval when the next value of the filtered signal is output.

Closest to the proposed technical entity is a filter that contains a pseudo-random signal sensor, a comparator, a reversible counter, an operative memory device and a control unit 2.

The disadvantage of such a filter is limited filtering accuracy due to the non-ideal frequency response of the filter, i.e. percolation of higher harmonics of the signal due to the rectangular shape of the impulse response of the filter ..

The purpose of the invention is to improve the accuracy of filtration.

The goal is achieved in that an analog-digital filter containing a pseudo-random signal counter, a comparator whose output is connected with a reversible counter, the output of which is connected to the information input of the memory block whose output is the first information output of the filter, the synchronization block that outputs not with control inputs of a pseudo-random signal sensor, comparator, reversible counter and control input of the address / output generator of which is connected to the address input of the block n An analog adder, a multiplexer and three accumulating adders are inserted, the output of the memory unit is connected to the inputs of the first and second accumulating adders, the outputs of which are connected respectively to the first and second multiplexer inputs, the output of which is connected to the input of the third accumulating adder whose output is The second information output of the filter, the third information output of which is the output of the first accumulating adder, the output of the pseudo-random signal sensor is connected to the first the input of the analog adder, the output of which is connected to the input of the comparator, the second input of the analog adder

is the information input of the filter, and the control inputs of the three accumulating adders and the multiplexer are connected to the output of the synchronization unit.

5 The drawing shows the functional diagram of the analog-digital filter.

The analog-digital filter contains sensor 1 pseudo-random signals, analog adder 2, compressor 3, reversible counter 4 and memory block 5 (random access memory), first and second accumulating adders 6 and 7, multi-

W plexor 8, the third accumulating rummator 9, block 10 synchronization, the driver 11 addresses.

The filter works as follows. A filtering input signal is supplied to the filter input. In the input signal range, a pseudorandom signal sensor 1 generates a uniformly distributed two-pole pseudo-random signal at each clock cycle, which in the analog adder 2 is added to the filtered signal. Comparator 3 determines the polarity of the obtained sum of signals in direct dependence on the polarity of the resulting signal to the result of the reversible counter 4 is added or subtracted one. After the passage of N clock pulses in a reversible counter 4, a number proportional to the integral of the input signal is accumulated over the time interval At. The memory unit 5, the address generator 11, accumulating adders b, 7, 9 and multiplexer 8 realizes a stepwise-triangular shaped impulse characteristic, namely, after zeroing the block 5 and accumulating adders b, 7, 9, address 1 is generated by address generator 11. The resulting number at the output of block 5 is subtracted from the result of accumulating adder 7, and instead of it in block 5 is recorded the number from the reversible counter 4 corresponding to its input signal integral at the first time interval L1. At the same time, this number is added to the result of accumulating adder 6. After that, address builder 11 generates address K. The number that appears at the output of block 5 is subtracted from the result of accumulating adder b and added to the result of accumulating in adder 7. adder 9 adds the number from accumulated adder b, and subtracts the number from accumulator adder 7. Immediately after writing the number from reversible counter 4 to block 5, reversing counter 4 is zeroed and repeated with

the cycle of determining the integral of the input signal over the next time interval 4 t and its processing cycle. When processing the i-th interval of the input signal, the address generator 11 sequentially generates 1 + 1 and-K + i spins, where i is 0.1, ..., 2K-1. During T 2Kd1, in block 5, 2K numbers proportional to the integrals of the input signal at each time interval 4t will be written, and in the accumulating adders b, 9 there will be numbers proportional to the value of the filtered signal. Moreover, the number in the accumulator adder b is proportional to the filtered value of the signal with a square-wave impulse response, and the number LO in the accumulating adder 9 is the triangular impulse response of the filter. Cycle processing. Secondary 2K + 1-st and subsequent integrals of the input signal remains

the former, and the address driver 11 repeats the address generation cycles, from 1 to 2K. With an interval of L1, the values of the filtered signal appear at the outputs of the accumulating adders B and 9, which appear at the output of the accumulating adder 6 after the K-th processing cycle, and at the output of the accumulating adder 9 after the 2K-CSO processing cycle.

Thus, in the proposed device, an increase in the filtration accuracy makes it possible to provide a more accurate result of further digital processing of the useful signal. Therefore, the main advantage of the device is the simultaneous preservation of high speed and accuracy of filtering while extracting 20 useful signals from noise in real time, for example, in radar and communications.

Claims (1)

ANALOG-DIGITAL FILTER containing a pseudo-random signal sensor, a comparator, the output of which is connected to the input of the reversible counter, the output of which is connected to the information input of the memory unit, the output of which is the first in. formation filter output, a synchronization unit, the output of which is connected to the control inputs of the pseudo-random signal sensor, a comparator, a reverse counter and the control input of the address generator, the output of which is connected to the address input of the memory unit, characterized in that, in order to increase the accuracy of the filtering, an analog adder, a multiplexer, and three accumulating adders are introduced, the output of the memory block being connected to the inputs of the first and second accumulating adders, the outputs of which are connected respectively with the first and second inputs of the multiplexer, the output of which is connected to the input of the third accumulating adder, the output of which is the second information output of the filter, the third information output of which is the output of the first accumulating adder, the output of the pseudo-random signal sensor is connected to the first input of the analog adder, the output of the second is connected to the input comparator, the second input of the analog adder is the information input of the filter, and the control inputs of the three accumulating adders and multiplex Pa connected to the output of the synchronization unit. , SU „„ 1039019>