RU1798630C - Frequency analyzer - Google Patents

Abstract

The invention relates to devices for determining the current value of the frequency of a narrowband signal - and can be used in automatic control systems and specialized computing devices. The purpose of the invention is to increase performance and reduce requirements for implementation length. The frequency analyzer comprises a trigger 1, a switch 2, a clock generator 3. RAM element 4, the first 5, second 6 and an additional 27 registers, the first 10 and second 11 elements of RAM

Description

w

k

V |

Yu

00 Os

with

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adder 3, comparison element 9, counter 12, as well as the first 14 and second 15 additional counter, the first 16 and second 17 multipliers - accumulators, multipliers 19-23, subtractors 24 and 25 and dividers 7 and 26, as well as analog-digital transducer 28 and amplifier 29. Harmonic extraction The invention relates to devices for automatically detecting the current value of a signal frequency in the presence of a high level of random noise.

The aim of the invention is to increase speed and reduce the requirements for length of implementation.

Structural diagram of the proposed frequency analyzer is shown in the drawing. / -. .-....

The frequency analyzer comprises a trigger 1, a switch 2, a clock generator 3, a RAM element 4, the first 5 and second 6 registers, a divider 7, an adder 8, a comparison element 9, the first 10 and the second 11 read-only memory elements and a counter 12 , the information outputs of which are connected to the address inputs of the first element of read-only memory 10, and the first input of trigger 1 is the input 13 for starting the frequency analyzer, which also contains the first 14 and second 15 additional counters, the first 16 and second 17 matrix accumulator multipliers torahs six multipliers 18-23, two combination subtractors 24 and 25, an additional divider 26, an additional register 27 and. analog-to-digital converter 28, the input of which is connected through an input amplifier 29 to the input 30 of the frequency analyzer, the output of the analog-to-digital converter 28 is connected to the information inputs of the RAM element 4, the address inputs of which are connected by the information outputs of the first additional counter 14, the counting input of which is connected with the output of switch 2, the first information input of which is the input 31 of the reference frequency and is connected to the trigger input of the analog-to-digital converter 28, the output of trigger 1 is inen with the control input of switch 2, the write input of the RETAIL / READ mode of the RAM element A and the reset input of the counter 12, the direct dynamic counter input of which is connected to the inverse dynamic clock inputs of the first 16 and second 17 matrix accumulator multipliers, the best approximating the input implementation, written to element 4 with subsequent reading with an increased frequency, provides a quick determination of the instantaneous value of the frequency at a high level of additive noise and noise at. 1 ill.

tors, the second information input of the switch 2 and the output of the clock generator 3, the transfer output of the counter 12 is connected to the inverse dynamic

the reset inputs of the first 16 and second 17 matrix battery multipliers, the inverse dynamic counting input of the second additional counter 15, and the transfer input are larger than the comparison element

9, the reset input of the second additional counter 15 is connected to the input 13 of the start of the frequency analyzer, which is connected to the reset input of the first additional counter 14 and the additional register 27,

the direct dynamic clock input of which is connected to the output of MORE comparison element 9, which is connected to the clock input of the first register 5, the information outputs of which are connected

with information inputs of the second register 6, the clock input of which is connected to the transfer output of the second additional counter 15. information outputs of which are connected to address inputs

the second memory element 11, the information inputs of the first register 5 and an additional group of inputs of the first memory element 10, the first and second group of outputs of which are connected to the first

groups of information inputs of the first 16 and second 17 matrix battery multipliers, the second groups of information inputs of which are connected to the information outputs of the RAM element 4, the first group of outputs 32 of the Second element of the read-only memory 11 is connected to the first group of information inputs of the first multiplier 18, the second group of outputs 33 of the second memory element 11 is connected to the first group of information inputs of the second multiplier 19, the third group of information outputs 34 of the second memory element memory 11 is connected to the first

groups of information inputs of the third 20 and fourth 21 multipliers, the fourth group of information outputs 35 of the second element of read-only memory 11 is connected to

the inputs of the job of the divider of the additional divider 26 and the divider 7, the information outputs of which are connected to the first groups of information inputs of the fifth 22 and sixth 23 multipliers, respectively, the output of the first matrix multiplier switch 16 is connected to the second groups of information inputs of the first 18, fourth 21 and n of that of 22 multipliers, the output of which of the matrix multiplier-accumulator 17 is connected to the second groups of information inputs of the second 1.9. of the third 20 and sixth 23 multipliers, the inputs of the reducible and deductible first combination calculator 24 are connected to the outputs of the first 18 and third 20 multipliers, the inputs of the reducible and subtracted second combination subtractor 25 are connected to the outputs of the second 19 and fourth 21 multipliers, the outputs of the first 24 and second 25 combination subtractors are connected to the inputs of the divisible respectively additional divider 16 and divider 7. and the outputs of the fifth 22 and sixth 23 multipliers are connected to the information inputs odes of the adder 8, the outputs of which are connected to the first group of inputs of the element of comparison 9 and the information inputs of the additional register 27, the outputs of which are connected to the second group of inputs of the element of comparison 9.

The frequency analyzer operates as follows.

The signal, which is an additive mixture of a narrow-band random component, the frequency that needs to be determined and the random components of noise and interference, is input 30. This signal is then fed through a matching amplifier 29 to the input of the analog-to-digital converter 28. The converter is started according to the start pulses supplied to input 31 and having a frequency fkBO. The beginning of the operation cycle of the device is associated with the supply of a start signal to input 13. By this signal, the counters 14 and 15, as well as the register 27 are reset to zero. In addition, trigger 1 switches to the state when its output signal switches the switch 2 to the state of transmission of pulses from input 31 to input of counter 14, and element 4 goes into recording mode. Thus, the analog-to-digital converter 28 is started on the leading edge of the pulse at input .31, and the counter 14 is switched on the falling edge, ensuring that the next count in element 4 is recorded at consecutive addresses, starting from zero. After filling element 4 with the transfer signal from counter 14, trigger 1 switches to the opposite state and its output signal removes the reset signal from counter 13, and to the input of counter 14 through

switch 2 receives pulses from the generator 3. These same pulses provide the switching counter 12. which provides a sample from the memory element 10 pairs of values of sin a) to T |, cos and) to P, where I is the number

samples determined by the counter code 12, and the frequency (o is determined by the code on the second group of inputs of this memory element, i.e., the code from the output of counter 15. Thus, in the multiplier x-accumulators (for example, implemented on TO chips C 1008. Service C 1009, Service C 1010. KR 1518VZh1, KR 1518VZhZ) amounts are formed

bi, k

 i

I 0

y (tf) cos w to ti

25

b2.k 2 y (ti)

sin a) to ti,

I 0

where k 1 ...., M and is determined by the output code of counter 16.

For each k, codes are selected from memory element 11. .

11 k Z,

a nk 2, cos tOkti

I 0

35

1.2, k 2,

COS O) to t | Sin WK t | ,

 0

 h

322k 2 /

40i 0

A K a 11. k a 22. k - a2i2. n

Multipliers 18-23.0, subtractors 24, 25, dividers 7 and 26, and adder 8 provide the formation of the code adder output

$ k 3fcb 1, k + bk02k

fifty

v b i. k a 21. k - b 2.k a 12k b in, X ---------- ЈЈ

l, P2. k341.k - b 1.k a 12kb 2k + ---------- 2fc ----------

The obtained values of Sk are compared by element 9 with previously recorded in register 27 (at the beginning of the cycle there is a zero value in it) and if Sk is greater than it is recorded in register 27, and the corresponding value of k in register 5.

In this way, a definition corresponding to a maximum of Sk is provided, and such k is selected as a code corresponding to a frequency o that approximates the current input signal most accurately. This result is recorded in register b until the end of the next work cycle. At the output of register 6, which is the output of the device, the code characterizes the current value of the frequency (signal period).

Since the pulse frequency of the 3f generator can be chosen significantly higher than the frequency fKB. it is possible to determine the current value of the frequency of the narrow-band component with high speed, and the determination algorithm implemented by the proposed device provides high reliability of the estimate.

The effect of using the proposed solution is to increase the accuracy of frequency measurements, expanding the functionality and applications.

Claims (1)

SUMMARY OF THE INVENTION A frequency analyzer containing a trigger, a switch, a clock, an element of RAM, the first and second registers, a divider, an adder, an element of comparison, the first and second elements of read-only memory and a counter whose information outputs are connected to the address inputs of the first element memory, and the first input of the trigger is the start input of the frequency analyzer, with the exception that, in order to improve performance and reduce the requirements for implementation length, it is equipped with the first and second add-ons counter, the first and second matrix multiplier-accumulator, six multipliers, two combination subtractors, an additional divider, an additional register and an analog-to-digital converter, the input of which is connected through the input amplifier to the input of the frequency analyzer, the output is analog the digital converter is connected to the information inputs of the RAM element, the address inputs of which are connected to the information outputs of the first additional counter, the counting input of which is connected with the output of the switch, the first information input of which is the input of the reference frequency and connected to the input of the start of the analog-to-digital converter, the trigger output is connected to the control input of the switch, the input of the task of the write-read mode of the RAM element, and the counter reset input, direct dynamic the counting input of which is connected to the inverse dynamic clock inputs of the first and second matrix battery multipliers, the second information input of the switch, and the output of the clock generator c, the counter transfer output is connected to the inverse dynamic reset inputs of the first and second matrix battery multipliers, the inverse dynamic counter input of the second additional counter and the transfer input. More comparison element, the reset input of the second additional counter is connected to the start input of the frequency analyzer, which is connected with the reset input of the first additional counter and additional register, the direct dynamic clock input of which is connected to the output More than the comparison element, which is connected to the clock input of the first register, the information outputs of which are connected to the information inputs of the second register, the clock input of which is connected to the transfer output of the second 5 additional counter, information outputs of which are connected to the address inputs of the second memory element, information inputs of the first register and an additional group of inputs of the first element 0 memory, the first and second group of outputs of which are connected to the first groups of information inputs of the first and second matrix battery multipliers, the second groups of information inputs of which 5 are connected to the information outputs of the random access memory element, the first group of outputs of the second read-only memory element is connected to the first group of information inputs of the first multiplier, the second 0 the group of outputs of the second memory element is connected to the first group of information inputs of the second multiplier, the third group of information outputs of the second memory element is connected 5 with the first groups of information inputs of the third and fourth multipliers, the fourth group of information outputs of the second memory element is connected to the inputs of the divider of the additional divider and divider, the information outputs of which are connected to the first groups of information inputs of the fifth and sixth multipliers, respectively, the output of the first matrix multiplier - the accumulator of 5 torus is connected to the second groups of information inputs of the first, fourth and fifth multipliers, the output of the second matrix multiply the l-accumulator of the torus is connected to the second groups of information inputs of the second, third and sixth multipliers, the inputs of the reduced and subtracted first combination subtractor connected to the outputs of the first and third multipliers, the inputs of the reduced and subtracted second combination subtractor are connected to the outputs of the second and fourth multipliers, the outputs of the first and second combination subtracters are connected to the inputs of the divided 0 respectively, an additional divider and divider, and the outputs of the fifth and sixth multipliers are connected to the information inputs of the adder, the outputs of which are connected to the first group of inputs of the comparison element and the information inputs of the additional register, the outputs of which are connected to the second group of inputs of the comparison element.