SU1035643A1 - Analog memory - Google Patents

Description

The invention relates to the field of computing and can be used in information-measuring systems for storing and reproducing information. A device is known which comprises a first linearly rising voltage generator, the input of which is connected to the first input of the device, a second linearly increasing voltage generator and a comparison circuit, the input of which is connected to one of the driver's inputs, the output of which is the output of the device. The device also contains a third generator of linearly increasing voltage, the input of which is connected to the second input of the device and to another input of the former, as well. the output to the first output of the comparison circuit, the second input of which is connected to the output of the subtraction circuit, the inputs of which are connected to the outputs of the generators, and the input of the second linearly increasing voltage is connected to the third input of the Cl Cl device. the presence of three generators. linearly increasing voltage and subtraction circuits, and limited functionality, as a result of which the device performs only one operation — memorizing the duration of a rectangular input pulse. The closest to the proposed technical value is an analog storage device containing the first i-generator of linearly increasing voltage, the input of which is connected to the first input of the device and to one of the trigger inputs, and the output to the first input of the comparison circuit, the output of which is connected one of the driver inputs, the output of which is the output of the device, and the second ramp generator, the input of which is connected to the trigger output. In addition, the output of the linearly rising voltage generator is connected to the second input of the circuit, and the second input of the device to another trigger input and to another input of the driver 2. The known device provides for storing and one-time reproduction of information containing s in the input pulse duration Tak the operation is relatively rare in practice. Much more often, one has to encounter the need to remember and repeatedly reproduce information containing the input pulse duration (form a pulse train with a duration equal to the input pulse duration), or memorize, repeatedly reproduce and simultaneously convert the specified information (form a pulse packet with a duration varying from pulse to pulse according to a certain law). The known device cannot be used for; performance of these operations, which limits its scope. The aim of the invention is to increase the reliability of the device. The goal is achieved by the fact that the analog. The storage device containing the first linearly rising voltage generator, the input of which is connected to the first input of the trigger and is the first input of the device, the output of the first linear voltage generator is connected to the first input of the comparison unit, the output of which is connected to the first input of the former. pulses, memory element, moreover: | output of the pulse former, -, the device output, the input of the second generator of line-rising voltage is connected to the first output of the trigger, the counter, the decoder and the element I are entered, the first input of which is the second input of the device The output of the element I is connected to the second input of the pulse former, the output of which is connected to the first input of the memory element, the second input of the element I is connected to the second output of the trigger, the second input of which is connected to the output of the decoder, the input of the decoder oedinen with the counter output, whose input is connected to the output of comparison unit, a second generator output voltage increases linearly connected to the second input of the memory element whose output is connected to the second input of the comparing unit. . FIG. 1 image of the functional diagram of the proposed device; in fig. 2, 3, and 4 are timing diagrams explaining the principle of its operation. The device (Fig. I; contains linearly increasing voltage generators 1 and 2, trigger 3, comparison unit 4, pulse shaper 5, element bb, memory element 7, counter 8 and decoder 9. The device operates as follows. In the memory mode and repeated reproduction of the information contained in the pulse duration applied to Device In1 of the device (Fig. 2a), with the leading edge of this pulse trigger 3 is set to position 1 at input S. The potential at the zero output of the trigger 2, abruptly betraying It reaches a level 31 - .rush (Fig. 2, &), and this potential difference triggers generator 2, the voltage U at the output of which begins to increase linearly (Fig. 2, d). the unit output of flip-flop 3, associated with controlling the equalizing input of the element 6, takes the value of a logical unit (Fig. 2, c), thereby giving permission for the passage of clock pulses from the input device 2 through the element b 5, made in the form of a trigger. The falling edge of the input pulse (Fig. 2, a) starts the generator 1, the voltage 1/2 at the output of which begins to increase linearly (Fig. 2, d). The slope of this voltage in this mode is chosen to be equal to the slope of the voltage, and since the duration of the playback cycle here displays the duration of the input pulse. The beginning of the first cycle of reproduction of information contained in the duration of the input pulse corresponds to the arrival of the first clock pulse (Fig. 2, d; for closeness, all clock pulses are numbered; the clock pulse shown by the dotted line does not pass to shaper 5, since element b. at this moment in time, the shaper 5 is still closed, which, in doing so, is set to position 1. A high potential, corresponding to the potential of a logical unit of FIG. 2, e), from the shaper 5 output goes to the control unit Id g of memory element 7. and translates it (up to this point in time, the specified element operates in addition mode) to the storage mode of the instantaneous value Ux, (the second digit in the subscript index ce corresponds to the number of the clock pulse set by this playback cycle I output voltage and generator 2 (Fig. 2, d). The voltage sweep U continues in this case. For example, they are compared with each other; at the moment of equality (Fig. 2, d), comparison block 4 is triggered, the pulse from whose output (.fig . 2, g} returns the shaper 5 to its original position (Fig. 2, e The resolving potential is removed from the control input of the memory element 7, and it again goes into the adding mode (Fig. 2, -d dotted lcnc). During the first reproduction cycle the pulse is formed with a duration equal to the duration of the input pulse, the pulse is removed from the output of the imaging unit 5 and is fed to the output of the device, i.e., the information contained in the duration of the input pulse is displayed at the desired time, and ends. On the other hand, cycle 43. The second playback cycle starts with the arrival of the second clock pulse (Fig. 2, e), proceeds analogously with the engine above and ends with the operation of the 4-block comparison (at the moment of equalization of the voltages 0.2 and returning the imager 5 to the initial position O and translating the memory element 7 is in the addition mode. Each next i-th cycle (i 1, 2, .., n proceeds in the same sequence, with the output pulses of the comparator unit 4 (Fig. 2, w, the number of which, obviously, is equal to the number of reproduction cycles, is counted by counter 8. With a certain code in counter 8 (corresponding to a specified number of reproduction cycles), the decoder 9 set up to this code works, the pulse from which output returns trigger 3 to its original position About the input E (Fig. 2, b, v / and reset both generators 1 and 2 to zero on the installation inputs (not shown A jr - "-% CXKJU (ЯЬ l V iIXCL CA -" s J. Counter 8 and the decoder 9 constructively can be made in the form of an integrated microcircuit, for example K176IE8. Period T clock pulses are selected from the condition T. where Txx is the input pulse duration, applied to device Bx.1, the transition process time in memory element 7 when it is switched to the add-on mode. In the memory and single-time reproduction mode, the information contained in the input the pulse, the device operates as described above, the decoder 9 being tuned to the code generated in the counter 8 when it counts a single pulse, and the first time the comparison unit 4 is triggered returns trigger 3 to the end On th position and resets both generators 1 and 2 in their mounting inputs. in the mode of “playback, repeated reproduction and transformation of information contained in the duration of the pulse supplied to Bx.1. device, the leading edge of this pulse trigger 3, as before, is set to position 1 at input S (fig.3, bg c and fig.4, b, c), start-up generator 2, the voltage U at the output of which starts to increase ( Fig. 3 g; Fig. 4, d). The falling edge of the input pulse (Fig. 3, a; Fig. 4, a) starts the generator 1, the voltage Uj at the output of which varies according to a similar law

(fig. 3; fig. 4, d). Voltage slope (./2 in this mode is chosen more (fig, 3 or less (fig.4 voltage 0), while the device works in the same way as in the previous mode {with the arrival of the i-ro clock pulse, the instantaneous value is remembered The voltage U, which is then compared with the voltage Uy g at the moment of equality, triggers 4 comparison, etc.), but the reproduction is accompanied by its transformation — the duration of the output pulses, which in the previous mode was equal to the duration of the input pulse, here is changing according to a certain law: monotonously decreases (Fig. 3, e) or increases (Fig. 4, s) from cycle to cycle. A change in the steepness of one linearly increasing voltage (in this case, a voltage of 1/2 relative to another can be achieved The known method is a change in the time constant of the integrating RC circuit. The choice of the number of reproduction cycles is achieved, as before, by setting the decoder 9 to the corresponding code value generated by the counter 8 by counting the output pulses of the 4 comparison unit.

The formation of a burst of pulses with a duration equal to the duration of the input pulse (or with a duration varying according to a definite, from pulse to pulse /

no different from the modes discussed above. The sequence and essence of the operation in the same cases is the same. The adjustment of the number of pulses in a pack is carried out

decoder 9.

Compared with the base sample, the proposed device has wider possibilities, since in addition to storing and reproducing information contained in the duration of the input pulse, it provides memorization and repeated reproduction of the information contained in the duration of the input pulse (formation of a pulse packet with a duration equal to the duration of the input pulse). pulse; the number of pulses in a packet is regulated /, as well as the memorization, repeated reproduction and conversion of information, Holding in the duration of the input pulse (the formation of a burst of pulses with a duration varying according to a certain law from pulse to pulse; the number of pulses

0 in a bundle is adjustable).

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Claims (1)

ANALOGUE MEMORY 'DEVICE containing a first ramp voltage generator whose input is connected to the first input of the trigger and is the first input of the device, the output of the first ramp voltage generator is connected to the first input of the comparison unit, the output of which is connected to the first input of the pulse shaper. a memory element, wherein the output of the pulse shaper is the output of the device, the input of the second ramp generator is connected to the first output of the trigger, characterized in that, in order to increase the reliability of the device, a counter, a decoder, a torus and an element And, the first input of which are introduced is the second input of the device, the output of the And element is connected to the second input of the pulse former, the output of which is connected to the first input of the memory element, the second input of the And element is connected to the second output of the trigger, the second input of which w is connected to the output of the decoder, the input of the decoder is connected to the output of the counter, the input of which is connected to the output of the comparison unit, the output of the second ramp generator is connected to the second input of the memory element, the output of which is connected to the second input of the comparison unit. SU .1035643>