SU1305722A1 - Calculating device - Google Patents

Abstract

The invention relates to electrical computing devices and can be used in analog computers. The purpose of the shadow image is to increase the speed and expand the scope of application due to the possibility of working with single-time pulse signals. The computing device contains the source 1 of the reference voltage, the first, second and third keys 2, Zib, integ (L u

Description

Rotor 4, sample and hold unit. 5, storage capacitor 7, null-organ 8, first, second, third and fourth triggers 9, 22, 23 and 30, element OR 10, first, second, third, fourth, fifth, sixth, seventh and eighth elements AND 12, 13, 24, 25, 26, 27, 28 and 29, pulse generator 14, first, second and third counters 16, 17 and 32, first and second subtractive counters 18 and 19, first and second decoders 20 and 21, block prohibit the passage of the first pulse 31.

one

The invention relates to electrical computing devices and can be used in analog computers.

The purpose of the invention is to increase speed and expand the scope of use due to the possibility of working with single-time pulse signals.

FIG. 1 shows a functional diagram of a computing device.

at

in fig. 2 time signal charts.

The device contains the source 1 of the reference voltage, the first and second keys 2 and 3, the integrator 4, the block 5 of sampling and storage, the third key 6, the storage capacitor 7, the zero-body 8, the first trigger 9, the element OR 10, the bus 11 zero potential, the first and second elements And 12 and 13, the generator 14 pulses, the input 15 installation mode, the first and second counters 16 and 17, the first and second subtractive counters 18 and 19, the first and second decoders 20 and 21, the second and third triggers 22 and 23, third, fourth, fifth, sixth, seventh and eighth elements And 24-29, fourth trigger 30, bl About 31 prohibition of cooling of the first pulse, the third counter 32, the input 33 of setting the number of operation cycles, the first and second information inputs 34. and 35, output 36, the first and second elements 37 and 38.

The computing device operates as follows.

The computational device operates cyclically and is very fast, since it provides a transition to the next cycle cycle (or the next cycle) immediately after the voltage on the plates of the storage capacitor 7 reaches zero and the zero-body 8 is activated The minimum permissible time period following the pulse signals is selected, and has a wide range of applications. 2 Il.

ten

f5

The functional elements 12-32 form a trimming unit, highlighted by a dotted line in FIG. 1. Time pulsed signals with duration Tj and T 5 arrive at the first and second inputs 34 and 35 Second, third and fourth triggers 22, 23 and 30, first, second and third counters 16, 17 and 32, first and second subtractive Counters 18 and 19 and block 31 of the transmission of the first pulse at the beginning of each measurement are set to their original (zero) position.

Block 31 of prohibiting the passage of the first pulse can be performed, for example, in the form of a trigger and an element, whose inputs are combined.

In the mode of periodically repeating time of the pulse signals on the set of operation mode settings, the low level potential corresponds to the logic level O, which blocks the first, second, third meter, and the last elements And 12, 13, 24 and 25. In the third counter 32 s the installation input of the number of operation cycles 33 is entered the number (in the return code) equal to the specified number of operation cycles of the device, while the overflow output of the third counter 32 is the potential of a high I o level corresponding to the logic level 1 (Fig. 2f), 1) 1st permits the passage of cher the first and second elements 2I-OR 37, and 38 time - 35 pulse signals (Fig. 2a, b) m .Vre- pulse signal with a duration T ,, (hereinafter - the signal T) proho01

thirty

Dit through the open second element 2I- OR 38 to the control input of the third key 6, set it (at time T) to the closed position. In this case, the initial voltage from the output 36 of the device is fed to the storage capacitor 7 and charges it to the value

defined as follows t.

V, and „(1st),

(one)

where t.

- the time constant of the charge circuit of the storage capacitor 7 with the third key 6 closed;

Ots some initial voltage. . : The falling edge of the signal T, passing also through the element OR 10 (Fig. 2y), is set to position 1, the first trigger 9, the potential 1 from the direct output of which (Fig. 2b) sets to the closed position the second key 3, storage capacitor 7 begins to discharge through integrator 4, the output voltage to

then changed by law

t.

and, g- - and, (1 de С

TO

TO

TO

with „e M - - Cn

(2)

thirty

 P

P

the capacitance of the storage capacitor 7 and the capacitor of the integrator 4, respectively,

transfer coefficient 35 of sampling and storage unit 5.

At the moment of time when the tension on the plates of the storage capacitor 7 reaches zero, the null-organ 8 triggers, im40

corner

The pulses from the output of the null organ 8 (Fig. 2d) also arrive at the input of block 31 of the forbidden passage of the first pulse, which prohibits the passage of the very first of them and passes the rest — the second, third, fourth, etc. (Fig. 2h). The second impulse from the output of the null organ 8 (the pulse from the output of which, corresponding to the end of the first cycle. The first cycle of the device operation (Fig. 2d), the upper trigger (block 31), respectively, returns the first flip-flop 9 to the origin-,

the O position (Fig. 2c), with It 411

potential

from the control input

As it was noted, the end of the second cycle of the first cycle passes through the eighth element I 29 (Fig. 2i, which is opened by potential 1 from the inverse output of the fourth trigger 30 (Fig. 2n)) and is counted by a third counter 32, the contents of which increase HP. and also enters the control input of the block

the second key 3 is removed, and it opens, disconnecting the storage capacitor 7 from the integrator 4.

As it was noted, the end of the second cycle of the first cycle, the passage through the eighth element I 29 (Fig. 2 which is opened by potential 1 from the reverse output of the fourth trigger 30 (Fig. 2n)) and counted by the third counter 32, the contents of which increase HP . unit as well as goes to the control input of the block

The time pulse signal with duration T ((fig. 2b) - further signal T, - passes through the open first element 2I-OR 37 to control-5 - 5 samples and storage, transferring its input to the first key 2, is set to sampling and storing it instantly into a closed position. The voltage of the source 1 of the reference voltage is applied to the memorized value of the output voltage of the integrator 4, which is the result of the first cycle of operation of the device

22

capacitor value.

four

and

charges him up

defined by the expression t,

EC (1 C-,

),

(3)

five

O

five

0

Where

- time constant of the charge circuit of the storage capacitor 7 with the first key 2 closed;

EJ, is the voltage of the voltage source 1. The trailing edge of the signal T (passing through the element OR 10 (fig.2u) is set to position 1, the first trigger 9, the potential 1 from the direct output of which (fig.2c) the second switch 3, the storage capacitor 7, is set in the closed position. It starts to discharge through the integrator 4, the output voltage of which varies according to the law

eleven

 and. H

Eo (1) -.

 Sp

(four) .

At the moment of time when the voltage on the plates of the storage capacitor 7 reaches zero, the zero-body 8, the pulse output from the output (Fig. 2d), corresponding to the end of the second cycle of the first cycle of the device, triggers, returns the first trigger 9 to the initial position O ( Fig. 2c), wherein the potential 1 is removed from the control input of the second key 3, and it opens.

The pulses from the output of the null organ 8 (Fig. 2d) also arrive at the input of the block 31 of the forbidden passage of the first pulse, which prohibits the passage of the very first of them and passes the rest — the second, third, fourth, etc. (Fig. 2h). The second impulse from the output of the zero-organ 8 (per vkkkor (and block 31), respectively,

    vkgkor (and block 31), respectively - ",

50

As it was noted, the end of the second cycle of the first cycle passes through the eighth element I 29 (Fig.2i), which is opened by potential 1 from the inverse output of the fourth trigger 30 (Fig 2l) and. counted by a third counter 32, the content of which is increased by HP. unit, as well as enters the control input block

 - 5 sampling and storage, putting it into sampling and memory mode instantly

5 sampling and storage, putting it into sampling and memory mode instantly

the actual value of the output voltage of the integrator 4, which is the result of the first cycle of operation of the device

s and: K, 5dS, E,. (.- T ,,,

G-1 1

and „1 - CK-SG e) 1 (5)

.

and

The falling edge of the specified (second) output zero-body pulse 8, in addition, the fourth trigger 30

In the one-time mode, a pulse is set at the counting input to

Position 1, while the potential of 1 jg signals supplied to the first

It is removed from its inverse output (the eighth element of AND 29 is blocked) and appears at the direct output (Fig. 2m), opening the seventh element of AND 28. The next (third) output pulse will pass through this element in the first beat of the second cycle of the device the zero-organ 8 (Fig. 2k), which, with the falling edge, returns the fourth trigger 30 to the O position, at. this potential 1 from the forward trigger of the fourth trigger 30 will be .sn t (the seventh element of And 29 is blocked) and inverse output (Fig. 2l) 5 opening the eighth element And 29, which is at the end of the second t KTA this cycle will be held next (fourth) output pulse zero organic 8 (FIG. 2i), etc. in the way

and the second information inputs for and 35 devices (Fig, 2a, b), at the input 15 of the installation of the operating mode of potential 1, preparing the first, swarm, third and fourth elements And 12, 13, 24 and 25 (Fig. 2g). The second and first elements are And 13 and 12, open at time T and. T, respectively, pass the clock pulses of the generator 14 to the counting inputs of the second and first counters 17 and 16 (Fig. 2d, e), which form codes proportional to Tg and T, respectively, by counting these impulses. The rest of the operations of the first operation cycle of the device for the two initial times of the pulse signals (Fig. 2a, b) are similar to those considered in. first mode: at time t

20

capacitor 7, and then (after installing the third key 3 in the closed position of the potential 1

set to closed position

the eighth element And 29 selects even -jg the third key 6, the charge starts the recorded output pulses of the zero-organ 8, each of which fixes the end of the corresponding cycle of the device (Fig. 2i).

The second and subsequent cycles of operation of the device are carried out similarly.

After n cycles of operation of the device, counting the next impulse from the output of the eighth element And 29, the third count40

chick 32 will overflow, the potential at its overflow entrance will abruptly change the 5 ° level of logical O (Fig. 2f) and block the first and second elements 2I-OR 37 and 38. The measurement and computational process ends here, and the output 36 of the device is similar ( 5) fixes the naps of the output of the first trigger 9) its time, until the voltage reaches zero, and so on. After the first cycle of operation, the device proceeds to the formation of its own pulse time signals of the same duration (T to ensure the measurement and computational process in subsequent cycles of operation.

The second impulse of the zero-organ 8 (Fig. 2d), or the first from the output of block 31 (Fig. 2c), appears at the output of the eighth element I 29 (Fig. 2i) and

performance

. ".,. F §; - - Ф

,, - .. (, -, -%) -,

. „.,. K .. (,. / ..,

when satisfied

Ii

  "G sp

- (1 - e

)

leads to the following mind

out .ll-S ivyhSp) E l -: - upillillL / SL.

(7)

 about 1 - expr-Tg / T)

Expression (7) is a device conversion equation.

In the one-time mode, the pulse signals fed to the first

signals sent to the first

the second information inputs for and 35 devices (figs, 2a, b), at the input 15 of the installation of the operating mode of potency 1, preparing the first, second, third and fourth elements And 12, 13, 24 and 25 (fig. 2g). The second and first elements are And 13 and 12, open at time T and. T, respectively, pass the clock pulses of the generator 14 to the counting inputs of the second and first counters 17 and 16 (Fig. 2d, e), which form codes proportional to Tg and T, respectively, by counting these impulses. The remaining operations of the first cycle of operation of the device for the two initial times of the pulse signals (Fig. 2a, b) are similar to those considered in. first mode: at time t

capacitor 7, and then (after installing the third key 3 in the closed position of the potential 1

-jg the third key 6, starts charging

the third key 6, the charge begins to charge

from the output of the first trigger 9) its bit until the voltage reaches zero, and so on. After the first cycle of operation, the device transfers to the formation of its own pulse time signals of the same duration (T to ensure the measurement and computational process in subsequent cycles of operation.

The second impulse of the zero-organ 8 (Fig. 2d), or the first from the output of block 31 (Fig. 2c), appears at the output of the eighth element I 29 (Fig. 2i) and

fixing the end of the first cycle of operation of the device, then passes through the fourth element I 25 and, entering the control input of the second subtractive counter 19, permits the transfer. rewrite the contents of the second one

counter 17, and also sets the third trigger 23 to position 1, at which potential 1 from its direct output (fig. 2n) opens the sixth element And 27, and the clock pulses of the generator 14 through this element start 7. 13

They are sent to the counting input of the second subtractive counter 19 (Fig. 2o) describing its contents. At the time. Corresponding to zeroing of the second subtractive counter 19, the second decoder 21, the pulse from whose output (Fig. 2n), rotates the third trigger 23 to the initial position O. Thus, the pulse signal is generated at the output of the specified trigger (FIG. 2n), as if imitating the second of the periodically repeating signals of the previous mode, which through the second element 2I-OR 38 and the OR element enters the first trigger 9 (Fig. 2u and the control input of the third key 6, sets it to the closed position and behind giving a sequence

A computing device containing a serially connected voltage source, first and second keys, an integrator, a sampling and storage unit, the output of which is the output of the computing device, a storage capacitor, the first plate of which is connected to the output of the first key, the output of the sampling and storage unit connected to the information input of the third key, the output of which is connected to the first lining of the storage capacitor, the second lining of which is connected to the zero potential bus, element OR, trans The left and second inputs of which are connected respectively to a control unit, characterized in that, in order to increase the speed of the -; - link and expand the change area, a zero-body, first, second, third, and quarter-triggers are introduced into it, the pulse generator, the first , second, third, fourth, fifth, sixth, seventh, eighth elements And, first, second and third counts, characteristic for the first cycle of 20% 1 input of the first and third key of the second cycle of the device. The third impulse of the zero-organ 8 (Fig. 2d) or the second from the output of block 31 (Fig. Зз), appearing at the output of the seventh element And 28 (Fig. 2k) and 25 fixing the end of the first clock cycle of the second 1st operation of the device, passes further through the third element I 24 and, arriving at the control input of the first subtractive counter 18, times 30, the first and second subtractive counts solve the rewriting of the contents of the first counter 16 into it, and also sets the second trigger 22 to position 1, where the potential 1 from its direct output (Fig. 2p) opens the 35th fifth element of And 26, and the cycle The new generator pulses 14 through this element begin to flow to the counting input of the first subtractive counter 18 (Fig. 3c), describing its contents. 40

The first and second decoders, the first and second elements 2I-1-SHI, block the passage of the first pulse, the output of the first key is connected to the first input of the zero-body, the second input of which is connected to the zero potential bus, the output of the zero-body is connected with a single input of the first trigger, to the installation input of About which the output of the element OR is connected, the direct output of the first trigger is connected to the control input of the second key, the first input of the first element AND is the first information input. The time point corresponding to zero The first subtractive counter 18 is activated, the first decoder 20 is triggered, the pulse from whose output (FIG. 2t) returns the second trigger 22 to the source device and is connected to the first position O. Thus, at the input of the first element 2I-OR, the output The specified trigger is formed by a time-pulse signal (Fig. 2p), as if imitating the second of the perio-signals, which is connected to the first input. the OR element, the first input of the second element AND is the second informationally repetitive signal from the 50 50 input device and is connected to the previous re; kim, which through the first element 2I-1SH37 37 and the element OR 10 enters the first trigger 9 (Fig. 2y) and the control input of the first key 2, setting it to the closed55 position of the first and second elements by the inputs of the first, and setting the sequence. operations, characteristic second cycle - the second cycle of the device.

with the first input of the second element 2I- OR, the output of which is connected to the second input of the element OR, the output of the pulse generator is connected to the second

And with the first inputs of the fifth and sixth elements And, the third inputs of the first and second elements And are connected according to the invention

A computing device containing a serially connected voltage source, first and second keys, an integrator, a sampling and storage unit, the output of which is the output of the computing device, a storage capacitor, the first plate of which is connected to the output of the first key, the output of the sampling and storage unit connected to the information input of the third key, the output of which is connected to the first lining of the storage capacitor, the second lining of which is connected to the zero potential bus, element OR, trans The left and second inputs of which are connected respectively to a control unit, characterized in that, in order to increase the speed of the -; - link and expand the change area, a zero-body, first, second, third, and quarter-triggers are introduced into it, the pulse generator, the first The second, third, fourth, fifth, sixth, seventh, eighth elements are AND, the first, second, and third counts are% 1 inputs of the first and third keys, and the first and second subtracters count

% 1 by the inputs of the first and third keys, the first and second subtracting counts

The first and second decoders, the first and second elements 2I-1-SHI, block the passage of the first pulse, the output of the first key is connected to the first input of the zero-body, the second input of which is connected to the zero potential bus, the output of the zero-body is connected with a single input of the first trigger, to the installation input of About which the output of the element OR is connected, the direct output of the first trigger is connected to the control input of the second key, the first input of the first element I is the first information input of the device and connected to the first input the first element 2I-OR exit

the house of the device and connected to the first input of the first element 2I-OR, the output

which is connected to the first input. element OR, the first input of the second element AND is the second information input of the device and is connected by the inputs of the first and second elements

with the first input of the second element 2I- OR, the output of which is connected to the second input of the element OR, the output of the pulse generator is connected to the second

the input of the device and is connected by the inputs of the first and second elements

And with the first inputs of the fifth and sixth elements AND, the third inputs of the first and second elements AND are connected respectively to the first inputs of the third and fourth elements AND, and they are the input of setting the operating mode of the device, the outputs of the third and fourth elements AND are connected to the single inputs the second and third flip-flops respectively, the direct outputs of which are connected respectively to the second inputs of the fifth and sixth elements AND, the outputs of the first and second elements AND are connected to the counting inputs of the first and second, respectively counters whose outputs are connected to the information inputs of the bits of the first and second subtractive counters, respectively, whose outputs are connected to the inputs of the first and second decoders, respectively, the output of the first decoder is connected to the installation input of the second trigger, the output of the second decoder is connected to the installation input of the third the trigger, the outputs of the fifth and sixth elements And are connected to the counting inputs of the first and second subtractive counters, respectively, the start inputs of which are connected to the outputs, respectively t

five

0

five

of the third and fourth elements And, the second inputs of which are connected to the outputs of the seventh and eighth elements And, the first inputs of which are connected to the counting input of the fourth trigger, the direct and inverse outputs of which are connected to the second inputs of the seventh and eighth elements And, the eighth And connected to the counting input of the third counter and to the control input of the sampling and storage unit, the second and fourth inputs of the first and second elements 2I-OR are connected to the overflow output of the third counter, three The inputs of the first and second elements 2I-OR are connected to the direct outputs of the second and third triggers, respectively; the output of the null organ is connected to the input of the first pulse inhibiting block whose output is connected to the counting input of the fourth trigger; the information inputs of the bits of the third counter are inputs set the number of cycles of operation of the device.

Editor V.Danko

Compiled by O.Otradnov

Tehred V.Kadar Proofreader I.Musk

Order 1445/48 Draw 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

2.

Claims (1)

They must enter the counting input of the second claims subtracting counter 19 (FIG. 2o), describing its contents. ¹ At the moment of time corresponding to the zeroing of the second subtracting counter 19, the second decoder 21 is activated, the pulse from the output of which (Fig. 2p) returns the third trigger 23 to its original position O. Thus, a time-pulse signal is generated at the output of the indicated trigger 10 (Fig. 2n), as if simulating the second of the periodically repeating signals of the previous mode, which through the second element 2I-ILY 38 and the element OR 1J) 15 is fed to the first trigger 9 (Fig.2u) and the control input of the third key 6, setting it in the closed position and setting the sequence of operations characteristic of the first cycle 20 of the second cycle of the device. The third pulse of the zero-organ 8 (Fig. 2d) or the second from the output of block 31 (Fig. 3s), appearing at the output of the seventh element And 28 (Fig. 2k) and 25 fixing the end of the first measure of the second cycle of the device, passes through the third element And 24 and, entering the control input of the first subtracting counter 18, decides 30 to overwrite the contents of the first counter 16 in it, and also sets the second trigger 22 to position 1, at which the potential 1 from its direct output (Fig. 2p) opens the 35th element And 26, and the clock pulses of the generator 14 through this lement begins to flow to the counting input of the first subtracter counter 18 (Fig. Sc), describing the contents. 40 At the point in time corresponding to the zeroing of the first subtracting counter 18, the first decoder 20 is triggered, the pulse from the output of which (Fig.2t) returns the second trigger 22 to the initial 45 position 0. Thus, a time-pulse signal is generated at the output of this trigger (Fig. 2p), • as if simulating the second of the periodically repeating signals of the previous mode, which through the first element 2I-GSHI 37 and the OR element 10 is supplied to the first trigger 9 (Fig. 2u) and the control input of the first key 2 setting it in closed position 55 and, setting the sequence. · operations characteristic of the second cycle of the second cycle of the device.