SU1251324A1 - Analog-to-digital integrating converter with automatic selection of conversion range - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to increase the speed of the device. This is achieved in that a device containing two switches 1.2, an operational amplifier 3, a capacitor 5, a switch 6 key. Two comparison units 7.8, a reference voltage block 4, two RS-flip-flops 10.11, And element , a clock pulse generator 15, two counters 12,13, p-1 additional (accumulative) elements made on the capacitors 16, nl additional feedback keys 17, two decoder 18,19, n-1 additional keys. 2 Il. (C (L S taa d SP j

Description

i

The invention relates to the technique and can be but in adaptive measurements with a digital output in digital voltmeters with a practical choice of limits

FIG. 1 shows the fna scheme of the device; on the timing charts

The device contains n + 1 keys 1, a current-limiting element made on a resistor 2, an operational amplifier 3, a block 4 of reference voltages, a cumulative element made on a capacitor 5, a feedback key 6, blocks 7 and 8 of the comparison, a source 9 of a threshold voltage first 10 and second 11 RS triggers, first 12 and second 13 counters, element 14, generator 1 5 clock pulses, additional p-1 accumulation elements made on capacitors 1 fS, additional p-1 keys 1 7 feedback zi, second 18 and first 19 decoders.

The device works as follows.

In the initial state, the first 11 and second 12 V.5-triggers are in the zero state, keys 6 and 17 are closed, which corresponds to high levels of voltage on the control inputs of these keys (Fig 2), keys 1 are open. The voltage at the output of the operational amplifier 3 and the capacitors 5.16 is equal to 0. At the outputs of the first 12 and second 13 counters, there are signals corresponding to the code of the selected range and the code of the voltage being converted, obtained as a result of the last one before this conversion.

At the moment of time t ,, (Fig. 2), the Start impulse of the A / D converter arrives at the Start, which resets counters 12 and 13 to О. At the end of the pulse at time t, the first RS flip-flop 10 is set to 1 state, with the signal the inverse output closes the key 6, and the signal from the output of the element 14 opens the first key 1, and the converted voltage Uj is fed to the input of the operational amplifier 3. At the counting resolution input of the second counter 13 there appears a signal allowing this counter to count

five

0

The number of pulses arriving at the counting input from the output of the generator 15. In this case, the capacity of the counter 13 is chosen so that its full filling with the pulses of the generator 15 before overflow occurs during a time T equal to the base integration time of the converted signal Uj, Na the second input of the second decoder 18 receives the signal Log. 1, and the first inputs come from the output of the first counter 12 code zero. In accordance with the truth table, a signal Log appears on all outputs of the decoder 18. O and all additional keys 17 are opened. Thus, at time t, in the feedback of the operational amplifier 3, only one capacitor 5 is switched on and the output voltage of the operational amplifier 3 begins to change according to the law 1 U (t)

Rc7 j

and dt.

(I)

where R is the resistance of the resistor 2;

C - capacitor capacitance 5.

Over a period of time (t, -t), integration is performed with the shortest time constant. At time t (Fig. 2), the voltage Uj (t) reaches the value of the voltage of the source 9, At the same time, at the output of block 8, the signal 1 and the contents of the first counter 12 increase. with per unit. Changing the code at the output of the counter 12 will cause the occurrence of signal 1 at the first output of the decoder 18 and the closure of the first additional switch 17. At the same time, the first additional capacitor 16 (with capacitance C ,,) is connected in parallel with capacitor 5. The voltage at the output of the operational amplifier 3 due to the redistribution of the charges on the capacitances decreases abruptly to

u, (t ,,, (v)

Co y (t)

with + with.

s

(2)

Where

With

with „+ s,

 II to

- range switching factor;

the subscript, at t, means that this is the time t before the first additional key 17 triggers;

The subscript + corresponds to the time after the operation of the key 17.

Since the voltage Uj (t), block 8 returns to the initial state.

3

If we substitute (1) in (2), we get | .

(H --R (C: TcT) l4, dt. (3)

fu the voltage at the output of the operational amplifier at the time t has a value corresponding to the integration of the voltage U with a constant R- (,) since time t. The voltage at the integrator output will begin to change according to the law of 1 g.

s (t) - RccJTc, J m P "

t., t t. i. (four)

Thus, the converter goes to the second conversion range.

At the time “time t, the voltage at the output of the operational amplifier 3 will again reach the value, which will trigger the block 8 and the counter 12 will write the number 2. The second additional switch 17 will close and the voltage at the output of the operational amplifier 3 will begin to change. in this way 1

W () -Y () J,

at t t t.j, (5)

those. The converter has moved to the third range. . ,

 A similar switch will occur at time t, (Fig. 2). By the time the pulse T ends (time t), the output of the operational amplifier 3 will be

s (- (s: t5,

Uhl

RCCo + C, + C, + C.,) (6)

in the first counter 10, the number 3 will be written and it will show the code corresponding to the fourth conversion range.

At time tj (Fig. 2) the pulse from the output, the overflow of the counter 13 will set the second RS flip-flop 11 into one state, with the signal from the output of the And 14 element closing the first I- key, and the second input of the first decoder 19 s the direct output of the RS flip-flop 11 receives a single signal and the output of the decoder 19 corresponding to the range selected as a result of the conversion (the code from the output of the counter 9) appears a signal opening

3244

the corresponding key is 1. Thus, block 4 is connected to the integrator. In this example, since the fourth range was selected through

oo

resistor 2 will flow current equal to.

 The reference voltage has a sign opposite to the sign of the voltage being converted. Therefore, the voltage at the output of the op amp 3 will begin to fall.

Uj (t)

and

R (CO + s + s + s,)

+ 5 (t-t J at t t t.

(7)

J - -5 / f -g X -5

As soon as the voltage at the output of the operational amplifier 3 becomes equal to 0, the voltage at the output of the block 7 drops to a low level and sets the RS-flip-flops 10 and 11 to the zero state.

In this case, the second inputs of the decoders 18 and. 19, the signal O comes, the decoder 19 closes the corresponding switch 1, the input voltage of the output of the block 4 stops at the input of the operational amplifier 3. At the input The counting resolution of the second counter 3 from the direct output of the RS flip-flop 10 comes a signal that prohibits counting a pulse counter from generator 15. The code at the output of counter 3 corresponds to the pulse duration at the direct output of the second trigger 11, which is proportional to the voltage U to be converted, as can be seen from the following expression derived from (7)

40

Y11.TL

and.

(eight)

Thus, at the output of the ADC (outputs of the first 12 and second 13 counters), at the end of the conversion time, a code corresponding to the value U, is formed, while the outputs of the counter 12 will have the code of the conversion range number, and at the outputs of the counter 13 there will be a code of the value U inside selected range.

FIG. Figure 2 also shows the process of converting voltage And less than and starting from time t. In this case, the conversion is performed on the third range, while

g

year

and,

(9)

Thus, in an analog-to-digital converter with automatic selection of the conversion range, the selection of the range occurs simultaneously with the conversion, which improves the speed of the device.

Claims (1)

Invention Formula An analog-to-digital converter with automatic conversion range, containing a cumulative element made on a capacitor, a current limiting element made on a resistor, the first key, the input of which is an input bus, and the output combined with the output of the second key and connected to the first output the resistor is input the second switch is connected to the first output of the unit of the reference voltage, the second terminal of the resistor is connected to the inputs of the operational amplifier of the feedback switch and the first circuit of the condenser Ator, the second lining of which is combined with the outputs of the operational amplifier of the feedback switch key and connected by the first inputs of the first and second comparison blocks J the second input of the latter is a common bus, and the output is connected to the R inputs of the first and second RS triggers, the second input of the first comparison block connected to the output of the threshold voltage source, the S input of the first RS flip-flop is a Start bus, and the direct output is connected to the first input of the AND element, the first and second pulse counters, the outputs of the first pulse counter, are Vym output lines, clock pulse generator, characterized in that in order to improve performance, it dry introduced additional keys 1, n-1 pre 1polnitelnyh feedback keys, n-1 additional accumulating elements formed on capacitor where n is the number of transform ranges, two decoders, n-1 outputs of the first decoder are connected to the corresponding n-1 control inputs t and n-1 additional keys, the pth output of the first decoder is connected to the control input of the second key, the output of which is combined with the outputs of the n-1 additional keys, the inputs of which are connected to the corresponding second outputs of the voltage block, the first inputs of the first decoder are unified with the first inputs of the second - the decoder is connected to the outputs of the first pulse counter, the second input of the first decoder is connected to the direct output of the second short-circuit trigger, the inverse output of which is connected to the second input of the element I, the output to It is costly connected to the control input of the first key, the S input of the second RS flip-flop is connected to the overflow output of the second pulse counter, the outputs of which are the second output buses, and the counting input connected to the output of the clock generator, allowing the second pulse counter to be connected to the second the input of the second decoder and is connected to the forward output of the first RS trigger, the reset input of the first pulse counter is combined with the reset input of the second pulse counter and is a Start bus, and the count input of the first counter Pulse ika is connected to the output of the first comparator unit, the control inputs n-1 dopol feedback keys are connected to the corresponding outputs of the second decoder, outputs n − 1 are additional, feedback keys are combined with the output of the operational amplifier, and the input of each of the n – l additional feedback keys is connected via an additional capacitor to the input of the operational amplifier. Editor N. Slobod Nick Order 4426/58 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Compiled by A. Titov. Tehred L. Serdyukova. Corrector A. Obruchar