SU1233270A2 - Delaying device - Google Patents

Abstract

The invention relates to instrumentation technology and can be used in various automation and remote control devices. The purpose of the invention is to expand the dynamic range of the input signal delay by providing a linear voltage change over time - the drive capacitor against leakage currents. The device contains a pulse generator 1 connected through a coincidence element 2 to the counting input of the pulse counter 3 and the set zero input of the first trigger (TG) 4, the output of which is connected to the current generator 5, and the unit setting input to the pulse counter 3 output, capacitor 6 connected to the common bus, the output of the current generator 5 and the first input of the threshold cascade 7; key element 8, soybeans (Lte soo oo go -4 ho

Description

parallel to the capacitor 6, the second TG 9, connected by its input to the input bus, the output of the threshold stage 7 and the output bus of the device, and the output with the coincidence element 2 and the key element 8; ZDL 10, subtraction unit 11 and a group of valves 12, The output of unit 11 is connected to the control inputs of counter 3 via the appropriate valves. The transfer output of unit P The invention relates to instrumentation technology and can be used in various automation devices and telemechanics.

The purpose of the invention is to broaden the dynamic range of the delays in the signal by providing a linear change in voltage at a time & l setting the capacitor against leakage currents.

The drawing shows a structural diagram of the proposed device delay.,

The delay device contains a generator of 1 pulses, an element 2 connected via a counter to the counting input of counter 3 and pulses and a zero input input of the first trigger 4, the output of which is connected to the input of the current generator 5, and a unit installation input to the output of the pulse counter 3, a capacitor 6 , connected by one plate to the common busbar, and the second to the output of the current generator 5 and the first input of the threshold stage 7, the key element 8 connected in parallel to the capacitor 6, the second trigger 9 connected by the unit installation input to the input bus, at the zero setting, with the output of the threshold stage 7 and the device output bus, the output is connected to the control inputs of coincidence element 2 and key element 8, digital-analogue converter 10, subtraction unit 11 and valve group 12, outputs of subtraction unit 11 through

It is connected to the second inputs of the valves and to the input of the higher bit of the DAC 10. An additional DAC 13 and an analog subtraction unit 14 are also inserted into the device, through which the piecewise constant correction of the delay time5 is made associated with the change in the process of forming the capacitor 6 due to leakage currents. Il, 1.. Additional to auth. St. 720711.

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the corresponding gates are connected to the control inputs of the counter 3, the transfer output of the subtraction unit 11 is connected to the second inputs of the gates and to the high-level input of the digital-i analogue converter 10, the inputs of the sub-unit 11 and digital-analogue converter 10 inputs, besides the input the higher bit, are connected to the terminals of the delay setting j as well as the additional digital-to-analog converter 13 and the analog subtractor 14, the first and second inputs of the analog subtractor 14 are connected respectively to the outputs of the main 10 and auxiliary An additional 13 digital-to-analog converters, and the output to the second input of the threshold

cascade 7,.

The delay device operates as follows.

The required value of the input signal delay is formed in the proposed device in two stages. In the first stage, in a pulse-counting way, the coarse delay part is multiplied by the period of the model generator 1. The corresponding code is fed to the inputs of the digital subtraction unit 1I. In the second stage, using a linear voltage conversion method — the time of forming the exact part of the delay, which varies within a coarse quantization step. This conversion is performed using a threshold stage and a sawtooth generator consisting of

trigger 4, generator 5 current, capacitor. 6 and element 8, the voltage-time converter is controlled by a digital-to-analog converter 10, to which the lower bits of the digital equivalent of the interval being formed are applied. The uncertainty of the temporal position of the pulses of the reference generator 1 relative to the triggering ones is compensated in the device with noMomii of the same analog conversion units that in this case perform the function of the time-voltage converter.

The input signal sets the trigger 4 to one state, unlocks the coincidence element 2, and starts the line capacitor charge b from the normally-on current generator 5. The closest impulse of Generator 1 passes through the open element 2 coincidence and sets in one state trigger 4, interrupting the formation of sawtooth voltage on capacitor 6. From this moment also begins the counting of reference pulses by counter 3, When the number of pulses fixed by c4eT4kKOM 3 becomes equal to the code the outputs of the valves 12, the output pulse of the counter returns the trigger 4 to its initial state and re-starts the sawtooth voltage formation process, which continues until equality is reached on input dah of the threshold stage 7. At this point, the output signal of the device is formed and the trigger 9 returns to the initial state.

 Block 11 subtracts one from the coarse delay code value. In this case, the total duration of the sawtooth voltage on the capacitor does not exceed two oscillation periods of generator 1, the first of which relates to synchronization and the second to the stage of forming an exact delay. If the generated delay value t is less than or equal to the coarse delay step T, then the zero code enters the input of the counter 3, which ensures that the trigger 4 is turned off and the silt voltage on the capacitor 6 is continuously forming. In particular, at T, there is no signal on the run

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transferring the digital subtractor 1I; the high bit value of the first digital-to-analog converter is I, and the sawtooth voltage portion corresponding to a delay of 1-2 oscillation periods of the oscillator 1 is used. If T is due to the transfer signal of the digital subtracting unit 11, the zero code arrives at the input of the counter 3, and the output of the digital-analog converter 10 sets the voltage corresponding to the delay within the oscillation period of the generator I (high-order digital-to-analog converter 10 is turned off)

Using the analog block 14, the piecewise-pos. This correction of the delay setting error is associated with the change in the process of its formation of the potential of the capacitor 6 due to the presence of leakage currents. The entire range of delays is divided into a number of sections in which some constant voltage is subtracted from the output voltage of the D / A converter 10 such that the error of the device due to charge leakage from the capacitor 6 does not exceed half of the required quantization step of the time scale. These corrective actions are formed with the help of an additional digital-to-analog converter 13, the number of bits of which corresponds to the required degree of expansion of the dynamic range of delays, as compared with the case of no correction of the error due to the leakage of charge from the storage capacitor.

Claims (1)

Invention Formula Delay device auth. St. No. 720711, distinguished by the fact that, in order to expand the dynamic range of input delays signal, between the output of the digital-to-analog converter and the second input of the threshold cascade, an analog subtractor is connected, another input of which is connected to the output of the additional digital-analog converter, the inputs to which are connected to corresponding outputs of the subtraction unit.